1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/os_misc.h"
26 #include "pipe/p_defines.h"
27 #include "pipe/p_screen.h"
28 #include "pipe/p_state.h"
29
30 #include "util/u_debug.h"
31 #include "util/u_memory.h"
32 #include "util/format/u_format.h"
33 #include "util/u_hash_table.h"
34 #include "util/u_screen.h"
35 #include "util/u_transfer_helper.h"
36 #include "util/perf/cpu_trace.h"
37 #include "util/ralloc.h"
38
39 #include <xf86drm.h>
40 #include "drm-uapi/drm_fourcc.h"
41 #include "drm-uapi/vc4_drm.h"
42 #include "vc4_screen.h"
43 #include "vc4_context.h"
44 #include "vc4_resource.h"
45
46 static const struct debug_named_value vc4_debug_options[] = {
47 { "cl", VC4_DEBUG_CL,
48 "Dump command list during creation" },
49 { "surf", VC4_DEBUG_SURFACE,
50 "Dump surface layouts" },
51 { "qpu", VC4_DEBUG_QPU,
52 "Dump generated QPU instructions" },
53 { "qir", VC4_DEBUG_QIR,
54 "Dump QPU IR during program compile" },
55 { "nir", VC4_DEBUG_NIR,
56 "Dump NIR during program compile" },
57 { "tgsi", VC4_DEBUG_TGSI,
58 "Dump TGSI during program compile" },
59 { "shaderdb", VC4_DEBUG_SHADERDB,
60 "Dump program compile information for shader-db analysis" },
61 { "perf", VC4_DEBUG_PERF,
62 "Print during performance-related events" },
63 { "norast", VC4_DEBUG_NORAST,
64 "Skip actual hardware execution of commands" },
65 { "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
66 "Flush after each draw call" },
67 { "always_sync", VC4_DEBUG_ALWAYS_SYNC,
68 "Wait for finish after each flush" },
69 #ifdef USE_VC4_SIMULATOR
70 { "dump", VC4_DEBUG_DUMP,
71 "Write a GPU command stream trace file" },
72 #endif
73 DEBUG_NAMED_VALUE_END
74 };
75
76 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", vc4_debug_options, 0)
77 uint32_t vc4_mesa_debug;
78
79 static const char *
vc4_screen_get_name(struct pipe_screen * pscreen)80 vc4_screen_get_name(struct pipe_screen *pscreen)
81 {
82 struct vc4_screen *screen = vc4_screen(pscreen);
83
84 if (!screen->name) {
85 screen->name = ralloc_asprintf(screen,
86 "VC4 V3D %d.%d",
87 screen->v3d_ver / 10,
88 screen->v3d_ver % 10);
89 }
90
91 return screen->name;
92 }
93
94 static const char *
vc4_screen_get_vendor(struct pipe_screen * pscreen)95 vc4_screen_get_vendor(struct pipe_screen *pscreen)
96 {
97 return "Broadcom";
98 }
99
100 static void
vc4_screen_destroy(struct pipe_screen * pscreen)101 vc4_screen_destroy(struct pipe_screen *pscreen)
102 {
103 struct vc4_screen *screen = vc4_screen(pscreen);
104
105 _mesa_hash_table_destroy(screen->bo_handles, NULL);
106 vc4_bufmgr_destroy(pscreen);
107 slab_destroy_parent(&screen->transfer_pool);
108 if (screen->ro)
109 screen->ro->destroy(screen->ro);
110
111 #ifdef USE_VC4_SIMULATOR
112 vc4_simulator_destroy(screen);
113 #endif
114
115 u_transfer_helper_destroy(pscreen->transfer_helper);
116
117 close(screen->fd);
118 ralloc_free(pscreen);
119 }
120
121 static bool
vc4_has_feature(struct vc4_screen * screen,uint32_t feature)122 vc4_has_feature(struct vc4_screen *screen, uint32_t feature)
123 {
124 struct drm_vc4_get_param p = {
125 .param = feature,
126 };
127 int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &p);
128
129 if (ret != 0)
130 return false;
131
132 return p.value;
133 }
134
135 static int
vc4_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)136 vc4_screen_get_shader_param(struct pipe_screen *pscreen,
137 enum pipe_shader_type shader,
138 enum pipe_shader_cap param)
139 {
140 if (shader != PIPE_SHADER_VERTEX &&
141 shader != PIPE_SHADER_FRAGMENT) {
142 return 0;
143 }
144
145 /* this is probably not totally correct.. but it's a start: */
146 switch (param) {
147 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
148 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
149 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
150 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
151 return 16384;
152
153 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
154 return vc4_screen(pscreen)->has_control_flow;
155
156 case PIPE_SHADER_CAP_MAX_INPUTS:
157 return 8;
158 case PIPE_SHADER_CAP_MAX_OUTPUTS:
159 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
160 case PIPE_SHADER_CAP_MAX_TEMPS:
161 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
162 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
163 return 16 * 1024 * sizeof(float);
164 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
165 return 1;
166 case PIPE_SHADER_CAP_CONT_SUPPORTED:
167 return 0;
168 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
169 return 0;
170 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
171 return 1;
172 case PIPE_SHADER_CAP_SUBROUTINES:
173 return 0;
174 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
175 return 0;
176 case PIPE_SHADER_CAP_INTEGERS:
177 return 1;
178 case PIPE_SHADER_CAP_INT64_ATOMICS:
179 case PIPE_SHADER_CAP_FP16:
180 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
181 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
182 case PIPE_SHADER_CAP_INT16:
183 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
184 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
185 return 0;
186 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
187 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
188 return VC4_MAX_TEXTURE_SAMPLERS;
189 case PIPE_SHADER_CAP_SUPPORTED_IRS:
190 return 1 << PIPE_SHADER_IR_NIR;
191 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
192 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
193 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
194 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
195 return 0;
196 default:
197 fprintf(stderr, "unknown shader param %d\n", param);
198 return 0;
199 }
200 return 0;
201 }
202
203 static void
vc4_init_screen_caps(struct vc4_screen * screen)204 vc4_init_screen_caps(struct vc4_screen *screen)
205 {
206 struct pipe_caps *caps = (struct pipe_caps *)&screen->base.caps;
207
208 u_init_pipe_screen_caps(&screen->base, 1);
209
210 /* Supported features (boolean caps). */
211 caps->vertex_color_unclamped = true;
212 caps->fragment_color_clamped = true;
213 caps->npot_textures = true;
214 caps->blend_equation_separate = true;
215 caps->texture_multisample = true;
216 caps->texture_swizzle = true;
217 caps->texture_barrier = true;
218 caps->tgsi_texcoord = true;
219
220 caps->native_fence_fd = screen->has_syncobj;
221
222 caps->tile_raster_order =
223 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER);
224
225 caps->fs_coord_origin_upper_left = true;
226 caps->fs_coord_pixel_center_half_integer = true;
227 caps->fs_face_is_integer_sysval = true;
228
229 caps->mixed_framebuffer_sizes = true;
230 caps->mixed_color_depth_bits = true;
231
232 /* Texturing. */
233 caps->max_texture_2d_size = 2048;
234 caps->max_texture_cube_levels = VC4_MAX_MIP_LEVELS;
235 caps->max_texture_3d_levels = 0;
236
237 caps->max_varyings = 8;
238
239 caps->vendor_id = 0x14E4;
240
241 uint64_t system_memory;
242 caps->video_memory = os_get_total_physical_memory(&system_memory) ?
243 system_memory >> 20 : 0;
244
245 caps->uma = true;
246
247 caps->alpha_test = false;
248 caps->vertex_color_clamped = false;
249 caps->two_sided_color = false;
250 caps->texrect = false;
251 caps->image_store_formatted = false;
252 caps->clip_planes = 0;
253
254 caps->supported_prim_modes = screen->prim_types;
255
256 caps->min_line_width =
257 caps->min_line_width_aa =
258 caps->min_point_size =
259 caps->min_point_size_aa = 1;
260
261 caps->point_size_granularity =
262 caps->line_width_granularity = 0.1;
263
264 caps->max_line_width =
265 caps->max_line_width_aa = 32;
266
267 caps->max_point_size =
268 caps->max_point_size_aa = 512.0f;
269 }
270
271 static bool
vc4_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)272 vc4_screen_is_format_supported(struct pipe_screen *pscreen,
273 enum pipe_format format,
274 enum pipe_texture_target target,
275 unsigned sample_count,
276 unsigned storage_sample_count,
277 unsigned usage)
278 {
279 struct vc4_screen *screen = vc4_screen(pscreen);
280
281 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
282 return false;
283
284 if (sample_count > 1 && sample_count != VC4_MAX_SAMPLES)
285 return false;
286
287 if (target >= PIPE_MAX_TEXTURE_TYPES) {
288 return false;
289 }
290
291 if (usage & PIPE_BIND_VERTEX_BUFFER) {
292 switch (format) {
293 case PIPE_FORMAT_R32G32B32A32_FLOAT:
294 case PIPE_FORMAT_R32G32B32_FLOAT:
295 case PIPE_FORMAT_R32G32_FLOAT:
296 case PIPE_FORMAT_R32_FLOAT:
297 case PIPE_FORMAT_R32G32B32A32_SNORM:
298 case PIPE_FORMAT_R32G32B32_SNORM:
299 case PIPE_FORMAT_R32G32_SNORM:
300 case PIPE_FORMAT_R32_SNORM:
301 case PIPE_FORMAT_R32G32B32A32_SSCALED:
302 case PIPE_FORMAT_R32G32B32_SSCALED:
303 case PIPE_FORMAT_R32G32_SSCALED:
304 case PIPE_FORMAT_R32_SSCALED:
305 case PIPE_FORMAT_R16G16B16A16_UNORM:
306 case PIPE_FORMAT_R16G16B16_UNORM:
307 case PIPE_FORMAT_R16G16_UNORM:
308 case PIPE_FORMAT_R16_UNORM:
309 case PIPE_FORMAT_R16G16B16A16_SNORM:
310 case PIPE_FORMAT_R16G16B16_SNORM:
311 case PIPE_FORMAT_R16G16_SNORM:
312 case PIPE_FORMAT_R16_SNORM:
313 case PIPE_FORMAT_R16G16B16A16_USCALED:
314 case PIPE_FORMAT_R16G16B16_USCALED:
315 case PIPE_FORMAT_R16G16_USCALED:
316 case PIPE_FORMAT_R16_USCALED:
317 case PIPE_FORMAT_R16G16B16A16_SSCALED:
318 case PIPE_FORMAT_R16G16B16_SSCALED:
319 case PIPE_FORMAT_R16G16_SSCALED:
320 case PIPE_FORMAT_R16_SSCALED:
321 case PIPE_FORMAT_R8G8B8A8_UNORM:
322 case PIPE_FORMAT_R8G8B8_UNORM:
323 case PIPE_FORMAT_R8G8_UNORM:
324 case PIPE_FORMAT_R8_UNORM:
325 case PIPE_FORMAT_R8G8B8A8_SNORM:
326 case PIPE_FORMAT_R8G8B8_SNORM:
327 case PIPE_FORMAT_R8G8_SNORM:
328 case PIPE_FORMAT_R8_SNORM:
329 case PIPE_FORMAT_R8G8B8A8_USCALED:
330 case PIPE_FORMAT_R8G8B8_USCALED:
331 case PIPE_FORMAT_R8G8_USCALED:
332 case PIPE_FORMAT_R8_USCALED:
333 case PIPE_FORMAT_R8G8B8A8_SSCALED:
334 case PIPE_FORMAT_R8G8B8_SSCALED:
335 case PIPE_FORMAT_R8G8_SSCALED:
336 case PIPE_FORMAT_R8_SSCALED:
337 break;
338 default:
339 return false;
340 }
341 }
342
343 if ((usage & PIPE_BIND_RENDER_TARGET) &&
344 !vc4_rt_format_supported(format)) {
345 return false;
346 }
347
348 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
349 (!vc4_tex_format_supported(format) ||
350 (format == PIPE_FORMAT_ETC1_RGB8 && !screen->has_etc1))) {
351 return false;
352 }
353
354 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
355 format != PIPE_FORMAT_S8_UINT_Z24_UNORM &&
356 format != PIPE_FORMAT_X8Z24_UNORM) {
357 return false;
358 }
359
360 if ((usage & PIPE_BIND_INDEX_BUFFER) &&
361 format != PIPE_FORMAT_R8_UINT &&
362 format != PIPE_FORMAT_R16_UINT) {
363 return false;
364 }
365
366 return true;
367 }
368
vc4_get_modifiers(struct pipe_screen * pscreen,int * num)369 static const uint64_t *vc4_get_modifiers(struct pipe_screen *pscreen, int *num)
370 {
371 struct vc4_screen *screen = vc4_screen(pscreen);
372 static const uint64_t all_modifiers[] = {
373 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
374 DRM_FORMAT_MOD_LINEAR,
375 };
376 int m;
377
378 /* We support both modifiers (tiled and linear) for all sampler
379 * formats, but if we don't have the DRM_VC4_GET_TILING ioctl
380 * we shouldn't advertise the tiled formats.
381 */
382 if (screen->has_tiling_ioctl) {
383 m = 0;
384 *num = 2;
385 } else{
386 m = 1;
387 *num = 1;
388 }
389
390 return &all_modifiers[m];
391 }
392
393 static void
vc4_screen_query_dmabuf_modifiers(struct pipe_screen * pscreen,enum pipe_format format,int max,uint64_t * modifiers,unsigned int * external_only,int * count)394 vc4_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
395 enum pipe_format format, int max,
396 uint64_t *modifiers,
397 unsigned int *external_only,
398 int *count)
399 {
400 const uint64_t *available_modifiers;
401 int i;
402 bool tex_will_lower;
403 int num_modifiers;
404
405 available_modifiers = vc4_get_modifiers(pscreen, &num_modifiers);
406
407 if (!modifiers) {
408 *count = num_modifiers;
409 return;
410 }
411
412 *count = MIN2(max, num_modifiers);
413 tex_will_lower = !vc4_tex_format_supported(format);
414 for (i = 0; i < *count; i++) {
415 modifiers[i] = available_modifiers[i];
416 if (external_only)
417 external_only[i] = tex_will_lower;
418 }
419 }
420
421 static bool
vc4_screen_is_dmabuf_modifier_supported(struct pipe_screen * pscreen,uint64_t modifier,enum pipe_format format,bool * external_only)422 vc4_screen_is_dmabuf_modifier_supported(struct pipe_screen *pscreen,
423 uint64_t modifier,
424 enum pipe_format format,
425 bool *external_only)
426 {
427 const uint64_t *available_modifiers;
428 int i, num_modifiers;
429
430 available_modifiers = vc4_get_modifiers(pscreen, &num_modifiers);
431
432 for (i = 0; i < num_modifiers; i++) {
433 if (modifier == available_modifiers[i]) {
434 if (external_only)
435 *external_only = !vc4_tex_format_supported(format);
436
437 return true;
438 }
439 }
440
441 return false;
442 }
443
444 static bool
vc4_get_chip_info(struct vc4_screen * screen)445 vc4_get_chip_info(struct vc4_screen *screen)
446 {
447 struct drm_vc4_get_param ident0 = {
448 .param = DRM_VC4_PARAM_V3D_IDENT0,
449 };
450 struct drm_vc4_get_param ident1 = {
451 .param = DRM_VC4_PARAM_V3D_IDENT1,
452 };
453 int ret;
454
455 ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
456 if (ret != 0) {
457 if (errno == EINVAL) {
458 /* Backwards compatibility with 2835 kernels which
459 * only do V3D 2.1.
460 */
461 screen->v3d_ver = 21;
462 return true;
463 } else {
464 fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
465 strerror(errno));
466 return false;
467 }
468 }
469 ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
470 if (ret != 0) {
471 fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
472 strerror(errno));
473 return false;
474 }
475
476 uint32_t major = (ident0.value >> 24) & 0xff;
477 uint32_t minor = (ident1.value >> 0) & 0xf;
478 screen->v3d_ver = major * 10 + minor;
479
480 if (screen->v3d_ver != 21 && screen->v3d_ver != 26) {
481 fprintf(stderr,
482 "V3D %d.%d not supported by this version of Mesa.\n",
483 screen->v3d_ver / 10,
484 screen->v3d_ver % 10);
485 return false;
486 }
487
488 return true;
489 }
490
491 static int
vc4_screen_get_fd(struct pipe_screen * pscreen)492 vc4_screen_get_fd(struct pipe_screen *pscreen)
493 {
494 struct vc4_screen *screen = vc4_screen(pscreen);
495
496 return screen->fd;
497 }
498
499 struct pipe_screen *
vc4_screen_create(int fd,const struct pipe_screen_config * config,struct renderonly * ro)500 vc4_screen_create(int fd, const struct pipe_screen_config *config,
501 struct renderonly *ro)
502 {
503 struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
504 uint64_t syncobj_cap = 0;
505 struct pipe_screen *pscreen;
506 int err;
507
508 util_cpu_trace_init();
509
510 pscreen = &screen->base;
511
512 pscreen->destroy = vc4_screen_destroy;
513 pscreen->get_screen_fd = vc4_screen_get_fd;
514 pscreen->get_shader_param = vc4_screen_get_shader_param;
515 pscreen->context_create = vc4_context_create;
516 pscreen->is_format_supported = vc4_screen_is_format_supported;
517
518 screen->fd = fd;
519 screen->ro = ro;
520
521 list_inithead(&screen->bo_cache.time_list);
522 (void) mtx_init(&screen->bo_handles_mutex, mtx_plain);
523 screen->bo_handles = util_hash_table_create_ptr_keys();
524
525 screen->has_control_flow =
526 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_BRANCHES);
527 screen->has_etc1 =
528 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_ETC1);
529 screen->has_threaded_fs =
530 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_THREADED_FS);
531 screen->has_madvise =
532 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_MADVISE);
533 screen->has_perfmon_ioctl =
534 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_PERFMON);
535
536 err = drmGetCap(fd, DRM_CAP_SYNCOBJ, &syncobj_cap);
537 if (err == 0 && syncobj_cap)
538 screen->has_syncobj = true;
539
540 if (!vc4_get_chip_info(screen))
541 goto fail;
542
543 slab_create_parent(&screen->transfer_pool, sizeof(struct vc4_transfer), 16);
544
545 vc4_fence_screen_init(screen);
546
547 vc4_mesa_debug = debug_get_option_vc4_debug();
548
549 #ifdef USE_VC4_SIMULATOR
550 vc4_simulator_init(screen);
551 #endif
552
553 vc4_resource_screen_init(pscreen);
554
555 pscreen->get_name = vc4_screen_get_name;
556 pscreen->get_vendor = vc4_screen_get_vendor;
557 pscreen->get_device_vendor = vc4_screen_get_vendor;
558 pscreen->get_compiler_options = vc4_screen_get_compiler_options;
559 pscreen->query_dmabuf_modifiers = vc4_screen_query_dmabuf_modifiers;
560 pscreen->is_dmabuf_modifier_supported = vc4_screen_is_dmabuf_modifier_supported;
561
562 if (screen->has_perfmon_ioctl) {
563 pscreen->get_driver_query_group_info = vc4_get_driver_query_group_info;
564 pscreen->get_driver_query_info = vc4_get_driver_query_info;
565 }
566
567 /* Generate the bitmask of supported draw primitives. */
568 screen->prim_types = BITFIELD_BIT(MESA_PRIM_POINTS) |
569 BITFIELD_BIT(MESA_PRIM_LINES) |
570 BITFIELD_BIT(MESA_PRIM_LINE_LOOP) |
571 BITFIELD_BIT(MESA_PRIM_LINE_STRIP) |
572 BITFIELD_BIT(MESA_PRIM_TRIANGLES) |
573 BITFIELD_BIT(MESA_PRIM_TRIANGLE_STRIP) |
574 BITFIELD_BIT(MESA_PRIM_TRIANGLE_FAN);
575
576 vc4_init_screen_caps(screen);
577
578 return pscreen;
579
580 fail:
581 close(fd);
582 ralloc_free(pscreen);
583 return NULL;
584 }
585