1 // Copyright 2019 The Fuchsia Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 //
6 //
7 //
8
9 #include "barrier.h"
10 #include "vulkan/runtime/vk_device.h"
11 #include "vulkan/runtime/vk_command_buffer.h"
12
13 //
14 //
15 //
16
17 void
vk_barrier_compute_w_to_compute_r(VkCommandBuffer cb)18 vk_barrier_compute_w_to_compute_r(VkCommandBuffer cb)
19 {
20 VK_FROM_HANDLE(vk_command_buffer, cmd_buffer, cb);
21 const struct vk_device_dispatch_table *disp =
22 &cmd_buffer->base.device->dispatch_table;
23
24 static VkMemoryBarrier const mb = {
25
26 .sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
27 .pNext = NULL,
28 .srcAccessMask = VK_ACCESS_SHADER_WRITE_BIT,
29 .dstAccessMask = VK_ACCESS_SHADER_READ_BIT
30 };
31
32 disp->CmdPipelineBarrier(cb,
33 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
34 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
35 0,
36 1,
37 &mb,
38 0,
39 NULL,
40 0,
41 NULL);
42 }
43
44 //
45 //
46 //
47
48 void
vk_barrier_compute_w_to_transfer_r(VkCommandBuffer cb)49 vk_barrier_compute_w_to_transfer_r(VkCommandBuffer cb)
50 {
51 VK_FROM_HANDLE(vk_command_buffer, cmd_buffer, cb);
52 const struct vk_device_dispatch_table *disp =
53 &cmd_buffer->base.device->dispatch_table;
54
55 static VkMemoryBarrier const mb = {
56
57 .sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
58 .pNext = NULL,
59 .srcAccessMask = VK_ACCESS_SHADER_WRITE_BIT,
60 .dstAccessMask = VK_ACCESS_TRANSFER_READ_BIT
61 };
62
63 disp->CmdPipelineBarrier(cb,
64 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
65 VK_PIPELINE_STAGE_TRANSFER_BIT,
66 0,
67 1,
68 &mb,
69 0,
70 NULL,
71 0,
72 NULL);
73 }
74
75 //
76 //
77 //
78
79 void
vk_barrier_transfer_w_to_compute_r(VkCommandBuffer cb)80 vk_barrier_transfer_w_to_compute_r(VkCommandBuffer cb)
81 {
82 VK_FROM_HANDLE(vk_command_buffer, cmd_buffer, cb);
83 const struct vk_device_dispatch_table *disp =
84 &cmd_buffer->base.device->dispatch_table;
85
86 static VkMemoryBarrier const mb = {
87
88 .sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
89 .pNext = NULL,
90 .srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT,
91 .dstAccessMask = VK_ACCESS_SHADER_READ_BIT
92 };
93
94 disp->CmdPipelineBarrier(cb,
95 VK_PIPELINE_STAGE_TRANSFER_BIT,
96 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
97 0,
98 1,
99 &mb,
100 0,
101 NULL,
102 0,
103 NULL);
104 }
105
106 //
107 //
108 //
109
110 void
vk_barrier_transfer_w_to_compute_w(VkCommandBuffer cb)111 vk_barrier_transfer_w_to_compute_w(VkCommandBuffer cb)
112 {
113 VK_FROM_HANDLE(vk_command_buffer, cmd_buffer, cb);
114 const struct vk_device_dispatch_table *disp =
115 &cmd_buffer->base.device->dispatch_table;
116
117 static VkMemoryBarrier const mb = {
118
119 .sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
120 .pNext = NULL,
121 .srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT,
122 .dstAccessMask = VK_ACCESS_SHADER_WRITE_BIT
123 };
124
125 disp->CmdPipelineBarrier(cb,
126 VK_PIPELINE_STAGE_TRANSFER_BIT,
127 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
128 0,
129 1,
130 &mb,
131 0,
132 NULL,
133 0,
134 NULL);
135 }
136
137 //
138 //
139 //
140
141 void
vk_barrier_compute_w_to_indirect_compute_r(VkCommandBuffer cb)142 vk_barrier_compute_w_to_indirect_compute_r(VkCommandBuffer cb)
143 {
144 VK_FROM_HANDLE(vk_command_buffer, cmd_buffer, cb);
145 const struct vk_device_dispatch_table *disp =
146 &cmd_buffer->base.device->dispatch_table;
147
148 static VkMemoryBarrier const mb = {
149
150 .sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
151 .pNext = NULL,
152 .srcAccessMask = VK_ACCESS_SHADER_WRITE_BIT,
153 .dstAccessMask = VK_ACCESS_INDIRECT_COMMAND_READ_BIT | //
154 VK_ACCESS_SHADER_READ_BIT
155 };
156
157 disp->CmdPipelineBarrier(cb,
158 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
159 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT | VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
160 0,
161 1,
162 &mb,
163 0,
164 NULL,
165 0,
166 NULL);
167 }
168
169 //
170 //
171 //
172
173 void
vk_barrier_transfer_w_compute_w_to_transfer_r(VkCommandBuffer cb)174 vk_barrier_transfer_w_compute_w_to_transfer_r(VkCommandBuffer cb)
175 {
176 VK_FROM_HANDLE(vk_command_buffer, cmd_buffer, cb);
177 const struct vk_device_dispatch_table *disp =
178 &cmd_buffer->base.device->dispatch_table;
179
180 static VkMemoryBarrier const mb = {
181
182 .sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
183 .pNext = NULL,
184 .srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT | //
185 VK_ACCESS_SHADER_WRITE_BIT,
186 .dstAccessMask = VK_ACCESS_TRANSFER_READ_BIT
187 };
188
189 disp->CmdPipelineBarrier(cb,
190 VK_PIPELINE_STAGE_TRANSFER_BIT | VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
191 VK_PIPELINE_STAGE_TRANSFER_BIT,
192 0,
193 1,
194 &mb,
195 0,
196 NULL,
197 0,
198 NULL);
199 }
200
201 //
202 //
203 //
204
205 void
vk_barrier_compute_w_to_host_r(VkCommandBuffer cb)206 vk_barrier_compute_w_to_host_r(VkCommandBuffer cb)
207 {
208 VK_FROM_HANDLE(vk_command_buffer, cmd_buffer, cb);
209 const struct vk_device_dispatch_table *disp =
210 &cmd_buffer->base.device->dispatch_table;
211
212 static VkMemoryBarrier const mb = {
213
214 .sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
215 .pNext = NULL,
216 .srcAccessMask = VK_ACCESS_SHADER_WRITE_BIT,
217 .dstAccessMask = VK_ACCESS_HOST_READ_BIT
218 };
219
220 disp->CmdPipelineBarrier(cb,
221 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
222 VK_PIPELINE_STAGE_HOST_BIT,
223 0,
224 1,
225 &mb,
226 0,
227 NULL,
228 0,
229 NULL);
230 }
231
232 //
233 //
234 //
235
236 void
vk_barrier_transfer_w_to_host_r(VkCommandBuffer cb)237 vk_barrier_transfer_w_to_host_r(VkCommandBuffer cb)
238 {
239 VK_FROM_HANDLE(vk_command_buffer, cmd_buffer, cb);
240 const struct vk_device_dispatch_table *disp =
241 &cmd_buffer->base.device->dispatch_table;
242
243 static VkMemoryBarrier const mb = {
244
245 .sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
246 .pNext = NULL,
247 .srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT,
248 .dstAccessMask = VK_ACCESS_HOST_READ_BIT
249 };
250
251 disp->CmdPipelineBarrier(cb,
252 VK_PIPELINE_STAGE_TRANSFER_BIT,
253 VK_PIPELINE_STAGE_HOST_BIT,
254 0,
255 1,
256 &mb,
257 0,
258 NULL,
259 0,
260 NULL);
261 }
262
263 //
264 //
265 //
266
267 void
vk_memory_barrier(VkCommandBuffer cb,VkPipelineStageFlags src_stage,VkAccessFlags src_mask,VkPipelineStageFlags dst_stage,VkAccessFlags dst_mask)268 vk_memory_barrier(VkCommandBuffer cb,
269 VkPipelineStageFlags src_stage,
270 VkAccessFlags src_mask,
271 VkPipelineStageFlags dst_stage,
272 VkAccessFlags dst_mask)
273 {
274 VK_FROM_HANDLE(vk_command_buffer, cmd_buffer, cb);
275 const struct vk_device_dispatch_table *disp =
276 &cmd_buffer->base.device->dispatch_table;
277
278 VkMemoryBarrier const mb = { .sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
279 .pNext = NULL,
280 .srcAccessMask = src_mask,
281 .dstAccessMask = dst_mask };
282
283 disp->CmdPipelineBarrier(cb, src_stage, dst_stage, 0, 1, &mb, 0, NULL, 0, NULL);
284 }
285
286 //
287 //
288 //
289
290 void
vk_barrier_debug(VkCommandBuffer cb)291 vk_barrier_debug(VkCommandBuffer cb)
292 {
293 VK_FROM_HANDLE(vk_command_buffer, cmd_buffer, cb);
294 const struct vk_device_dispatch_table *disp =
295 &cmd_buffer->base.device->dispatch_table;
296
297 static VkMemoryBarrier const mb = {
298
299 .sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
300 .pNext = NULL,
301 .srcAccessMask = VK_ACCESS_INDIRECT_COMMAND_READ_BIT | //
302 VK_ACCESS_INDEX_READ_BIT | //
303 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT | //
304 VK_ACCESS_UNIFORM_READ_BIT | //
305 VK_ACCESS_INPUT_ATTACHMENT_READ_BIT | //
306 VK_ACCESS_SHADER_READ_BIT | //
307 VK_ACCESS_SHADER_WRITE_BIT | //
308 VK_ACCESS_COLOR_ATTACHMENT_READ_BIT | //
309 VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT | //
310 VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT | //
311 VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT | //
312 VK_ACCESS_TRANSFER_READ_BIT | //
313 VK_ACCESS_TRANSFER_WRITE_BIT | //
314 VK_ACCESS_HOST_READ_BIT | //
315 VK_ACCESS_HOST_WRITE_BIT,
316 .dstAccessMask = VK_ACCESS_INDIRECT_COMMAND_READ_BIT | //
317 VK_ACCESS_INDEX_READ_BIT | //
318 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT | //
319 VK_ACCESS_UNIFORM_READ_BIT | //
320 VK_ACCESS_INPUT_ATTACHMENT_READ_BIT | //
321 VK_ACCESS_SHADER_READ_BIT | //
322 VK_ACCESS_SHADER_WRITE_BIT | //
323 VK_ACCESS_COLOR_ATTACHMENT_READ_BIT | //
324 VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT | //
325 VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT | //
326 VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT | //
327 VK_ACCESS_TRANSFER_READ_BIT | //
328 VK_ACCESS_TRANSFER_WRITE_BIT | //
329 VK_ACCESS_HOST_READ_BIT | //
330 VK_ACCESS_HOST_WRITE_BIT
331 };
332
333 disp->CmdPipelineBarrier(cb,
334 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
335 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
336 0,
337 1,
338 &mb,
339 0,
340 NULL,
341 0,
342 NULL);
343 }
344
345 //
346 //
347 //
348