1 /* Copyright 2022 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 #pragma once 25 #include "vpe_command.h" 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 /*************************** 31 * VPE Descriptor 32 ***************************/ 33 #define VPE_DESC_CD__SHIFT 16 34 #define VPE_DESC_CD_MASK 0x000F0000 35 36 #define VPE_DESC_ADDR__SHIFT 32 37 #define VPE_DESC_HIGH_ADDR_MASK 0xFFFFFFFF00000000 38 39 /* The lowest bits are reuse and tmz as bit 1 and bit 0. 40 Smibs will substract the address with emb gpuva to 41 get offset and then reuse bit will be preserved 42 So as long as the embedded buffer is allocated 43 at correct alignment (currently low addr is [31:2] 44 which means we need a 4 byte(2 bit) alignment), 45 the offset generated will still cover the 46 reuse bit as part of it. 47 Ex : Address : 0x200036 GPU Virtual Address : 0x200000 48 offset is 0x36 which keeps the reuse bit */ 49 #define VPE_DESC_LOW_ADDR_MASK 0x00000000FFFFFFFF 50 #define VPE_DESC_REUSE_TMZ_MASK 0x0000000000000003 51 52 #define VPE_DESC_NUM_CONFIG_DESCRIPTOR__SHIFT 0 53 #define VPE_DESC_NUM_CONFIG_DESCRIPTOR_MASK 0x000000FF 54 55 #define VPE_DESC_REUSE__MASK 0x00000002 56 57 #define VPE_DESC_CMD_HEADER(cd) \ 58 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPE_DESC, 0) | (((cd) << VPE_DESC_CD__SHIFT) & VPE_DESC_CD_MASK)) 59 60 /*************************** 61 * VPE Plane Config 62 ***************************/ 63 enum VPE_PLANE_CFG_SUBOP { 64 VPE_PLANE_CFG_SUBOP_1_TO_1 = 0x0, 65 VPE_PLANE_CFG_SUBOP_2_TO_1 = 0x1, 66 VPE_PLANE_CFG_SUBOP_2_TO_2 = 0x2 67 }; 68 69 #define VPE_PLANE_CFG_ONE_PLANE 0 70 #define VPE_PLANE_CFG_TWO_PLANES 1 71 72 #define VPE_PLANE_CFG_NPS0__SHIFT 16 73 #define VPE_PLANE_CFG_NPS0_MASK 0x00030000 74 75 #define VPE_PLANE_CFG_NPD0__SHIFT 18 76 #define VPE_PLANE_CFG_NPD0_MASK 0x000C0000 77 78 #define VPE_PLANE_CFG_NPS1__SHIFT 20 79 #define VPE_PLANE_CFG_NPS1_MASK 0x00300000 80 81 #define VPE_PLANE_CFG_NPD1__SHIFT 22 82 #define VPE_PLANE_CFG_NPD1_MASK 0x00C00000 83 84 #define VPE_PLANE_CFG_TMZ__SHIFT 16 85 #define VPE_PLANE_CFG_TMZ_MASK 0x00010000 86 87 #define VPE_PLANE_CFG_SWIZZLE_MODE__SHIFT 3 88 #define VPE_PLANE_CFG_SWIZZLE_MODE_MASK 0x000000F8 89 90 #define VPE_PLANE_CFG_ROTATION__SHIFT 0 91 #define VPE_PLANE_CFG_ROTATION_MASK 0x00000003 92 93 #define VPE_PLANE_CFG_MIRROR__SHIFT 0 94 #define VPE_PLANE_CFG_MIRROR_MASK 0x00000003 95 96 #define VPE_PLANE_ADDR_LO__SHIFT 0 97 #define VPE_PLANE_ADDR_LO_MASK 0xFFFFFF00 98 99 #define VPE_PLANE_CFG_PITCH__SHIFT 0 100 #define VPE_PLANE_CFG_PITCH_MASK 0x00003FFF 101 102 #define VPE_PLANE_CFG_VIEWPORT_Y__SHIFT 16 103 #define VPE_PLANE_CFG_VIEWPORT_Y_MASK 0x3FFF0000 104 #define VPE_PLANE_CFG_VIEWPORT_X__SHIFT 0 105 #define VPE_PLANE_CFG_VIEWPORT_X_MASK 0x00003FFF 106 107 #define VPE_PLANE_CFG_VIEWPORT_HEIGHT__SHIFT 16 108 #define VPE_PLANE_CFG_VIEWPORT_HEIGHT_MASK 0x1FFF0000 109 #define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE__SHIFT 13 110 #define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE_MASK 0x0000E000 111 #define VPE_PLANE_CFG_VIEWPORT_WIDTH__SHIFT 0 112 #define VPE_PLANE_CFG_VIEWPORT_WIDTH_MASK 0x00001FFF 113 114 #define VPE_PLANE_ADDR__SHIFT 32 115 #define VPE_PLANE_HIGH_ADDR_MASK 0xFFFFFFFF00000000 116 117 #define VPE_PLANE_LOW_ADDR_MASK 0x00000000FFFFFFFF 118 #define VPE_PLANE_REUSE_TMZ_MASK 0x0000000000000003 119 120 enum VPE_PLANE_CFG_ELEMENT_SIZE { 121 VPE_PLANE_CFG_ELEMENT_SIZE_8BPE = 0, 122 VPE_PLANE_CFG_ELEMENT_SIZE_16BPE = 1, 123 VPE_PLANE_CFG_ELEMENT_SIZE_32BPE = 2, 124 VPE_PLANE_CFG_ELEMENT_SIZE_64BPE = 3 125 }; 126 127 #define VPE_PLANE_CFG_CMD_HEADER(subop, nps0, npd0, nps1, npd1) \ 128 (VPE_CMD_HEADER(VPE_CMD_OPCODE_PLANE_CFG, subop) | \ 129 (((nps0) << VPE_PLANE_CFG_NPS0__SHIFT) & VPE_PLANE_CFG_NPS0_MASK) | \ 130 (((npd0) << VPE_PLANE_CFG_NPD0__SHIFT) & VPE_PLANE_CFG_NPD0_MASK) | \ 131 (((nps1) << VPE_PLANE_CFG_NPS1__SHIFT) & VPE_PLANE_CFG_NPS1_MASK) | \ 132 (((npd0) << VPE_PLANE_CFG_NPD1__SHIFT) & VPE_PLANE_CFG_NPD1_MASK)) 133 134 135 #ifdef __cplusplus 136 } 137 #endif 138