1 /* 2 * Copyright (c) 2017 Joan Lledó 3 * Copyright (c) 2009, 2012 Samuel Thibault 4 * Heavily inspired from the freebsd, netbsd, and openbsd backends 5 * (C) Copyright Eric Anholt 2006 6 * (C) Copyright IBM Corporation 2006 7 * Copyright (c) 2008 Juan Romero Pardines 8 * Copyright (c) 2008 Mark Kettenis 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 /* Macros and declarations used by both x86 and Hurd modules. */ 24 25 #ifndef X86_PCI_H 26 #define X86_PCI_H 27 28 #include "pciaccess.h" 29 #include "pciaccess_private.h" 30 31 #define PCI_VENDOR(reg) ((reg) & 0xFFFF) 32 #define PCI_VENDOR_INVALID 0xFFFF 33 34 #define PCI_VENDOR_ID 0x00 35 #define PCI_SUB_VENDOR_ID 0x2c 36 #define PCI_VENDOR_ID_COMPAQ 0x0e11 37 #define PCI_VENDOR_ID_INTEL 0x8086 38 39 #define PCI_DEVICE(reg) (((reg) >> 16) & 0xFFFF) 40 #define PCI_DEVICE_INVALID 0xFFFF 41 42 #define PCI_CLASS 0x08 43 #define PCI_CLASS_DEVICE 0x0a 44 #define PCI_CLASS_DISPLAY_VGA 0x0300 45 #define PCI_CLASS_BRIDGE_HOST 0x0600 46 47 #define PCIC_DISPLAY 0x03 48 #define PCIS_DISPLAY_VGA 0x00 49 50 #define PCI_HDRTYPE 0x0E 51 #define PCI_HDRTYPE_DEVICE 0x00 52 #define PCI_HDRTYPE_BRIDGE 0x01 53 #define PCI_HDRTYPE_CARDBUS 0x02 54 #define PCI_IRQ 0x3C 55 56 #define PCI_BAR_ADDR_0 0x10 57 #define PCI_XROMBAR_ADDR_00 0x30 58 #define PCI_XROMBAR_ADDR_01 0x38 59 60 #define PCI_COMMAND 0x04 61 #define PCI_SECONDARY_BUS 0x19 62 63 int x86_enable_io(void); 64 int x86_disable_io(void); 65 void pci_system_x86_destroy(void); 66 struct pci_io_handle *pci_device_x86_open_legacy_io(struct pci_io_handle *ret, 67 struct pci_device *dev, pciaddr_t base, pciaddr_t size); 68 void pci_device_x86_close_io(struct pci_device *dev, 69 struct pci_io_handle *handle); 70 uint32_t pci_device_x86_read32(struct pci_io_handle *handle, uint32_t reg); 71 uint16_t pci_device_x86_read16(struct pci_io_handle *handle, uint32_t reg); 72 uint8_t pci_device_x86_read8(struct pci_io_handle *handle, uint32_t reg); 73 void pci_device_x86_write32(struct pci_io_handle *handle, uint32_t reg, 74 uint32_t data); 75 void pci_device_x86_write16(struct pci_io_handle *handle, uint32_t reg, 76 uint16_t data); 77 void pci_device_x86_write8(struct pci_io_handle *handle, uint32_t reg, 78 uint8_t data); 79 int pci_system_x86_map_dev_mem(void **dest, size_t mem_offset, size_t mem_size, 80 int write); 81 82 #endif /* X86_PCI_H */ 83