1 /* 2 * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DDRPHY_PHYINIT_CSR_ALL_DEFINES_H 8 #define DDRPHY_PHYINIT_CSR_ALL_DEFINES_H 9 10 /* ANIBx register offsets */ 11 #define CSR_MTESTMUXSEL_ADDR 0x1AU 12 #define CSR_AFORCEDRVCONT_ADDR 0x27U 13 #define CSR_AFORCETRICONT_ADDR 0x28U 14 #define CSR_ATXIMPEDANCE_ADDR 0x43U 15 #define CSR_ATESTPRBSERR_ADDR 0x53U 16 #define CSR_ATXSLEWRATE_ADDR 0x55U 17 #define CSR_ATESTPRBSERRCNT_ADDR 0x56U 18 #define CSR_ATXDLY_ADDR 0x80U 19 20 /* DBYTEx register offsets */ 21 #define CSR_DBYTEMISCMODE_ADDR 0x0U 22 #define CSR_TSMBYTE0_ADDR 0x1U 23 #define CSR_TRAININGPARAM_ADDR 0x2U 24 #define CSR_USEDQSENREPLICA_ADDR 0x3U 25 #define CSR_RXTRAINPATTERNENABLE_ADDR 0x10U 26 #define CSR_TSMBYTE1_ADDR 0x11U 27 #define CSR_TSMBYTE2_ADDR 0x12U 28 #define CSR_TSMBYTE3_ADDR 0x13U 29 #define CSR_TSMBYTE4_ADDR 0x14U 30 #define CSR_TESTMODECONFIG_ADDR 0x17U 31 #define CSR_TSMBYTE5_ADDR 0x18U 32 /* MTESTMUXSEL already defined in ANIBx section */ 33 #define CSR_DTSMTRAINMODECTRL_ADDR 0x1FU 34 #define CSR_DFIMRL_ADDR 0x20U 35 #define CSR_ASYNCDBYTEMODE_ADDR 0x24U 36 #define CSR_ASYNCDBYTETXEN_ADDR 0x26U 37 #define CSR_ASYNCDBYTETXDATA_ADDR 0x28U 38 #define CSR_ASYNCDBYTERXDATA_ADDR 0x2AU 39 #define CSR_VREFDAC1_ADDR 0x30U 40 #define CSR_TRAININGCNTR_ADDR 0x32U 41 #define CSR_VREFDAC0_ADDR 0x40U 42 #define CSR_TXIMPEDANCECTRL0_ADDR 0x41U 43 #define CSR_DQDQSRCVCNTRL_ADDR 0x43U 44 #define CSR_TXEQUALIZATIONMODE_ADDR 0x48U 45 #define CSR_TXIMPEDANCECTRL1_ADDR 0x49U 46 #define CSR_DQDQSRCVCNTRL1_ADDR 0x4AU 47 #define CSR_TXIMPEDANCECTRL2_ADDR 0x4BU 48 #define CSR_DQDQSRCVCNTRL2_ADDR 0x4CU 49 #define CSR_TXODTDRVSTREN_ADDR 0x4DU 50 #define CSR_RXFIFOCHECKSTATUS_ADDR 0x56U 51 #define CSR_RXFIFOCHECKERRVALUES_ADDR 0x57U 52 #define CSR_RXFIFOINFO_ADDR 0x58U 53 #define CSR_RXFIFOVISIBILITY_ADDR 0x59U 54 #define CSR_RXFIFOCONTENTSDQ3210_ADDR 0x5AU 55 #define CSR_RXFIFOCONTENTSDQ7654_ADDR 0x5BU 56 #define CSR_RXFIFOCONTENTSDBI_ADDR 0x5CU 57 #define CSR_TXSLEWRATE_ADDR 0x5FU 58 #define CSR_TRAININGINCDECDTSMEN_ADDR 0x62U 59 #define CSR_RXPBDLYTG0_ADDR 0x68U 60 #define CSR_RXPBDLYTG1_ADDR 0x69U 61 #define CSR_RXPBDLYTG2_ADDR 0x6AU 62 #define CSR_RXPBDLYTG3_ADDR 0x6BU 63 #define CSR_RXENDLYTG0_ADDR 0x80U 64 #define CSR_RXENDLYTG1_ADDR 0x81U 65 #define CSR_RXENDLYTG2_ADDR 0x82U 66 #define CSR_RXENDLYTG3_ADDR 0x83U 67 #define CSR_RXCLKDLYTG0_ADDR 0x8CU 68 #define CSR_RXCLKDLYTG1_ADDR 0x8DU 69 #define CSR_RXCLKDLYTG2_ADDR 0x8EU 70 #define CSR_RXCLKDLYTG3_ADDR 0x8FU 71 #define CSR_RXCLKCDLYTG0_ADDR 0x90U 72 #define CSR_RXCLKCDLYTG1_ADDR 0x91U 73 #define CSR_RXCLKCDLYTG2_ADDR 0x92U 74 #define CSR_RXCLKCDLYTG3_ADDR 0x93U 75 #define CSR_DQ0LNSEL_ADDR 0xA0U 76 #define CSR_DQ1LNSEL_ADDR 0xA1U 77 #define CSR_DQ2LNSEL_ADDR 0xA2U 78 #define CSR_DQ3LNSEL_ADDR 0xA3U 79 #define CSR_DQ4LNSEL_ADDR 0xA4U 80 #define CSR_DQ5LNSEL_ADDR 0xA5U 81 #define CSR_DQ6LNSEL_ADDR 0xA6U 82 #define CSR_DQ7LNSEL_ADDR 0xA7U 83 #define CSR_PPTCTLSTATIC_ADDR 0xAAU 84 #define CSR_PPTCTLDYN_ADDR 0xABU 85 #define CSR_PPTINFO_ADDR 0xACU 86 #define CSR_PPTRXENEVNT_ADDR 0xADU 87 #define CSR_PPTDQSCNTINVTRNTG0_ADDR 0xAEU 88 #define CSR_PPTDQSCNTINVTRNTG1_ADDR 0xAFU 89 #define CSR_DTSMBLANKINGCTRL_ADDR 0xB1U 90 #define CSR_TSM0_ADDR 0xB2U 91 #define CSR_TSM1_ADDR 0xB3U 92 #define CSR_TSM2_ADDR 0xB4U 93 #define CSR_TSM3_ADDR 0xB5U 94 #define CSR_TXCHKDATASELECTS_ADDR 0xB6U 95 #define CSR_DTSMUPTHLDXINGIND_ADDR 0xB7U 96 #define CSR_DTSMLOTHLDXINGIND_ADDR 0xB8U 97 #define CSR_DBYTEALLDTSMCTRL0_ADDR 0xB9U 98 #define CSR_DBYTEALLDTSMCTRL1_ADDR 0xBAU 99 #define CSR_DBYTEALLDTSMCTRL2_ADDR 0xBBU 100 #define CSR_TXDQDLYTG0_ADDR 0xC0U 101 #define CSR_TXDQDLYTG1_ADDR 0xC1U 102 #define CSR_TXDQDLYTG2_ADDR 0xC2U 103 #define CSR_TXDQDLYTG3_ADDR 0xC3U 104 #define CSR_TXDQSDLYTG0_ADDR 0xD0U 105 #define CSR_TXDQSDLYTG1_ADDR 0xD1U 106 #define CSR_TXDQSDLYTG2_ADDR 0xD2U 107 #define CSR_TXDQSDLYTG3_ADDR 0xD3U 108 #define CSR_DXLCDLSTATUS_ADDR 0xE4U 109 110 /* MASTER0 register offsets */ 111 #define CSR_RXFIFOINIT_ADDR 0x0U 112 #define CSR_FORCECLKDISABLE_ADDR 0x1U 113 #define CSR_CLOCKINGCTRL_ADDR 0x2U 114 #define CSR_FORCEINTERNALUPDATE_ADDR 0x3U 115 #define CSR_PHYCONFIG_ADDR 0x4U 116 #define CSR_PGCR_ADDR 0x5U 117 #define CSR_TESTBUMPCNTRL1_ADDR 0x7U 118 #define CSR_CALUCLKINFO_ADDR 0x8U 119 #define CSR_TESTBUMPCNTRL_ADDR 0xAU 120 #define CSR_SEQ0BDLY0_ADDR 0xBU 121 #define CSR_SEQ0BDLY1_ADDR 0xCU 122 #define CSR_SEQ0BDLY2_ADDR 0xDU 123 #define CSR_SEQ0BDLY3_ADDR 0xEU 124 #define CSR_PHYALERTSTATUS_ADDR 0xFU 125 #define CSR_PPTTRAINSETUP_ADDR 0x10U 126 #define CSR_PPTTRAINSETUP2_ADDR 0x11U 127 #define CSR_ATESTMODE_ADDR 0x12U 128 #define CSR_TXCALBINP_ADDR 0x14U 129 #define CSR_TXCALBINN_ADDR 0x15U 130 #define CSR_TXCALPOVR_ADDR 0x16U 131 #define CSR_TXCALNOVR_ADDR 0x17U 132 #define CSR_DFIMODE_ADDR 0x18U 133 #define CSR_TRISTATEMODECA_ADDR 0x19U 134 /* MTESTMUXSEL already defined in ANIBx section */ 135 #define CSR_MTESTPGMINFO_ADDR 0x1BU 136 #define CSR_DYNPWRDNUP_ADDR 0x1CU 137 #define CSR_PMIENABLE_ADDR 0x1DU 138 #define CSR_PHYTID_ADDR 0x1EU 139 #define CSR_HWTMRL_ADDR 0x20U 140 #define CSR_DFIPHYUPD_ADDR 0x21U 141 #define CSR_PDAMRSWRITEMODE_ADDR 0x22U 142 #define CSR_DFIGEARDOWNCTL_ADDR 0x23U 143 #define CSR_DQSPREAMBLECONTROL_ADDR 0x24U 144 #define CSR_MASTERX4CONFIG_ADDR 0x25U 145 #define CSR_WRLEVBITS_ADDR 0x26U 146 #define CSR_ENABLECSMULTICAST_ADDR 0x27U 147 #define CSR_HWTLPCSMULTICAST_ADDR 0x28U 148 #define CSR_ACX4ANIBDIS_ADDR 0x2CU 149 #define CSR_DMIPINPRESENT_ADDR 0x2DU 150 #define CSR_ARDPTRINITVAL_ADDR 0x2EU 151 #define CSR_DB0LCDLCALPHDETOUT_ADDR 0x30U 152 #define CSR_DB1LCDLCALPHDETOUT_ADDR 0x31U 153 #define CSR_DB2LCDLCALPHDETOUT_ADDR 0x32U 154 #define CSR_DB3LCDLCALPHDETOUT_ADDR 0x33U 155 #define CSR_DB4LCDLCALPHDETOUT_ADDR 0x34U 156 #define CSR_DB5LCDLCALPHDETOUT_ADDR 0x35U 157 #define CSR_DB6LCDLCALPHDETOUT_ADDR 0x36U 158 #define CSR_DB7LCDLCALPHDETOUT_ADDR 0x37U 159 #define CSR_DB8LCDLCALPHDETOUT_ADDR 0x38U 160 #define CSR_DB9LCDLCALPHDETOUT_ADDR 0x39U 161 #define CSR_DBYTEDLLMODECNTRL_ADDR 0x3AU 162 #define CSR_DBYTERXENTRAIN_ADDR 0x3BU 163 #define CSR_ANLCDLCALPHDETOUT_ADDR 0x3FU 164 #define CSR_CALOFFSETS_ADDR 0x45U 165 #define CSR_SARINITVALS_ADDR 0x47U 166 #define CSR_CALPEXTOVR_ADDR 0x49U 167 #define CSR_CALCMPR5OVR_ADDR 0x4AU 168 #define CSR_CALNINTOVR_ADDR 0x4BU 169 #define CSR_CALDRVSTR0_ADDR 0x50U 170 #define CSR_PROCODTCTL_ADDR 0x55U 171 #define CSR_PROCODTTIMECTL_ADDR 0x56U 172 #define CSR_MEMALERTCONTROL_ADDR 0x5BU 173 #define CSR_MEMALERTCONTROL2_ADDR 0x5CU 174 #define CSR_MEMRESETL_ADDR 0x60U 175 #define CSR_PUBMODE_ADDR 0x6EU 176 #define CSR_MISCPHYSTATUS_ADDR 0x6FU 177 #define CSR_CORELOOPBACKSEL_ADDR 0x70U 178 #define CSR_DLLTRAINPARAM_ADDR 0x71U 179 #define CSR_HWTLPCSENA_ADDR 0x72U 180 #define CSR_HWTLPCSENB_ADDR 0x73U 181 #define CSR_HWTLPCSENBYPASS_ADDR 0x74U 182 #define CSR_DFICAMODE_ADDR 0x75U 183 #define CSR_HWTCACTL_ADDR 0x76U 184 #define CSR_HWTCAMODE_ADDR 0x77U 185 #define CSR_DLLCONTROL_ADDR 0x78U 186 #define CSR_PULSEDLLUPDATEPHASE_ADDR 0x79U 187 #define CSR_HWTCONTROLOVR0_ADDR 0x7AU 188 #define CSR_HWTCONTROLOVR1_ADDR 0x7BU 189 #define CSR_DLLGAINCTL_ADDR 0x7CU 190 #define CSR_DLLLOCKPARAM_ADDR 0x7DU 191 #define CSR_HWTCONTROLVAL0_ADDR 0x7EU 192 #define CSR_HWTCONTROLVAL1_ADDR 0x7FU 193 #define CSR_ACSMGLBLSTART_ADDR 0x81U 194 #define CSR_ACSMGLBLSGLSTPCTRL_ADDR 0x82U 195 #define CSR_LCDLCALPHASE_ADDR 0x84U 196 #define CSR_LCDLCALCTRL_ADDR 0x85U 197 #define CSR_CALRATE_ADDR 0x88U 198 #define CSR_CALZAP_ADDR 0x89U 199 #define CSR_PSTATE_ADDR 0x8BU 200 #define CSR_CALPREDRIVEROVERRIDE_ADDR 0x8CU 201 #define CSR_PLLOUTGATECONTROL_ADDR 0x8DU 202 #define CSR_UCMEMRESETCONTROL_ADDR 0x8FU 203 #define CSR_PORCONTROL_ADDR 0x90U 204 #define CSR_CALBUSY_ADDR 0x97U 205 #define CSR_CALMISC2_ADDR 0x98U 206 #define CSR_CALMISC_ADDR 0x9AU 207 #define CSR_CALVREFS_ADDR 0x9BU 208 #define CSR_CALCMPR5_ADDR 0x9CU 209 #define CSR_CALNINT_ADDR 0x9DU 210 #define CSR_CALPEXT_ADDR 0x9EU 211 #define CSR_CALCMPINVERT_ADDR 0xA8U 212 #define CSR_CALCMPANACNTRL_ADDR 0xAEU 213 #define CSR_DFIRDDATACSDESTMAP_ADDR 0xB0U 214 #define CSR_VREFINGLOBAL_ADDR 0xB2U 215 #define CSR_DFIWRDATACSDESTMAP_ADDR 0xB4U 216 #define CSR_MASUPDGOODCTR_ADDR 0xB5U 217 #define CSR_PHYUPD0GOODCTR_ADDR 0xB6U 218 #define CSR_PHYUPD1GOODCTR_ADDR 0xB7U 219 #define CSR_CTLUPD0GOODCTR_ADDR 0xB8U 220 #define CSR_CTLUPD1GOODCTR_ADDR 0xB9U 221 #define CSR_MASUPDFAILCTR_ADDR 0xBAU 222 #define CSR_PHYUPD0FAILCTR_ADDR 0xBBU 223 #define CSR_PHYUPD1FAILCTR_ADDR 0xBCU 224 #define CSR_PHYPERFCTRENABLE_ADDR 0xBDU 225 #define CSR_DFIWRRDDATACSCONFIG_ADDR 0xBEU 226 #define CSR_PLLPWRDN_ADDR 0xC3U 227 #define CSR_PLLRESET_ADDR 0xC4U 228 #define CSR_PLLCTRL2_ADDR 0xC5U 229 #define CSR_PLLCTRL0_ADDR 0xC6U 230 #define CSR_PLLCTRL1_ADDR 0xC7U 231 #define CSR_PLLTST_ADDR 0xC8U 232 #define CSR_PLLLOCKSTATUS_ADDR 0xC9U 233 #define CSR_PLLTESTMODE_ADDR 0xCAU 234 #define CSR_PLLCTRL3_ADDR 0xCBU 235 #define CSR_PLLCTRL4_ADDR 0xCCU 236 #define CSR_PLLENDOFCAL_ADDR 0xCDU 237 #define CSR_PLLSTANDBYEFF_ADDR 0xCEU 238 #define CSR_PLLDACVALOUT_ADDR 0xCFU 239 #define CSR_DLYTESTSEQ_ADDR 0xD0U 240 #define CSR_DLYTESTRINGSELDB_ADDR 0xD1U 241 #define CSR_DLYTESTRINGSELAC_ADDR 0xD2U 242 #define CSR_DLYTESTCNTDFICLKIV_ADDR 0xD3U 243 #define CSR_DLYTESTCNTDFICLK_ADDR 0xD4U 244 #define CSR_DLYTESTCNTRINGOSCDB0_ADDR 0xD5U 245 #define CSR_DLYTESTCNTRINGOSCDB1_ADDR 0xD6U 246 #define CSR_DLYTESTCNTRINGOSCDB2_ADDR 0xD7U 247 #define CSR_DLYTESTCNTRINGOSCDB3_ADDR 0xD8U 248 #define CSR_DLYTESTCNTRINGOSCDB4_ADDR 0xD9U 249 #define CSR_DLYTESTCNTRINGOSCDB5_ADDR 0xDAU 250 #define CSR_DLYTESTCNTRINGOSCDB6_ADDR 0xDBU 251 #define CSR_DLYTESTCNTRINGOSCDB7_ADDR 0xDCU 252 #define CSR_DLYTESTCNTRINGOSCDB8_ADDR 0xDDU 253 #define CSR_DLYTESTCNTRINGOSCDB9_ADDR 0xDEU 254 #define CSR_DLYTESTCNTRINGOSCAC_ADDR 0xDFU 255 #define CSR_MSTLCDLDBGCNTL_ADDR 0xE0U 256 #define CSR_MSTLCDL0DBGRES_ADDR 0xE1U 257 #define CSR_MSTLCDL1DBGRES_ADDR 0xE2U 258 #define CSR_LCDLDBGCNTL_ADDR 0xE3U 259 #define CSR_ACLCDLSTATUS_ADDR 0xE4U 260 #define CSR_CUSTPHYREV_ADDR 0xEDU 261 #define CSR_PHYREV_ADDR 0xEEU 262 #define CSR_LP3EXITSEQ0BSTARTVECTOR_ADDR 0xEFU 263 #define CSR_DFIFREQXLAT0_ADDR 0xF0U 264 #define CSR_DFIFREQXLAT1_ADDR 0xF1U 265 #define CSR_DFIFREQXLAT2_ADDR 0xF2U 266 #define CSR_DFIFREQXLAT3_ADDR 0xF3U 267 #define CSR_DFIFREQXLAT4_ADDR 0xF4U 268 #define CSR_DFIFREQXLAT5_ADDR 0xF5U 269 #define CSR_DFIFREQXLAT6_ADDR 0xF6U 270 #define CSR_DFIFREQXLAT7_ADDR 0xF7U 271 #define CSR_TXRDPTRINIT_ADDR 0xF8U 272 #define CSR_DFIINITCOMPLETE_ADDR 0xF9U 273 #define CSR_DFIFREQRATIO_ADDR 0xFAU 274 #define CSR_RXFIFOCHECKS_ADDR 0xFBU 275 #define CSR_MTESTDTOCTRL_ADDR 0xFFU 276 #define CSR_MAPCAA0TODFI_ADDR 0x100U 277 #define CSR_MAPCAA1TODFI_ADDR 0x101U 278 #define CSR_MAPCAA2TODFI_ADDR 0x102U 279 #define CSR_MAPCAA3TODFI_ADDR 0x103U 280 #define CSR_MAPCAA4TODFI_ADDR 0x104U 281 #define CSR_MAPCAA5TODFI_ADDR 0x105U 282 #define CSR_MAPCAA6TODFI_ADDR 0x106U 283 #define CSR_MAPCAA7TODFI_ADDR 0x107U 284 #define CSR_MAPCAA8TODFI_ADDR 0x108U 285 #define CSR_MAPCAA9TODFI_ADDR 0x109U 286 #define CSR_MAPCAB0TODFI_ADDR 0x110U 287 #define CSR_MAPCAB1TODFI_ADDR 0x111U 288 #define CSR_MAPCAB2TODFI_ADDR 0x112U 289 #define CSR_MAPCAB3TODFI_ADDR 0x113U 290 #define CSR_MAPCAB4TODFI_ADDR 0x114U 291 #define CSR_MAPCAB5TODFI_ADDR 0x115U 292 #define CSR_MAPCAB6TODFI_ADDR 0x116U 293 #define CSR_MAPCAB7TODFI_ADDR 0x117U 294 #define CSR_MAPCAB8TODFI_ADDR 0x118U 295 #define CSR_MAPCAB9TODFI_ADDR 0x119U 296 #define CSR_PHYINTERRUPTENABLE_ADDR 0x11BU 297 #define CSR_PHYINTERRUPTFWCONTROL_ADDR 0x11CU 298 #define CSR_PHYINTERRUPTMASK_ADDR 0x11DU 299 #define CSR_PHYINTERRUPTCLEAR_ADDR 0x11EU 300 #define CSR_PHYINTERRUPTSTATUS_ADDR 0x11FU 301 #define CSR_HWTSWIZZLEHWTADDRESS0_ADDR 0x120U 302 #define CSR_HWTSWIZZLEHWTADDRESS1_ADDR 0x121U 303 #define CSR_HWTSWIZZLEHWTADDRESS2_ADDR 0x122U 304 #define CSR_HWTSWIZZLEHWTADDRESS3_ADDR 0x123U 305 #define CSR_HWTSWIZZLEHWTADDRESS4_ADDR 0x124U 306 #define CSR_HWTSWIZZLEHWTADDRESS5_ADDR 0x125U 307 #define CSR_HWTSWIZZLEHWTADDRESS6_ADDR 0x126U 308 #define CSR_HWTSWIZZLEHWTADDRESS7_ADDR 0x127U 309 #define CSR_HWTSWIZZLEHWTADDRESS8_ADDR 0x128U 310 #define CSR_HWTSWIZZLEHWTADDRESS9_ADDR 0x129U 311 #define CSR_HWTSWIZZLEHWTADDRESS10_ADDR 0x12AU 312 #define CSR_HWTSWIZZLEHWTADDRESS11_ADDR 0x12BU 313 #define CSR_HWTSWIZZLEHWTADDRESS12_ADDR 0x12CU 314 #define CSR_HWTSWIZZLEHWTADDRESS13_ADDR 0x12DU 315 #define CSR_HWTSWIZZLEHWTADDRESS14_ADDR 0x12EU 316 #define CSR_HWTSWIZZLEHWTADDRESS15_ADDR 0x12FU 317 #define CSR_HWTSWIZZLEHWTADDRESS17_ADDR 0x130U 318 #define CSR_HWTSWIZZLEHWTACTN_ADDR 0x131U 319 #define CSR_HWTSWIZZLEHWTBANK0_ADDR 0x132U 320 #define CSR_HWTSWIZZLEHWTBANK1_ADDR 0x133U 321 #define CSR_HWTSWIZZLEHWTBANK2_ADDR 0x134U 322 #define CSR_HWTSWIZZLEHWTBG0_ADDR 0x135U 323 #define CSR_HWTSWIZZLEHWTBG1_ADDR 0x136U 324 #define CSR_HWTSWIZZLEHWTCASN_ADDR 0x137U 325 #define CSR_HWTSWIZZLEHWTRASN_ADDR 0x138U 326 #define CSR_HWTSWIZZLEHWTWEN_ADDR 0x139U 327 #define CSR_HWTSWIZZLEHWTPARITYIN_ADDR 0x13AU 328 #define CSR_DFIHANDSHAKEDELAYS0_ADDR 0x13CU 329 #define CSR_DFIHANDSHAKEDELAYS1_ADDR 0x13DU 330 #define CSR_REMOTEIMPCAL_ADDR 0x13EU 331 #define CSR_ACLOOPBACKCTL_ADDR 0x13FU 332 333 /* ACSM0 register offsets */ 334 #define CSR_ACSMSEQ0X0_ADDR 0x0U 335 #define CSR_ACSMSEQ0X1_ADDR 0x1U 336 #define CSR_ACSMSEQ0X2_ADDR 0x2U 337 #define CSR_ACSMSEQ0X3_ADDR 0x3U 338 #define CSR_ACSMSEQ0X4_ADDR 0x4U 339 #define CSR_ACSMSEQ0X5_ADDR 0x5U 340 #define CSR_ACSMSEQ0X6_ADDR 0x6U 341 #define CSR_ACSMSEQ0X7_ADDR 0x7U 342 #define CSR_ACSMSEQ0X8_ADDR 0x8U 343 #define CSR_ACSMSEQ0X9_ADDR 0x9U 344 #define CSR_ACSMSEQ0X10_ADDR 0xAU 345 #define CSR_ACSMSEQ0X11_ADDR 0xBU 346 #define CSR_ACSMSEQ0X12_ADDR 0xCU 347 #define CSR_ACSMSEQ0X13_ADDR 0xDU 348 #define CSR_ACSMSEQ0X14_ADDR 0xEU 349 #define CSR_ACSMSEQ0X15_ADDR 0xFU 350 #define CSR_ACSMSEQ0X16_ADDR 0x10U 351 #define CSR_ACSMSEQ0X17_ADDR 0x11U 352 #define CSR_ACSMSEQ0X18_ADDR 0x12U 353 #define CSR_ACSMSEQ0X19_ADDR 0x13U 354 #define CSR_ACSMSEQ0X20_ADDR 0x14U 355 #define CSR_ACSMSEQ0X21_ADDR 0x15U 356 #define CSR_ACSMSEQ0X22_ADDR 0x16U 357 #define CSR_ACSMSEQ0X23_ADDR 0x17U 358 #define CSR_ACSMSEQ0X24_ADDR 0x18U 359 #define CSR_ACSMSEQ0X25_ADDR 0x19U 360 #define CSR_ACSMSEQ0X26_ADDR 0x1AU 361 #define CSR_ACSMSEQ0X27_ADDR 0x1BU 362 #define CSR_ACSMSEQ0X28_ADDR 0x1CU 363 #define CSR_ACSMSEQ0X29_ADDR 0x1DU 364 #define CSR_ACSMSEQ0X30_ADDR 0x1EU 365 #define CSR_ACSMSEQ0X31_ADDR 0x1FU 366 #define CSR_ACSMSEQ1X0_ADDR 0x20U 367 #define CSR_ACSMSEQ1X1_ADDR 0x21U 368 #define CSR_ACSMSEQ1X2_ADDR 0x22U 369 #define CSR_ACSMSEQ1X3_ADDR 0x23U 370 #define CSR_ACSMSEQ1X4_ADDR 0x24U 371 #define CSR_ACSMSEQ1X5_ADDR 0x25U 372 #define CSR_ACSMSEQ1X6_ADDR 0x26U 373 #define CSR_ACSMSEQ1X7_ADDR 0x27U 374 #define CSR_ACSMSEQ1X8_ADDR 0x28U 375 #define CSR_ACSMSEQ1X9_ADDR 0x29U 376 #define CSR_ACSMSEQ1X10_ADDR 0x2AU 377 #define CSR_ACSMSEQ1X11_ADDR 0x2BU 378 #define CSR_ACSMSEQ1X12_ADDR 0x2CU 379 #define CSR_ACSMSEQ1X13_ADDR 0x2DU 380 #define CSR_ACSMSEQ1X14_ADDR 0x2EU 381 #define CSR_ACSMSEQ1X15_ADDR 0x2FU 382 #define CSR_ACSMSEQ1X16_ADDR 0x30U 383 #define CSR_ACSMSEQ1X17_ADDR 0x31U 384 #define CSR_ACSMSEQ1X18_ADDR 0x32U 385 #define CSR_ACSMSEQ1X19_ADDR 0x33U 386 #define CSR_ACSMSEQ1X20_ADDR 0x34U 387 #define CSR_ACSMSEQ1X21_ADDR 0x35U 388 #define CSR_ACSMSEQ1X22_ADDR 0x36U 389 #define CSR_ACSMSEQ1X23_ADDR 0x37U 390 #define CSR_ACSMSEQ1X24_ADDR 0x38U 391 #define CSR_ACSMSEQ1X25_ADDR 0x39U 392 #define CSR_ACSMSEQ1X26_ADDR 0x3AU 393 #define CSR_ACSMSEQ1X27_ADDR 0x3BU 394 #define CSR_ACSMSEQ1X28_ADDR 0x3CU 395 #define CSR_ACSMSEQ1X29_ADDR 0x3DU 396 #define CSR_ACSMSEQ1X30_ADDR 0x3EU 397 #define CSR_ACSMSEQ1X31_ADDR 0x3FU 398 #define CSR_ACSMSEQ2X0_ADDR 0x40U 399 #define CSR_ACSMSEQ2X1_ADDR 0x41U 400 #define CSR_ACSMSEQ2X2_ADDR 0x42U 401 #define CSR_ACSMSEQ2X3_ADDR 0x43U 402 #define CSR_ACSMSEQ2X4_ADDR 0x44U 403 #define CSR_ACSMSEQ2X5_ADDR 0x45U 404 #define CSR_ACSMSEQ2X6_ADDR 0x46U 405 #define CSR_ACSMSEQ2X7_ADDR 0x47U 406 #define CSR_ACSMSEQ2X8_ADDR 0x48U 407 #define CSR_ACSMSEQ2X9_ADDR 0x49U 408 #define CSR_ACSMSEQ2X10_ADDR 0x4AU 409 #define CSR_ACSMSEQ2X11_ADDR 0x4BU 410 #define CSR_ACSMSEQ2X12_ADDR 0x4CU 411 #define CSR_ACSMSEQ2X13_ADDR 0x4DU 412 #define CSR_ACSMSEQ2X14_ADDR 0x4EU 413 #define CSR_ACSMSEQ2X15_ADDR 0x4FU 414 #define CSR_ACSMSEQ2X16_ADDR 0x50U 415 #define CSR_ACSMSEQ2X17_ADDR 0x51U 416 #define CSR_ACSMSEQ2X18_ADDR 0x52U 417 #define CSR_ACSMSEQ2X19_ADDR 0x53U 418 #define CSR_ACSMSEQ2X20_ADDR 0x54U 419 #define CSR_ACSMSEQ2X21_ADDR 0x55U 420 #define CSR_ACSMSEQ2X22_ADDR 0x56U 421 #define CSR_ACSMSEQ2X23_ADDR 0x57U 422 #define CSR_ACSMSEQ2X24_ADDR 0x58U 423 #define CSR_ACSMSEQ2X25_ADDR 0x59U 424 #define CSR_ACSMSEQ2X26_ADDR 0x5AU 425 #define CSR_ACSMSEQ2X27_ADDR 0x5BU 426 #define CSR_ACSMSEQ2X28_ADDR 0x5CU 427 #define CSR_ACSMSEQ2X29_ADDR 0x5DU 428 #define CSR_ACSMSEQ2X30_ADDR 0x5EU 429 #define CSR_ACSMSEQ2X31_ADDR 0x5FU 430 #define CSR_ACSMSEQ3X0_ADDR 0x60U 431 #define CSR_ACSMSEQ3X1_ADDR 0x61U 432 #define CSR_ACSMSEQ3X2_ADDR 0x62U 433 #define CSR_ACSMSEQ3X3_ADDR 0x63U 434 #define CSR_ACSMSEQ3X4_ADDR 0x64U 435 #define CSR_ACSMSEQ3X5_ADDR 0x65U 436 #define CSR_ACSMSEQ3X6_ADDR 0x66U 437 #define CSR_ACSMSEQ3X7_ADDR 0x67U 438 #define CSR_ACSMSEQ3X8_ADDR 0x68U 439 #define CSR_ACSMSEQ3X9_ADDR 0x69U 440 #define CSR_ACSMSEQ3X10_ADDR 0x6AU 441 #define CSR_ACSMSEQ3X11_ADDR 0x6BU 442 #define CSR_ACSMSEQ3X12_ADDR 0x6CU 443 #define CSR_ACSMSEQ3X13_ADDR 0x6DU 444 #define CSR_ACSMSEQ3X14_ADDR 0x6EU 445 #define CSR_ACSMSEQ3X15_ADDR 0x6FU 446 #define CSR_ACSMSEQ3X16_ADDR 0x70U 447 #define CSR_ACSMSEQ3X17_ADDR 0x71U 448 #define CSR_ACSMSEQ3X18_ADDR 0x72U 449 #define CSR_ACSMSEQ3X19_ADDR 0x73U 450 #define CSR_ACSMSEQ3X20_ADDR 0x74U 451 #define CSR_ACSMSEQ3X21_ADDR 0x75U 452 #define CSR_ACSMSEQ3X22_ADDR 0x76U 453 #define CSR_ACSMSEQ3X23_ADDR 0x77U 454 #define CSR_ACSMSEQ3X24_ADDR 0x78U 455 #define CSR_ACSMSEQ3X25_ADDR 0x79U 456 #define CSR_ACSMSEQ3X26_ADDR 0x7AU 457 #define CSR_ACSMSEQ3X27_ADDR 0x7BU 458 #define CSR_ACSMSEQ3X28_ADDR 0x7CU 459 #define CSR_ACSMSEQ3X29_ADDR 0x7DU 460 #define CSR_ACSMSEQ3X30_ADDR 0x7EU 461 #define CSR_ACSMSEQ3X31_ADDR 0x7FU 462 #define CSR_ACSMPLAYBACK0X0_ADDR 0x80U 463 #define CSR_ACSMPLAYBACK1X0_ADDR 0x81U 464 #define CSR_ACSMPLAYBACK0X1_ADDR 0x82U 465 #define CSR_ACSMPLAYBACK1X1_ADDR 0x83U 466 #define CSR_ACSMPLAYBACK0X2_ADDR 0x84U 467 #define CSR_ACSMPLAYBACK1X2_ADDR 0x85U 468 #define CSR_ACSMPLAYBACK0X3_ADDR 0x86U 469 #define CSR_ACSMPLAYBACK1X3_ADDR 0x87U 470 #define CSR_ACSMPLAYBACK0X4_ADDR 0x88U 471 #define CSR_ACSMPLAYBACK1X4_ADDR 0x89U 472 #define CSR_ACSMPLAYBACK0X5_ADDR 0x8AU 473 #define CSR_ACSMPLAYBACK1X5_ADDR 0x8BU 474 #define CSR_ACSMPLAYBACK0X6_ADDR 0x8CU 475 #define CSR_ACSMPLAYBACK1X6_ADDR 0x8DU 476 #define CSR_ACSMPLAYBACK0X7_ADDR 0x8EU 477 #define CSR_ACSMPLAYBACK1X7_ADDR 0x8FU 478 #define CSR_ACSMPSTATEOVREN_ADDR 0x90U 479 #define CSR_ACSMPSTATEOVRVAL_ADDR 0x91U 480 #define CSR_ACSMCTRL23_ADDR 0xC0U 481 #define CSR_ACSMCKEVAL_ADDR 0xC2U 482 #define CSR_LOWSPEEDCLOCKDIVIDER_ADDR 0xC8U 483 #define CSR_ACSMCSMAPCTRL0_ADDR 0xD0U 484 #define CSR_ACSMCSMAPCTRL1_ADDR 0xD1U 485 #define CSR_ACSMCSMAPCTRL2_ADDR 0xD2U 486 #define CSR_ACSMCSMAPCTRL3_ADDR 0xD3U 487 #define CSR_ACSMCSMAPCTRL4_ADDR 0xD4U 488 #define CSR_ACSMCSMAPCTRL5_ADDR 0xD5U 489 #define CSR_ACSMCSMAPCTRL6_ADDR 0xD6U 490 #define CSR_ACSMCSMAPCTRL7_ADDR 0xD7U 491 #define CSR_ACSMCSMAPCTRL8_ADDR 0xD8U 492 #define CSR_ACSMCSMAPCTRL9_ADDR 0xD9U 493 #define CSR_ACSMCSMAPCTRL10_ADDR 0xDAU 494 #define CSR_ACSMCSMAPCTRL11_ADDR 0xDBU 495 #define CSR_ACSMCSMAPCTRL12_ADDR 0xDCU 496 #define CSR_ACSMCSMAPCTRL13_ADDR 0xDDU 497 #define CSR_ACSMCSMAPCTRL14_ADDR 0xDEU 498 #define CSR_ACSMCSMAPCTRL15_ADDR 0xDFU 499 #define CSR_ACSMODTCTRL0_ADDR 0xE0U 500 #define CSR_ACSMODTCTRL1_ADDR 0xE1U 501 #define CSR_ACSMODTCTRL2_ADDR 0xE2U 502 #define CSR_ACSMODTCTRL3_ADDR 0xE3U 503 #define CSR_ACSMODTCTRL4_ADDR 0xE4U 504 #define CSR_ACSMODTCTRL5_ADDR 0xE5U 505 #define CSR_ACSMODTCTRL6_ADDR 0xE6U 506 #define CSR_ACSMODTCTRL7_ADDR 0xE7U 507 #define CSR_ACSMODTCTRL8_ADDR 0xE8U 508 #define CSR_ACSMCTRL16_ADDR 0xE9U 509 #define CSR_LOWSPEEDCLOCKSTOPVAL_ADDR 0xEAU 510 #define CSR_ACSMCTRL18_ADDR 0xEBU 511 #define CSR_ACSMCTRL19_ADDR 0xECU 512 #define CSR_ACSMCTRL20_ADDR 0xEDU 513 #define CSR_ACSMCTRL21_ADDR 0xEEU 514 #define CSR_ACSMCTRL22_ADDR 0xEFU 515 #define CSR_ACSMCTRL0_ADDR 0xF0U 516 #define CSR_ACSMCTRL1_ADDR 0xF1U 517 #define CSR_ACSMCTRL2_ADDR 0xF2U 518 #define CSR_ACSMCTRL3_ADDR 0xF3U 519 #define CSR_ACSMCTRL4_ADDR 0xF4U 520 #define CSR_ACSMCTRL5_ADDR 0xF5U 521 #define CSR_ACSMCTRL6_ADDR 0xF6U 522 #define CSR_ACSMCTRL7_ADDR 0xF7U 523 #define CSR_ACSMCTRL8_ADDR 0xF8U 524 #define CSR_ACSMCTRL9_ADDR 0xF9U 525 #define CSR_ACSMCTRL10_ADDR 0xFAU 526 #define CSR_ACSMCTRL11_ADDR 0xFBU 527 #define CSR_ACSMCTRL12_ADDR 0xFCU 528 #define CSR_ACSMCTRL13_ADDR 0xFDU 529 #define CSR_ACSMCTRL14_ADDR 0xFEU 530 #define CSR_ACSMCTRL15_ADDR 0xFFU 531 532 /* PPGC0 register offsets */ 533 #define CSR_PPGCCTRL1_ADDR 0x11U 534 #define CSR_PPGCLANE2CRCINMAP0_ADDR 0x15U 535 #define CSR_PPGCLANE2CRCINMAP1_ADDR 0x16U 536 #define CSR_PRBSTAPDLY0_ADDR 0x24U 537 #define CSR_PRBSTAPDLY1_ADDR 0x25U 538 #define CSR_PRBSTAPDLY2_ADDR 0x26U 539 #define CSR_PRBSTAPDLY3_ADDR 0x27U 540 #define CSR_GENPRBSBYTE0_ADDR 0x30U 541 #define CSR_GENPRBSBYTE1_ADDR 0x31U 542 #define CSR_GENPRBSBYTE2_ADDR 0x32U 543 #define CSR_GENPRBSBYTE3_ADDR 0x33U 544 #define CSR_GENPRBSBYTE4_ADDR 0x34U 545 #define CSR_GENPRBSBYTE5_ADDR 0x35U 546 #define CSR_GENPRBSBYTE6_ADDR 0x36U 547 #define CSR_GENPRBSBYTE7_ADDR 0x37U 548 #define CSR_GENPRBSBYTE8_ADDR 0x38U 549 #define CSR_GENPRBSBYTE9_ADDR 0x39U 550 #define CSR_GENPRBSBYTE10_ADDR 0x3AU 551 #define CSR_GENPRBSBYTE11_ADDR 0x3BU 552 #define CSR_GENPRBSBYTE12_ADDR 0x3CU 553 #define CSR_GENPRBSBYTE13_ADDR 0x3DU 554 #define CSR_GENPRBSBYTE14_ADDR 0x3EU 555 #define CSR_GENPRBSBYTE15_ADDR 0x3FU 556 #define CSR_PRBSGENCTL_ADDR 0x60U 557 #define CSR_PRBSGENSTATELO_ADDR 0x61U 558 #define CSR_PRBSGENSTATEHI_ADDR 0x62U 559 #define CSR_PRBSCHKSTATELO_ADDR 0x63U 560 #define CSR_PRBSCHKSTATEHI_ADDR 0x64U 561 #define CSR_PRBSGENCTL1_ADDR 0x65U 562 #define CSR_PRBSGENCTL2_ADDR 0x66U 563 564 /* INITENG0 register offsets */ 565 #define CSR_PRESEQUENCEREG0B0S0_ADDR 0x0U 566 #define CSR_PRESEQUENCEREG0B0S1_ADDR 0x1U 567 #define CSR_PRESEQUENCEREG0B0S2_ADDR 0x2U 568 #define CSR_PRESEQUENCEREG0B1S0_ADDR 0x3U 569 #define CSR_PRESEQUENCEREG0B1S1_ADDR 0x4U 570 #define CSR_PRESEQUENCEREG0B1S2_ADDR 0x5U 571 #define CSR_POSTSEQUENCEREG0B0S0_ADDR 0x6U 572 #define CSR_POSTSEQUENCEREG0B0S1_ADDR 0x7U 573 #define CSR_POSTSEQUENCEREG0B0S2_ADDR 0x8U 574 #define CSR_POSTSEQUENCEREG0B1S0_ADDR 0x9U 575 #define CSR_POSTSEQUENCEREG0B1S1_ADDR 0xAU 576 #define CSR_POSTSEQUENCEREG0B1S2_ADDR 0xBU 577 #define CSR_SEQ0BDISABLEFLAG0_ADDR 0xCU 578 #define CSR_SEQ0BDISABLEFLAG1_ADDR 0xDU 579 #define CSR_SEQ0BDISABLEFLAG2_ADDR 0xEU 580 #define CSR_SEQ0BDISABLEFLAG3_ADDR 0xFU 581 #define CSR_SEQ0BDISABLEFLAG4_ADDR 0x10U 582 #define CSR_SEQ0BDISABLEFLAG5_ADDR 0x11U 583 #define CSR_SEQ0BDISABLEFLAG6_ADDR 0x12U 584 #define CSR_SEQ0BDISABLEFLAG7_ADDR 0x13U 585 #define CSR_STARTVECTOR0B0_ADDR 0x17U 586 #define CSR_STARTVECTOR0B1_ADDR 0x18U 587 #define CSR_STARTVECTOR0B2_ADDR 0x19U 588 #define CSR_STARTVECTOR0B3_ADDR 0x1AU 589 #define CSR_STARTVECTOR0B4_ADDR 0x1BU 590 #define CSR_STARTVECTOR0B5_ADDR 0x1CU 591 #define CSR_STARTVECTOR0B6_ADDR 0x1DU 592 #define CSR_STARTVECTOR0B7_ADDR 0x1EU 593 #define CSR_STARTVECTOR0B8_ADDR 0x1FU 594 #define CSR_STARTVECTOR0B9_ADDR 0x20U 595 #define CSR_STARTVECTOR0B10_ADDR 0x21U 596 #define CSR_STARTVECTOR0B11_ADDR 0x22U 597 #define CSR_STARTVECTOR0B12_ADDR 0x23U 598 #define CSR_STARTVECTOR0B13_ADDR 0x24U 599 #define CSR_STARTVECTOR0B14_ADDR 0x25U 600 #define CSR_STARTVECTOR0B15_ADDR 0x26U 601 #define CSR_SEQ0BWAITCONDSEL_ADDR 0x27U 602 #define CSR_PHYINLP3_ADDR 0x28U 603 #define CSR_SEQUENCEREG0B0S0_ADDR 0x29U 604 #define CSR_SEQUENCEREG0B0S1_ADDR 0x2AU 605 #define CSR_SEQUENCEREG0B0S2_ADDR 0x2BU 606 #define CSR_SEQUENCEREG0B1S0_ADDR 0x2CU 607 #define CSR_SEQUENCEREG0B1S1_ADDR 0x2DU 608 #define CSR_SEQUENCEREG0B1S2_ADDR 0x2EU 609 #define CSR_SEQUENCEREG0B2S0_ADDR 0x2FU 610 #define CSR_SEQUENCEREG0B2S1_ADDR 0x30U 611 #define CSR_SEQUENCEREG0B2S2_ADDR 0x31U 612 #define CSR_SEQUENCEREG0B3S0_ADDR 0x32U 613 #define CSR_SEQUENCEREG0B3S1_ADDR 0x33U 614 #define CSR_SEQUENCEREG0B3S2_ADDR 0x34U 615 #define CSR_SEQUENCEREG0B4S0_ADDR 0x35U 616 #define CSR_SEQUENCEREG0B4S1_ADDR 0x36U 617 #define CSR_SEQUENCEREG0B4S2_ADDR 0x37U 618 #define CSR_SEQUENCEREG0B5S0_ADDR 0x38U 619 #define CSR_SEQUENCEREG0B5S1_ADDR 0x39U 620 #define CSR_SEQUENCEREG0B5S2_ADDR 0x3AU 621 #define CSR_SEQUENCEREG0B6S0_ADDR 0x3BU 622 #define CSR_SEQUENCEREG0B6S1_ADDR 0x3CU 623 #define CSR_SEQUENCEREG0B6S2_ADDR 0x3DU 624 #define CSR_SEQUENCEREG0B7S0_ADDR 0x3EU 625 #define CSR_SEQUENCEREG0B7S1_ADDR 0x3FU 626 #define CSR_SEQUENCEREG0B7S2_ADDR 0x40U 627 #define CSR_SEQUENCEREG0B8S0_ADDR 0x41U 628 #define CSR_SEQUENCEREG0B8S1_ADDR 0x42U 629 #define CSR_SEQUENCEREG0B8S2_ADDR 0x43U 630 #define CSR_SEQUENCEREG0B9S0_ADDR 0x44U 631 #define CSR_SEQUENCEREG0B9S1_ADDR 0x45U 632 #define CSR_SEQUENCEREG0B9S2_ADDR 0x46U 633 #define CSR_SEQUENCEREG0B10S0_ADDR 0x47U 634 #define CSR_SEQUENCEREG0B10S1_ADDR 0x48U 635 #define CSR_SEQUENCEREG0B10S2_ADDR 0x49U 636 #define CSR_SEQUENCEREG0B11S0_ADDR 0x4AU 637 #define CSR_SEQUENCEREG0B11S1_ADDR 0x4BU 638 #define CSR_SEQUENCEREG0B11S2_ADDR 0x4CU 639 #define CSR_SEQUENCEREG0B12S0_ADDR 0x4DU 640 #define CSR_SEQUENCEREG0B12S1_ADDR 0x4EU 641 #define CSR_SEQUENCEREG0B12S2_ADDR 0x4FU 642 #define CSR_SEQUENCEREG0B13S0_ADDR 0x50U 643 #define CSR_SEQUENCEREG0B13S1_ADDR 0x51U 644 #define CSR_SEQUENCEREG0B13S2_ADDR 0x52U 645 #define CSR_SEQUENCEREG0B14S0_ADDR 0x53U 646 #define CSR_SEQUENCEREG0B14S1_ADDR 0x54U 647 #define CSR_SEQUENCEREG0B14S2_ADDR 0x55U 648 #define CSR_SEQUENCEREG0B15S0_ADDR 0x56U 649 #define CSR_SEQUENCEREG0B15S1_ADDR 0x57U 650 #define CSR_SEQUENCEREG0B15S2_ADDR 0x58U 651 #define CSR_SEQUENCEREG0B16S0_ADDR 0x59U 652 #define CSR_SEQUENCEREG0B16S1_ADDR 0x5AU 653 #define CSR_SEQUENCEREG0B16S2_ADDR 0x5BU 654 #define CSR_SEQUENCEREG0B17S0_ADDR 0x5CU 655 #define CSR_SEQUENCEREG0B17S1_ADDR 0x5DU 656 #define CSR_SEQUENCEREG0B17S2_ADDR 0x5EU 657 #define CSR_SEQUENCEREG0B18S0_ADDR 0x5FU 658 #define CSR_SEQUENCEREG0B18S1_ADDR 0x60U 659 #define CSR_SEQUENCEREG0B18S2_ADDR 0x61U 660 #define CSR_SEQUENCEREG0B19S0_ADDR 0x62U 661 #define CSR_SEQUENCEREG0B19S1_ADDR 0x63U 662 #define CSR_SEQUENCEREG0B19S2_ADDR 0x64U 663 #define CSR_SEQUENCEREG0B20S0_ADDR 0x65U 664 #define CSR_SEQUENCEREG0B20S1_ADDR 0x66U 665 #define CSR_SEQUENCEREG0B20S2_ADDR 0x67U 666 #define CSR_SEQUENCEREG0B21S0_ADDR 0x68U 667 #define CSR_SEQUENCEREG0B21S1_ADDR 0x69U 668 #define CSR_SEQUENCEREG0B21S2_ADDR 0x6AU 669 #define CSR_SEQUENCEREG0B22S0_ADDR 0x6BU 670 #define CSR_SEQUENCEREG0B22S1_ADDR 0x6CU 671 #define CSR_SEQUENCEREG0B22S2_ADDR 0x6DU 672 #define CSR_SEQUENCEREG0B23S0_ADDR 0x6EU 673 #define CSR_SEQUENCEREG0B23S1_ADDR 0x6FU 674 #define CSR_SEQUENCEREG0B23S2_ADDR 0x70U 675 #define CSR_SEQUENCEREG0B24S0_ADDR 0x71U 676 #define CSR_SEQUENCEREG0B24S1_ADDR 0x72U 677 #define CSR_SEQUENCEREG0B24S2_ADDR 0x73U 678 #define CSR_SEQUENCEREG0B25S0_ADDR 0x74U 679 #define CSR_SEQUENCEREG0B25S1_ADDR 0x75U 680 #define CSR_SEQUENCEREG0B25S2_ADDR 0x76U 681 #define CSR_SEQUENCEREG0B26S0_ADDR 0x77U 682 #define CSR_SEQUENCEREG0B26S1_ADDR 0x78U 683 #define CSR_SEQUENCEREG0B26S2_ADDR 0x79U 684 #define CSR_SEQUENCEREG0B27S0_ADDR 0x7AU 685 #define CSR_SEQUENCEREG0B27S1_ADDR 0x7BU 686 #define CSR_SEQUENCEREG0B27S2_ADDR 0x7CU 687 #define CSR_SEQUENCEREG0B28S0_ADDR 0x7DU 688 #define CSR_SEQUENCEREG0B28S1_ADDR 0x7EU 689 #define CSR_SEQUENCEREG0B28S2_ADDR 0x7FU 690 #define CSR_SEQUENCEREG0B29S0_ADDR 0x80U 691 #define CSR_SEQUENCEREG0B29S1_ADDR 0x81U 692 #define CSR_SEQUENCEREG0B29S2_ADDR 0x82U 693 #define CSR_SEQUENCEREG0B30S0_ADDR 0x83U 694 #define CSR_SEQUENCEREG0B30S1_ADDR 0x84U 695 #define CSR_SEQUENCEREG0B30S2_ADDR 0x85U 696 #define CSR_SEQUENCEREG0B31S0_ADDR 0x86U 697 #define CSR_SEQUENCEREG0B31S1_ADDR 0x87U 698 #define CSR_SEQUENCEREG0B31S2_ADDR 0x88U 699 #define CSR_SEQUENCEREG0B32S0_ADDR 0x89U 700 #define CSR_SEQUENCEREG0B32S1_ADDR 0x8AU 701 #define CSR_SEQUENCEREG0B32S2_ADDR 0x8BU 702 #define CSR_SEQUENCEREG0B33S0_ADDR 0x8CU 703 #define CSR_SEQUENCEREG0B33S1_ADDR 0x8DU 704 #define CSR_SEQUENCEREG0B33S2_ADDR 0x8EU 705 #define CSR_SEQUENCEREG0B34S0_ADDR 0x8FU 706 #define CSR_SEQUENCEREG0B34S1_ADDR 0x90U 707 #define CSR_SEQUENCEREG0B34S2_ADDR 0x91U 708 #define CSR_SEQUENCEREG0B35S0_ADDR 0x92U 709 #define CSR_SEQUENCEREG0B35S1_ADDR 0x93U 710 #define CSR_SEQUENCEREG0B35S2_ADDR 0x94U 711 #define CSR_SEQUENCEREG0B36S0_ADDR 0x95U 712 #define CSR_SEQUENCEREG0B36S1_ADDR 0x96U 713 #define CSR_SEQUENCEREG0B36S2_ADDR 0x97U 714 #define CSR_SEQUENCEREG0B37S0_ADDR 0x98U 715 #define CSR_SEQUENCEREG0B37S1_ADDR 0x99U 716 #define CSR_SEQUENCEREG0B37S2_ADDR 0x9AU 717 #define CSR_SEQUENCEREG0B38S0_ADDR 0x9BU 718 #define CSR_SEQUENCEREG0B38S1_ADDR 0x9CU 719 #define CSR_SEQUENCEREG0B38S2_ADDR 0x9DU 720 #define CSR_SEQUENCEREG0B39S0_ADDR 0x9EU 721 #define CSR_SEQUENCEREG0B39S1_ADDR 0x9FU 722 #define CSR_SEQUENCEREG0B39S2_ADDR 0xA0U 723 #define CSR_SEQUENCEREG0B40S0_ADDR 0xA1U 724 #define CSR_SEQUENCEREG0B40S1_ADDR 0xA2U 725 #define CSR_SEQUENCEREG0B40S2_ADDR 0xA3U 726 #define CSR_SEQUENCEREG0B41S0_ADDR 0xA4U 727 #define CSR_SEQUENCEREG0B41S1_ADDR 0xA5U 728 #define CSR_SEQUENCEREG0B41S2_ADDR 0xA6U 729 #define CSR_SEQUENCEREG0B42S0_ADDR 0xA7U 730 #define CSR_SEQUENCEREG0B42S1_ADDR 0xA8U 731 #define CSR_SEQUENCEREG0B42S2_ADDR 0xA9U 732 #define CSR_SEQUENCEREG0B43S0_ADDR 0xAAU 733 #define CSR_SEQUENCEREG0B43S1_ADDR 0xABU 734 #define CSR_SEQUENCEREG0B43S2_ADDR 0xACU 735 #define CSR_SEQUENCEREG0B44S0_ADDR 0xADU 736 #define CSR_SEQUENCEREG0B44S1_ADDR 0xAEU 737 #define CSR_SEQUENCEREG0B44S2_ADDR 0xAFU 738 #define CSR_SEQUENCEREG0B45S0_ADDR 0xB0U 739 #define CSR_SEQUENCEREG0B45S1_ADDR 0xB1U 740 #define CSR_SEQUENCEREG0B45S2_ADDR 0xB2U 741 #define CSR_SEQUENCEREG0B46S0_ADDR 0xB3U 742 #define CSR_SEQUENCEREG0B46S1_ADDR 0xB4U 743 #define CSR_SEQUENCEREG0B46S2_ADDR 0xB5U 744 #define CSR_SEQUENCEREG0B47S0_ADDR 0xB6U 745 #define CSR_SEQUENCEREG0B47S1_ADDR 0xB7U 746 #define CSR_SEQUENCEREG0B47S2_ADDR 0xB8U 747 #define CSR_SEQUENCEREG0B48S0_ADDR 0xB9U 748 #define CSR_SEQUENCEREG0B48S1_ADDR 0xBAU 749 #define CSR_SEQUENCEREG0B48S2_ADDR 0xBBU 750 #define CSR_SEQUENCEREG0B49S0_ADDR 0xBCU 751 #define CSR_SEQUENCEREG0B49S1_ADDR 0xBDU 752 #define CSR_SEQUENCEREG0B49S2_ADDR 0xBEU 753 #define CSR_SEQUENCEREG0B50S0_ADDR 0xBFU 754 #define CSR_SEQUENCEREG0B50S1_ADDR 0xC0U 755 #define CSR_SEQUENCEREG0B50S2_ADDR 0xC1U 756 #define CSR_SEQUENCEREG0B51S0_ADDR 0xC2U 757 #define CSR_SEQUENCEREG0B51S1_ADDR 0xC3U 758 #define CSR_SEQUENCEREG0B51S2_ADDR 0xC4U 759 #define CSR_SEQUENCEREG0B52S0_ADDR 0xC5U 760 #define CSR_SEQUENCEREG0B52S1_ADDR 0xC6U 761 #define CSR_SEQUENCEREG0B52S2_ADDR 0xC7U 762 #define CSR_SEQUENCEREG0B53S0_ADDR 0xC8U 763 #define CSR_SEQUENCEREG0B53S1_ADDR 0xC9U 764 #define CSR_SEQUENCEREG0B53S2_ADDR 0xCAU 765 #define CSR_SEQUENCEREG0B54S0_ADDR 0xCBU 766 #define CSR_SEQUENCEREG0B54S1_ADDR 0xCCU 767 #define CSR_SEQUENCEREG0B54S2_ADDR 0xCDU 768 #define CSR_SEQUENCEREG0B55S0_ADDR 0xCEU 769 #define CSR_SEQUENCEREG0B55S1_ADDR 0xCFU 770 #define CSR_SEQUENCEREG0B55S2_ADDR 0xD0U 771 #define CSR_SEQUENCEREG0B56S0_ADDR 0xD1U 772 #define CSR_SEQUENCEREG0B56S1_ADDR 0xD2U 773 #define CSR_SEQUENCEREG0B56S2_ADDR 0xD3U 774 #define CSR_SEQUENCEREG0B57S0_ADDR 0xD4U 775 #define CSR_SEQUENCEREG0B57S1_ADDR 0xD5U 776 #define CSR_SEQUENCEREG0B57S2_ADDR 0xD6U 777 #define CSR_SEQUENCEREG0B58S0_ADDR 0xD7U 778 #define CSR_SEQUENCEREG0B58S1_ADDR 0xD8U 779 #define CSR_SEQUENCEREG0B58S2_ADDR 0xD9U 780 #define CSR_SEQUENCEREG0B59S0_ADDR 0xDAU 781 #define CSR_SEQUENCEREG0B59S1_ADDR 0xDBU 782 #define CSR_SEQUENCEREG0B59S2_ADDR 0xDCU 783 #define CSR_SEQUENCEREG0B60S0_ADDR 0xDDU 784 #define CSR_SEQUENCEREG0B60S1_ADDR 0xDEU 785 #define CSR_SEQUENCEREG0B60S2_ADDR 0xDFU 786 #define CSR_SEQUENCEREG0B61S0_ADDR 0xE0U 787 #define CSR_SEQUENCEREG0B61S1_ADDR 0xE1U 788 #define CSR_SEQUENCEREG0B61S2_ADDR 0xE2U 789 #define CSR_SEQUENCEREG0B62S0_ADDR 0xE3U 790 #define CSR_SEQUENCEREG0B62S1_ADDR 0xE4U 791 #define CSR_SEQUENCEREG0B62S2_ADDR 0xE5U 792 #define CSR_SEQUENCEREG0B63S0_ADDR 0xE6U 793 #define CSR_SEQUENCEREG0B63S1_ADDR 0xE7U 794 #define CSR_SEQUENCEREG0B63S2_ADDR 0xE8U 795 #define CSR_SEQUENCEREG0B64S0_ADDR 0xE9U 796 #define CSR_SEQUENCEREG0B64S1_ADDR 0xEAU 797 #define CSR_SEQUENCEREG0B64S2_ADDR 0xEBU 798 #define CSR_SEQUENCEREG0B65S0_ADDR 0xECU 799 #define CSR_SEQUENCEREG0B65S1_ADDR 0xEDU 800 #define CSR_SEQUENCEREG0B65S2_ADDR 0xEEU 801 #define CSR_SEQUENCEREG0B66S0_ADDR 0xEFU 802 #define CSR_SEQUENCEREG0B66S1_ADDR 0xF0U 803 #define CSR_SEQUENCEREG0B66S2_ADDR 0xF1U 804 #define CSR_SEQUENCEREG0B67S0_ADDR 0xF2U 805 #define CSR_SEQUENCEREG0B67S1_ADDR 0xF3U 806 #define CSR_SEQUENCEREG0B67S2_ADDR 0xF4U 807 #define CSR_SEQUENCEREG0B68S0_ADDR 0xF5U 808 #define CSR_SEQUENCEREG0B68S1_ADDR 0xF6U 809 #define CSR_SEQUENCEREG0B68S2_ADDR 0xF7U 810 #define CSR_SEQUENCEREG0B69S0_ADDR 0xF8U 811 #define CSR_SEQUENCEREG0B69S1_ADDR 0xF9U 812 #define CSR_SEQUENCEREG0B69S2_ADDR 0xFAU 813 #define CSR_SEQUENCEREG0B70S0_ADDR 0xFBU 814 #define CSR_SEQUENCEREG0B70S1_ADDR 0xFCU 815 #define CSR_SEQUENCEREG0B70S2_ADDR 0xFDU 816 #define CSR_SEQUENCEREG0B71S0_ADDR 0xFEU 817 #define CSR_SEQUENCEREG0B71S1_ADDR 0xFFU 818 #define CSR_SEQUENCEREG0B71S2_ADDR 0x100U 819 #define CSR_SEQUENCEREG0B72S0_ADDR 0x101U 820 #define CSR_SEQUENCEREG0B72S1_ADDR 0x102U 821 #define CSR_SEQUENCEREG0B72S2_ADDR 0x103U 822 #define CSR_SEQUENCEREG0B73S0_ADDR 0x104U 823 #define CSR_SEQUENCEREG0B73S1_ADDR 0x105U 824 #define CSR_SEQUENCEREG0B73S2_ADDR 0x106U 825 #define CSR_SEQUENCEREG0B74S0_ADDR 0x107U 826 #define CSR_SEQUENCEREG0B74S1_ADDR 0x108U 827 #define CSR_SEQUENCEREG0B74S2_ADDR 0x109U 828 #define CSR_SEQUENCEREG0B75S0_ADDR 0x10AU 829 #define CSR_SEQUENCEREG0B75S1_ADDR 0x10BU 830 #define CSR_SEQUENCEREG0B75S2_ADDR 0x10CU 831 #define CSR_SEQUENCEREG0B76S0_ADDR 0x10DU 832 #define CSR_SEQUENCEREG0B76S1_ADDR 0x10EU 833 #define CSR_SEQUENCEREG0B76S2_ADDR 0x10FU 834 #define CSR_SEQUENCEREG0B77S0_ADDR 0x110U 835 #define CSR_SEQUENCEREG0B77S1_ADDR 0x111U 836 #define CSR_SEQUENCEREG0B77S2_ADDR 0x112U 837 #define CSR_SEQUENCEREG0B78S0_ADDR 0x113U 838 #define CSR_SEQUENCEREG0B78S1_ADDR 0x114U 839 #define CSR_SEQUENCEREG0B78S2_ADDR 0x115U 840 #define CSR_SEQUENCEREG0B79S0_ADDR 0x116U 841 #define CSR_SEQUENCEREG0B79S1_ADDR 0x117U 842 #define CSR_SEQUENCEREG0B79S2_ADDR 0x118U 843 #define CSR_SEQUENCEREG0B80S0_ADDR 0x119U 844 #define CSR_SEQUENCEREG0B80S1_ADDR 0x11AU 845 #define CSR_SEQUENCEREG0B80S2_ADDR 0x11BU 846 #define CSR_SEQUENCEREG0B81S0_ADDR 0x11CU 847 #define CSR_SEQUENCEREG0B81S1_ADDR 0x11DU 848 #define CSR_SEQUENCEREG0B81S2_ADDR 0x11EU 849 #define CSR_SEQUENCEREG0B82S0_ADDR 0x11FU 850 #define CSR_SEQUENCEREG0B82S1_ADDR 0x120U 851 #define CSR_SEQUENCEREG0B82S2_ADDR 0x121U 852 #define CSR_SEQUENCEREG0B83S0_ADDR 0x122U 853 #define CSR_SEQUENCEREG0B83S1_ADDR 0x123U 854 #define CSR_SEQUENCEREG0B83S2_ADDR 0x124U 855 #define CSR_SEQUENCEREG0B84S0_ADDR 0x125U 856 #define CSR_SEQUENCEREG0B84S1_ADDR 0x126U 857 #define CSR_SEQUENCEREG0B84S2_ADDR 0x127U 858 #define CSR_SEQUENCEREG0B85S0_ADDR 0x128U 859 #define CSR_SEQUENCEREG0B85S1_ADDR 0x129U 860 #define CSR_SEQUENCEREG0B85S2_ADDR 0x12AU 861 #define CSR_SEQUENCEREG0B86S0_ADDR 0x12BU 862 #define CSR_SEQUENCEREG0B86S1_ADDR 0x12CU 863 #define CSR_SEQUENCEREG0B86S2_ADDR 0x12DU 864 #define CSR_SEQUENCEREG0B87S0_ADDR 0x12EU 865 #define CSR_SEQUENCEREG0B87S1_ADDR 0x12FU 866 #define CSR_SEQUENCEREG0B87S2_ADDR 0x130U 867 #define CSR_SEQUENCEREG0B88S0_ADDR 0x131U 868 #define CSR_SEQUENCEREG0B88S1_ADDR 0x132U 869 #define CSR_SEQUENCEREG0B88S2_ADDR 0x133U 870 #define CSR_SEQUENCEREG0B89S0_ADDR 0x134U 871 #define CSR_SEQUENCEREG0B89S1_ADDR 0x135U 872 #define CSR_SEQUENCEREG0B89S2_ADDR 0x136U 873 #define CSR_SEQUENCEREG0B90S0_ADDR 0x137U 874 #define CSR_SEQUENCEREG0B90S1_ADDR 0x138U 875 #define CSR_SEQUENCEREG0B90S2_ADDR 0x139U 876 #define CSR_SEQUENCEREG0B91S0_ADDR 0x13AU 877 #define CSR_SEQUENCEREG0B91S1_ADDR 0x13BU 878 #define CSR_SEQUENCEREG0B91S2_ADDR 0x13CU 879 #define CSR_SEQUENCEREG0B92S0_ADDR 0x13DU 880 #define CSR_SEQUENCEREG0B92S1_ADDR 0x13EU 881 #define CSR_SEQUENCEREG0B92S2_ADDR 0x13FU 882 #define CSR_SEQUENCEREG0B93S0_ADDR 0x140U 883 #define CSR_SEQUENCEREG0B93S1_ADDR 0x141U 884 #define CSR_SEQUENCEREG0B93S2_ADDR 0x142U 885 #define CSR_SEQUENCEREG0B94S0_ADDR 0x143U 886 #define CSR_SEQUENCEREG0B94S1_ADDR 0x144U 887 #define CSR_SEQUENCEREG0B94S2_ADDR 0x145U 888 #define CSR_SEQUENCEREG0B95S0_ADDR 0x146U 889 #define CSR_SEQUENCEREG0B95S1_ADDR 0x147U 890 #define CSR_SEQUENCEREG0B95S2_ADDR 0x148U 891 #define CSR_SEQUENCEREG0B96S0_ADDR 0x149U 892 #define CSR_SEQUENCEREG0B96S1_ADDR 0x14AU 893 #define CSR_SEQUENCEREG0B96S2_ADDR 0x14BU 894 #define CSR_SEQUENCEREG0B97S0_ADDR 0x14CU 895 #define CSR_SEQUENCEREG0B97S1_ADDR 0x14DU 896 #define CSR_SEQUENCEREG0B97S2_ADDR 0x14EU 897 #define CSR_SEQUENCEREG0B98S0_ADDR 0x14FU 898 #define CSR_SEQUENCEREG0B98S1_ADDR 0x150U 899 #define CSR_SEQUENCEREG0B98S2_ADDR 0x151U 900 #define CSR_SEQUENCEREG0B99S0_ADDR 0x152U 901 #define CSR_SEQUENCEREG0B99S1_ADDR 0x153U 902 #define CSR_SEQUENCEREG0B99S2_ADDR 0x154U 903 #define CSR_SEQUENCEREG0B100S0_ADDR 0x155U 904 #define CSR_SEQUENCEREG0B100S1_ADDR 0x156U 905 #define CSR_SEQUENCEREG0B100S2_ADDR 0x157U 906 #define CSR_SEQUENCEREG0B101S0_ADDR 0x158U 907 #define CSR_SEQUENCEREG0B101S1_ADDR 0x159U 908 #define CSR_SEQUENCEREG0B101S2_ADDR 0x15AU 909 #define CSR_SEQUENCEREG0B102S0_ADDR 0x15BU 910 #define CSR_SEQUENCEREG0B102S1_ADDR 0x15CU 911 #define CSR_SEQUENCEREG0B102S2_ADDR 0x15DU 912 #define CSR_SEQUENCEREG0B103S0_ADDR 0x15EU 913 #define CSR_SEQUENCEREG0B103S1_ADDR 0x15FU 914 #define CSR_SEQUENCEREG0B103S2_ADDR 0x160U 915 #define CSR_SEQUENCEREG0B104S0_ADDR 0x161U 916 #define CSR_SEQUENCEREG0B104S1_ADDR 0x162U 917 #define CSR_SEQUENCEREG0B104S2_ADDR 0x163U 918 #define CSR_SEQUENCEREG0B105S0_ADDR 0x164U 919 #define CSR_SEQUENCEREG0B105S1_ADDR 0x165U 920 #define CSR_SEQUENCEREG0B105S2_ADDR 0x166U 921 #define CSR_SEQUENCEREG0B106S0_ADDR 0x167U 922 #define CSR_SEQUENCEREG0B106S1_ADDR 0x168U 923 #define CSR_SEQUENCEREG0B106S2_ADDR 0x169U 924 #define CSR_SEQUENCEREG0B107S0_ADDR 0x16AU 925 #define CSR_SEQUENCEREG0B107S1_ADDR 0x16BU 926 #define CSR_SEQUENCEREG0B107S2_ADDR 0x16CU 927 #define CSR_SEQUENCEREG0B108S0_ADDR 0x16DU 928 #define CSR_SEQUENCEREG0B108S1_ADDR 0x16EU 929 #define CSR_SEQUENCEREG0B108S2_ADDR 0x16FU 930 #define CSR_SEQUENCEREG0B109S0_ADDR 0x170U 931 #define CSR_SEQUENCEREG0B109S1_ADDR 0x171U 932 #define CSR_SEQUENCEREG0B109S2_ADDR 0x172U 933 #define CSR_SEQUENCEREG0B110S0_ADDR 0x173U 934 #define CSR_SEQUENCEREG0B110S1_ADDR 0x174U 935 #define CSR_SEQUENCEREG0B110S2_ADDR 0x175U 936 #define CSR_SEQUENCEREG0B111S0_ADDR 0x176U 937 #define CSR_SEQUENCEREG0B111S1_ADDR 0x177U 938 #define CSR_SEQUENCEREG0B111S2_ADDR 0x178U 939 #define CSR_SEQUENCEREG0B112S0_ADDR 0x179U 940 #define CSR_SEQUENCEREG0B112S1_ADDR 0x17AU 941 #define CSR_SEQUENCEREG0B112S2_ADDR 0x17BU 942 #define CSR_SEQUENCEREG0B113S0_ADDR 0x17CU 943 #define CSR_SEQUENCEREG0B113S1_ADDR 0x17DU 944 #define CSR_SEQUENCEREG0B113S2_ADDR 0x17EU 945 #define CSR_SEQUENCEREG0B114S0_ADDR 0x17FU 946 #define CSR_SEQUENCEREG0B114S1_ADDR 0x180U 947 #define CSR_SEQUENCEREG0B114S2_ADDR 0x181U 948 #define CSR_SEQUENCEREG0B115S0_ADDR 0x182U 949 #define CSR_SEQUENCEREG0B115S1_ADDR 0x183U 950 #define CSR_SEQUENCEREG0B115S2_ADDR 0x184U 951 #define CSR_SEQUENCEREG0B116S0_ADDR 0x185U 952 #define CSR_SEQUENCEREG0B116S1_ADDR 0x186U 953 #define CSR_SEQUENCEREG0B116S2_ADDR 0x187U 954 #define CSR_SEQUENCEREG0B117S0_ADDR 0x188U 955 #define CSR_SEQUENCEREG0B117S1_ADDR 0x189U 956 #define CSR_SEQUENCEREG0B117S2_ADDR 0x18AU 957 #define CSR_SEQUENCEREG0B118S0_ADDR 0x18BU 958 #define CSR_SEQUENCEREG0B118S1_ADDR 0x18CU 959 #define CSR_SEQUENCEREG0B118S2_ADDR 0x18DU 960 #define CSR_SEQUENCEREG0B119S0_ADDR 0x18EU 961 #define CSR_SEQUENCEREG0B119S1_ADDR 0x18FU 962 #define CSR_SEQUENCEREG0B119S2_ADDR 0x190U 963 #define CSR_SEQUENCEREG0B120S0_ADDR 0x191U 964 #define CSR_SEQUENCEREG0B120S1_ADDR 0x192U 965 #define CSR_SEQUENCEREG0B120S2_ADDR 0x193U 966 #define CSR_SEQUENCEREG0B121S0_ADDR 0x194U 967 #define CSR_SEQUENCEREG0B121S1_ADDR 0x195U 968 #define CSR_SEQUENCEREG0B121S2_ADDR 0x196U 969 #define CSR_SEQ0BGPR1_ADDR 0x201U 970 #define CSR_SEQ0BGPR2_ADDR 0x202U 971 #define CSR_SEQ0BGPR3_ADDR 0x203U 972 #define CSR_SEQ0BGPR4_ADDR 0x204U 973 #define CSR_SEQ0BGPR5_ADDR 0x205U 974 #define CSR_SEQ0BGPR6_ADDR 0x206U 975 #define CSR_SEQ0BGPR7_ADDR 0x207U 976 #define CSR_SEQ0BGPR8_ADDR 0x208U 977 #define CSR_SEQ0BFIXEDADDRBITS_ADDR 0x2FFU 978 979 /* DRTUB0 register offsets */ 980 #define CSR_DCTSHADOWREGS_ADDR 0x4U 981 #define CSR_DCTWRITEONLYSHADOW_ADDR 0x30U 982 #define CSR_UCTWRITEONLY_ADDR 0x32U 983 #define CSR_UCTWRITEPROT_ADDR 0x33U 984 #define CSR_UCTDATWRITEONLY_ADDR 0x34U 985 #define CSR_UCTDATWRITEPROT_ADDR 0x35U 986 #define CSR_UCTLERR_ADDR 0x36U 987 #define CSR_UCCLKHCLKENABLES_ADDR 0x80U 988 #define CSR_CURPSTATE0B_ADDR 0x81U 989 #define CSR_CLRWAKEUPSTICKY_ADDR 0x95U 990 #define CSR_WAKEUPMASK_ADDR 0x96U 991 #define CSR_CUSTPUBREV_ADDR 0xEDU 992 #define CSR_PUBREV_ADDR 0xEEU 993 994 /* APBONLY0 register offsets */ 995 #define CSR_MICROCONTMUXSEL_ADDR 0x0U 996 #define CSR_UCTSHADOWREGS_ADDR 0x4U 997 #define CSR_DCTWRITEONLY_ADDR 0x30U 998 #define CSR_DCTWRITEPROT_ADDR 0x31U 999 #define CSR_UCTWRITEONLYSHADOW_ADDR 0x32U 1000 #define CSR_UCTDATWRITEONLYSHADOW_ADDR 0x34U 1001 #define CSR_NEVERGATECSRCLOCK_ADDR 0x35U 1002 #define CSR_DFICFGRDDATAVALIDTICKS_ADDR 0x37U 1003 #define CSR_MICRORESET_ADDR 0x99U 1004 #define CSR_SEQUENCEROVERRIDE_ADDR 0xE7U 1005 #define CSR_DFIINITCOMPLETESHADOW_ADDR 0xFAU 1006 1007 /* ANIBx register bit fields */ 1008 /* CSR_MTESTMUXSEL */ 1009 #define CSR_MTESTMUXSEL_LSB 0 1010 #define CSR_MTESTMUXSEL_MASK GENMASK_32(5, 0) 1011 /* CSR_AFORCEDRVCONT */ 1012 #define CSR_AFORCEDRVCONT_LSB 0 1013 #define CSR_AFORCEDRVCONT_MASK GENMASK_32(3, 0) 1014 /* CSR_AFORCETRICONT */ 1015 #define CSR_AFORCETRICONT_LSB 0 1016 #define CSR_AFORCETRICONT_MASK GENMASK_32(3, 0) 1017 /* CSR_ATXIMPEDANCE */ 1018 #define CSR_ATXIMPEDANCE_LSB 0 1019 #define CSR_ATXIMPEDANCE_MASK GENMASK_32(9, 0) 1020 #define CSR_ADRVSTRENP_LSB 0 1021 #define CSR_ADRVSTRENP_MASK GENMASK_32(4, 0) 1022 #define CSR_ADRVSTRENN_LSB 5 1023 #define CSR_ADRVSTRENN_MASK GENMASK_32(9, 5) 1024 /* CSR_ATESTPRBSERR */ 1025 #define CSR_ATESTPRBSERR_LSB 0 1026 #define CSR_ATESTPRBSERR_MASK GENMASK_32(3, 0) 1027 /* CSR_ATXSLEWRATE */ 1028 #define CSR_ATXSLEWRATE_LSB 0 1029 #define CSR_ATXSLEWRATE_MASK GENMASK_32(10, 0) 1030 #define CSR_ATXPREP_LSB 0 1031 #define CSR_ATXPREP_MASK GENMASK_32(3, 0) 1032 #define CSR_ATXPREN_LSB 4 1033 #define CSR_ATXPREN_MASK GENMASK_32(7, 4) 1034 #define CSR_ATXPREDRVMODE_LSB 8 1035 #define CSR_ATXPREDRVMODE_MASK GENMASK_32(10, 8) 1036 /* CSR_ATESTPRBSERRCNT */ 1037 #define CSR_ATESTPRBSERRCNT_LSB 0 1038 #define CSR_ATESTPRBSERRCNT_MASK GENMASK_32(15, 0) 1039 /* CSR_ATXDLY */ 1040 #define CSR_ATXDLY_LSB 0 1041 #define CSR_ATXDLY_MASK GENMASK_32(6, 0) 1042 1043 /* DBYTEx register bit fields */ 1044 /* CSR_DBYTEMISCMODE */ 1045 #define CSR_DBYTEMISCMODE_LSB 2 1046 #define CSR_DBYTEMISCMODE_MASK BIT(2) 1047 #define CSR_DBYTEDISABLE_LSB 2 1048 #define CSR_DBYTEDISABLE_MASK BIT(2) 1049 /* CSR_TSMBYTE0 */ 1050 #define CSR_TSMBYTE0_LSB 0 1051 #define CSR_TSMBYTE0_MASK GENMASK_32(15, 0) 1052 #define CSR_PERPHTRAINEN_LSB 0 1053 #define CSR_PERPHTRAINEN_MASK BIT(0) 1054 #define CSR_EYEINC_LSB 1 1055 #define CSR_EYEINC_MASK BIT(1) 1056 #define CSR_EDGEINC_LSB 2 1057 #define CSR_EDGEINC_MASK BIT(2) 1058 #define CSR_EDGEEYEMXSEL_LSB 3 1059 #define CSR_EDGEEYEMXSEL_MASK BIT(3) 1060 #define CSR_TSMBYTE0RSVD_LSB 4 1061 #define CSR_TSMBYTE0RSVD_MASK GENMASK_32(5, 4) 1062 #define CSR_DIMMBROADINC_LSB 6 1063 #define CSR_DIMMBROADINC_MASK BIT(6) 1064 #define CSR_DIMMINC_LSB 7 1065 #define CSR_DIMMINC_MASK GENMASK_32(8, 7) 1066 #define CSR_COARSEINC_LSB 9 1067 #define CSR_COARSEINC_MASK BIT(9) 1068 #define CSR_DELAYINC_LSB 10 1069 #define CSR_DELAYINC_MASK BIT(10) 1070 #define CSR_RXINC_LSB 11 1071 #define CSR_RXINC_MASK BIT(11) 1072 #define CSR_RXPERTRAIN_LSB 12 1073 #define CSR_RXPERTRAIN_MASK BIT(12) 1074 #define CSR_TXPERTRAIN_LSB 13 1075 #define CSR_TXPERTRAIN_MASK BIT(13) 1076 #define CSR_DMTRAIN_LSB 14 1077 #define CSR_DMTRAIN_MASK BIT(14) 1078 #define CSR_WRLEVTRAIN_LSB 15 1079 #define CSR_WRLEVTRAIN_MASK BIT(15) 1080 /* CSR_TRAININGPARAM */ 1081 #define CSR_TRAININGPARAM_LSB 0 1082 #define CSR_TRAININGPARAM_MASK GENMASK_32(15, 0) 1083 #define CSR_ENDYNRATEREDUCTION_LSB 0 1084 #define CSR_ENDYNRATEREDUCTION_MASK BIT(0) 1085 #define CSR_TRAININGPARAM01RSVD_LSB 1 1086 #define CSR_TRAININGPARAM01RSVD_MASK BIT(1) 1087 #define CSR_TRAINENRXCLK_LSB 2 1088 #define CSR_TRAINENRXCLK_MASK BIT(2) 1089 #define CSR_TRAINENRXEN_LSB 3 1090 #define CSR_TRAINENRXEN_MASK BIT(3) 1091 #define CSR_TRAINENTXDQS_LSB 4 1092 #define CSR_TRAINENTXDQS_MASK BIT(4) 1093 #define CSR_TRAINENTXDQ_LSB 5 1094 #define CSR_TRAINENTXDQ_MASK BIT(5) 1095 #define CSR_TRAINENVREFDAC1_LSB 6 1096 #define CSR_TRAINENVREFDAC1_MASK BIT(6) 1097 #define CSR_TRAINENVREFDAC0_LSB 7 1098 #define CSR_TRAINENVREFDAC0_MASK BIT(7) 1099 #define CSR_TRAINENRXPBD_LSB 8 1100 #define CSR_TRAINENRXPBD_MASK BIT(8) 1101 #define CSR_ROLLINTOCOARSE_LSB 9 1102 #define CSR_ROLLINTOCOARSE_MASK BIT(9) 1103 #define CSR_TRAINUSINGNATIVEDDLCNTL_LSB 10 1104 #define CSR_TRAINUSINGNATIVEDDLCNTL_MASK BIT(10) 1105 #define CSR_TRAININGPARAM11RSVD_LSB 11 1106 #define CSR_TRAININGPARAM11RSVD_MASK BIT(11) 1107 #define CSR_TRAININGPARAM12RSVD_LSB 12 1108 #define CSR_TRAININGPARAM12RSVD_MASK BIT(12) 1109 #define CSR_INCDECRATE_LSB 13 1110 #define CSR_INCDECRATE_MASK GENMASK_32(15, 13) 1111 /* CSR_USEDQSENREPLICA */ 1112 #define CSR_USEDQSENREPLICA_LSB 0 1113 #define CSR_USEDQSENREPLICA_MASK BIT(0) 1114 /* CSR_RXTRAINPATTERNENABLE */ 1115 #define CSR_RXTRAINPATTERNENABLE_LSB 0 1116 #define CSR_RXTRAINPATTERNENABLE_MASK BIT(0) 1117 /* CSR_TSMBYTE1 */ 1118 #define CSR_TSMBYTE1_LSB 0 1119 #define CSR_TSMBYTE1_MASK GENMASK_32(15, 0) 1120 #define CSR_DTSMBDSTP_LSB 0 1121 #define CSR_DTSMBDSTP_MASK GENMASK_32(7, 0) 1122 #define CSR_DTSMGDSTP_LSB 8 1123 #define CSR_DTSMGDSTP_MASK GENMASK_32(15, 8) 1124 /* CSR_TSMBYTE2 */ 1125 #define CSR_TSMBYTE2_LSB 0 1126 #define CSR_TSMBYTE2_MASK GENMASK_32(15, 0) 1127 #define CSR_DTSMGDBAR_LSB 0 1128 #define CSR_DTSMGDBAR_MASK GENMASK_32(15, 0) 1129 /* CSR_TSMBYTE3 */ 1130 #define CSR_TSMBYTE3_LSB 0 1131 #define CSR_TSMBYTE3_MASK GENMASK_32(8, 0) 1132 #define CSR_DTSMINCDECMODE_LSB 0 1133 #define CSR_DTSMINCDECMODE_MASK BIT(0) 1134 #define CSR_DTSMINCDECCTRL_LSB 1 1135 #define CSR_DTSMINCDECCTRL_MASK BIT(1) 1136 #define CSR_ENBLRXSAMPFLOPS_LSB 2 1137 #define CSR_ENBLRXSAMPFLOPS_MASK BIT(2) 1138 #define CSR_SELRXSAMPFLOPS_LSB 3 1139 #define CSR_SELRXSAMPFLOPS_MASK BIT(3) 1140 #define CSR_SELRXBYBASS_LSB 4 1141 #define CSR_SELRXBYBASS_MASK BIT(4) 1142 #define CSR_DTSMIGNUPDATEACK_LSB 5 1143 #define CSR_DTSMIGNUPDATEACK_MASK BIT(5) 1144 #define CSR_ENABLERXDQASYNC_LSB 6 1145 #define CSR_ENABLERXDQASYNC_MASK BIT(6) 1146 #define CSR_DTSMSTATICCMPR_LSB 7 1147 #define CSR_DTSMSTATICCMPR_MASK BIT(7) 1148 #define CSR_DTSMSTATICCMPRVAL_LSB 8 1149 #define CSR_DTSMSTATICCMPRVAL_MASK BIT(8) 1150 /* CSR_TSMBYTE4 */ 1151 #define CSR_TSMBYTE4_LSB 0 1152 #define CSR_TSMBYTE4_MASK GENMASK_32(3, 0) 1153 #define CSR_DTSMINCDECPW_LSB 0 1154 #define CSR_DTSMINCDECPW_MASK GENMASK_32(3, 0) 1155 /* CSR_TESTMODECONFIG */ 1156 #define CSR_TESTMODECONFIG_LSB 0 1157 #define CSR_TESTMODECONFIG_MASK GENMASK_32(9, 0) 1158 #define CSR_LOOPBACKEN_LSB 0 1159 #define CSR_LOOPBACKEN_MASK BIT(0) 1160 #define CSR_RSVDTESTDLLEN_LSB 1 1161 #define CSR_RSVDTESTDLLEN_MASK BIT(1) 1162 #define CSR_RSVDTWOTCKTXDQSPRE_LSB 2 1163 #define CSR_RSVDTWOTCKTXDQSPRE_MASK BIT(2) 1164 #define CSR_TESTMODERSVD_LSB 3 1165 #define CSR_TESTMODERSVD_MASK GENMASK_32(7, 3) 1166 #define CSR_LOOPBACKDISDQSTRI_LSB 8 1167 #define CSR_LOOPBACKDISDQSTRI_MASK BIT(8) 1168 #define CSR_RSVDDISTXDQEQPREAMBLE_LSB 9 1169 #define CSR_RSVDDISTXDQEQPREAMBLE_MASK BIT(9) 1170 /* CSR_TSMBYTE5 */ 1171 #define CSR_TSMBYTE5_LSB 0 1172 #define CSR_TSMBYTE5_MASK GENMASK_32(15, 0) 1173 #define CSR_DTSMBDBAR_LSB 0 1174 #define CSR_DTSMBDBAR_MASK GENMASK_32(15, 0) 1175 /* MTESTMUXSEL already defined in ANIBx section */ 1176 /* CSR_DTSMTRAINMODECTRL */ 1177 #define CSR_DTSMTRAINMODECTRL_LSB 0 1178 #define CSR_DTSMTRAINMODECTRL_MASK GENMASK_32(3, 0) 1179 #define CSR_DTSMSOELANEMODE_LSB 0 1180 #define CSR_DTSMSOELANEMODE_MASK GENMASK_32(1, 0) 1181 #define CSR_DTSMBYTEERRANDMODE_LSB 2 1182 #define CSR_DTSMBYTEERRANDMODE_MASK BIT(2) 1183 #define CSR_DTSMNIBERRMODE_LSB 3 1184 #define CSR_DTSMNIBERRMODE_MASK BIT(3) 1185 /* CSR_DFIMRL */ 1186 #define CSR_DFIMRL_LSB 0 1187 #define CSR_DFIMRL_MASK GENMASK_32(4, 0) 1188 /* CSR_ASYNCDBYTEMODE */ 1189 #define CSR_ASYNCDBYTEMODE_LSB 0 1190 #define CSR_ASYNCDBYTEMODE_MASK GENMASK_32(8, 0) 1191 /* CSR_ASYNCDBYTETXEN */ 1192 #define CSR_ASYNCDBYTETXEN_LSB 0 1193 #define CSR_ASYNCDBYTETXEN_MASK GENMASK_32(11, 0) 1194 /* CSR_ASYNCDBYTETXDATA */ 1195 #define CSR_ASYNCDBYTETXDATA_LSB 0 1196 #define CSR_ASYNCDBYTETXDATA_MASK GENMASK_32(11, 0) 1197 /* CSR_ASYNCDBYTERXDATA */ 1198 #define CSR_ASYNCDBYTERXDATA_LSB 0 1199 #define CSR_ASYNCDBYTERXDATA_MASK GENMASK_32(11, 0) 1200 /* CSR_VREFDAC1 */ 1201 #define CSR_VREFDAC1_LSB 0 1202 #define CSR_VREFDAC1_MASK GENMASK_32(6, 0) 1203 /* CSR_TRAININGCNTR */ 1204 #define CSR_TRAININGCNTR_LSB 0 1205 #define CSR_TRAININGCNTR_MASK GENMASK_32(15, 0) 1206 #define CSR_TRAININGCNTRFINE_LSB 0 1207 #define CSR_TRAININGCNTRFINE_MASK GENMASK_32(9, 0) 1208 #define CSR_TRAININGCNTRCOARSE_LSB 10 1209 #define CSR_TRAININGCNTRCOARSE_MASK GENMASK_32(15, 10) 1210 /* CSR_VREFDAC0 */ 1211 #define CSR_VREFDAC0_LSB 0 1212 #define CSR_VREFDAC0_MASK GENMASK_32(6, 0) 1213 /* CSR_TXIMPEDANCECTRL0 */ 1214 #define CSR_TXIMPEDANCECTRL0_LSB 0 1215 #define CSR_TXIMPEDANCECTRL0_MASK GENMASK_32(11, 0) 1216 #define CSR_DRVSTRENDQP_LSB 0 1217 #define CSR_DRVSTRENDQP_MASK GENMASK_32(5, 0) 1218 #define CSR_DRVSTRENDQN_LSB 6 1219 #define CSR_DRVSTRENDQN_MASK GENMASK_32(11, 6) 1220 /* CSR_DQDQSRCVCNTRL */ 1221 #define CSR_DQDQSRCVCNTRL_LSB 0 1222 #define CSR_DQDQSRCVCNTRL_MASK GENMASK_32(15, 0) 1223 #define CSR_SELANALOGVREF_LSB 0 1224 #define CSR_SELANALOGVREF_MASK BIT(0) 1225 #define CSR_EXTVREFRANGE_LSB 1 1226 #define CSR_EXTVREFRANGE_MASK BIT(1) 1227 #define CSR_DFECTRL_LSB 2 1228 #define CSR_DFECTRL_MASK GENMASK_32(3, 2) 1229 #define CSR_MAJORMODEDBYTE_LSB 4 1230 #define CSR_MAJORMODEDBYTE_MASK GENMASK_32(6, 4) 1231 #define CSR_GAINCURRADJ_LSB 7 1232 #define CSR_GAINCURRADJ_MASK GENMASK_32(11, 7) 1233 #define CSR_RESERVED_LSB 12 1234 #define CSR_RESERVED_MASK GENMASK_32(15, 12) 1235 /* CSR_TXEQUALIZATIONMODE */ 1236 #define CSR_TXEQUALIZATIONMODE_LSB 0 1237 #define CSR_TXEQUALIZATIONMODE_MASK GENMASK_32(1, 0) 1238 #define CSR_TXEQMODE_LSB 0 1239 #define CSR_TXEQMODE_MASK GENMASK_32(1, 0) 1240 /* CSR_TXIMPEDANCECTRL1 */ 1241 #define CSR_TXIMPEDANCECTRL1_LSB 0 1242 #define CSR_TXIMPEDANCECTRL1_MASK GENMASK_32(11, 0) 1243 #define CSR_DRVSTRENFSDQP_LSB 0 1244 #define CSR_DRVSTRENFSDQP_MASK GENMASK_32(5, 0) 1245 #define CSR_DRVSTRENFSDQN_LSB 6 1246 #define CSR_DRVSTRENFSDQN_MASK GENMASK_32(11, 6) 1247 /* CSR_DQDQSRCVCNTRL1 */ 1248 #define CSR_DQDQSRCVCNTRL1_LSB 0 1249 #define CSR_DQDQSRCVCNTRL1_MASK GENMASK_32(11, 0) 1250 #define CSR_POWERDOWNRCVR_LSB 0 1251 #define CSR_POWERDOWNRCVR_MASK GENMASK_32(8, 0) 1252 #define CSR_POWERDOWNRCVRDQS_LSB 9 1253 #define CSR_POWERDOWNRCVRDQS_MASK BIT(9) 1254 #define CSR_RXPADSTANDBYEN_LSB 10 1255 #define CSR_RXPADSTANDBYEN_MASK BIT(10) 1256 #define CSR_ENLPREQPDR_LSB 11 1257 #define CSR_ENLPREQPDR_MASK BIT(11) 1258 /* CSR_TXIMPEDANCECTRL2 */ 1259 #define CSR_TXIMPEDANCECTRL2_LSB 0 1260 #define CSR_TXIMPEDANCECTRL2_MASK GENMASK_32(11, 0) 1261 #define CSR_DRVSTRENEQHIDQP_LSB 0 1262 #define CSR_DRVSTRENEQHIDQP_MASK GENMASK_32(5, 0) 1263 #define CSR_DRVSTRENEQLODQN_LSB 6 1264 #define CSR_DRVSTRENEQLODQN_MASK GENMASK_32(11, 6) 1265 /* CSR_DQDQSRCVCNTRL2 */ 1266 #define CSR_DQDQSRCVCNTRL2_LSB 0 1267 #define CSR_DQDQSRCVCNTRL2_MASK BIT(0) 1268 #define CSR_ENRXAGRESSIVEPDR_LSB 0 1269 #define CSR_ENRXAGRESSIVEPDR_MASK BIT(0) 1270 /* CSR_TXODTDRVSTREN */ 1271 #define CSR_TXODTDRVSTREN_LSB 0 1272 #define CSR_TXODTDRVSTREN_MASK GENMASK_32(11, 0) 1273 #define CSR_ODTSTRENP_LSB 0 1274 #define CSR_ODTSTRENP_MASK GENMASK_32(5, 0) 1275 #define CSR_ODTSTRENN_LSB 6 1276 #define CSR_ODTSTRENN_MASK GENMASK_32(11, 6) 1277 /* CSR_RXFIFOCHECKSTATUS */ 1278 #define CSR_RXFIFOCHECKSTATUS_LSB 0 1279 #define CSR_RXFIFOCHECKSTATUS_MASK GENMASK_32(1, 0) 1280 #define CSR_RXFIFOLOCERR_LSB 0 1281 #define CSR_RXFIFOLOCERR_MASK BIT(0) 1282 #define CSR_RXFIFOLOCUERR_LSB 1 1283 #define CSR_RXFIFOLOCUERR_MASK BIT(1) 1284 /* CSR_RXFIFOCHECKERRVALUES */ 1285 #define CSR_RXFIFOCHECKERRVALUES_LSB 0 1286 #define CSR_RXFIFOCHECKERRVALUES_MASK GENMASK_32(15, 0) 1287 #define CSR_RXFIFORDLOCERRVALUE_LSB 0 1288 #define CSR_RXFIFORDLOCERRVALUE_MASK GENMASK_32(3, 0) 1289 #define CSR_RXFIFOWRLOCERRVALUE_LSB 4 1290 #define CSR_RXFIFOWRLOCERRVALUE_MASK GENMASK_32(7, 4) 1291 #define CSR_RXFIFORDLOCUERRVALUE_LSB 8 1292 #define CSR_RXFIFORDLOCUERRVALUE_MASK GENMASK_32(11, 8) 1293 #define CSR_RXFIFOWRLOCUERRVALUE_LSB 12 1294 #define CSR_RXFIFOWRLOCUERRVALUE_MASK GENMASK_32(15, 12) 1295 /* CSR_RXFIFOINFO */ 1296 #define CSR_RXFIFOINFO_LSB 0 1297 #define CSR_RXFIFOINFO_MASK GENMASK_32(15, 0) 1298 #define CSR_RXFIFORDLOC_LSB 0 1299 #define CSR_RXFIFORDLOC_MASK GENMASK_32(3, 0) 1300 #define CSR_RXFIFOWRLOC_LSB 4 1301 #define CSR_RXFIFOWRLOC_MASK GENMASK_32(7, 4) 1302 #define CSR_RXFIFORDLOCU_LSB 8 1303 #define CSR_RXFIFORDLOCU_MASK GENMASK_32(11, 8) 1304 #define CSR_RXFIFOWRLOCU_LSB 12 1305 #define CSR_RXFIFOWRLOCU_MASK GENMASK_32(15, 12) 1306 /* CSR_RXFIFOVISIBILITY */ 1307 #define CSR_RXFIFOVISIBILITY_LSB 0 1308 #define CSR_RXFIFOVISIBILITY_MASK GENMASK_32(4, 0) 1309 #define CSR_RXFIFORDPTR_LSB 0 1310 #define CSR_RXFIFORDPTR_MASK GENMASK_32(2, 0) 1311 #define CSR_RXFIFORDPTROVR_LSB 3 1312 #define CSR_RXFIFORDPTROVR_MASK BIT(3) 1313 #define CSR_RXFIFORDEN_LSB 4 1314 #define CSR_RXFIFORDEN_MASK BIT(4) 1315 /* CSR_RXFIFOCONTENTSDQ3210 */ 1316 #define CSR_RXFIFOCONTENTSDQ3210_LSB 0 1317 #define CSR_RXFIFOCONTENTSDQ3210_MASK GENMASK_32(15, 0) 1318 /* CSR_RXFIFOCONTENTSDQ7654 */ 1319 #define CSR_RXFIFOCONTENTSDQ7654_LSB 0 1320 #define CSR_RXFIFOCONTENTSDQ7654_MASK GENMASK_32(15, 0) 1321 /* CSR_RXFIFOCONTENTSDBI */ 1322 #define CSR_RXFIFOCONTENTSDBI_LSB 0 1323 #define CSR_RXFIFOCONTENTSDBI_MASK GENMASK_32(3, 0) 1324 /* CSR_TXSLEWRATE */ 1325 #define CSR_TXSLEWRATE_LSB 0 1326 #define CSR_TXSLEWRATE_MASK GENMASK_32(10, 0) 1327 #define CSR_TXPREP_LSB 0 1328 #define CSR_TXPREP_MASK GENMASK_32(3, 0) 1329 #define CSR_TXPREN_LSB 4 1330 #define CSR_TXPREN_MASK GENMASK_32(7, 4) 1331 #define CSR_TXPREDRVMODE_LSB 8 1332 #define CSR_TXPREDRVMODE_MASK GENMASK_32(10, 8) 1333 /* CSR_TRAININGINCDECDTSMEN */ 1334 #define CSR_TRAININGINCDECDTSMEN_LSB 0 1335 #define CSR_TRAININGINCDECDTSMEN_MASK GENMASK_32(8, 0) 1336 /* CSR_RXPBDLYTG0 */ 1337 #define CSR_RXPBDLYTG0_LSB 0 1338 #define CSR_RXPBDLYTG0_MASK GENMASK_32(6, 0) 1339 /* CSR_RXPBDLYTG1 */ 1340 #define CSR_RXPBDLYTG1_LSB 0 1341 #define CSR_RXPBDLYTG1_MASK GENMASK_32(6, 0) 1342 /* CSR_RXPBDLYTG2 */ 1343 #define CSR_RXPBDLYTG2_LSB 0 1344 #define CSR_RXPBDLYTG2_MASK GENMASK_32(6, 0) 1345 /* CSR_RXPBDLYTG3 */ 1346 #define CSR_RXPBDLYTG3_LSB 0 1347 #define CSR_RXPBDLYTG3_MASK GENMASK_32(6, 0) 1348 /* CSR_RXENDLYTG0 */ 1349 #define CSR_RXENDLYTG0_LSB 0 1350 #define CSR_RXENDLYTG0_MASK GENMASK_32(10, 0) 1351 /* CSR_RXENDLYTG1 */ 1352 #define CSR_RXENDLYTG1_LSB 0 1353 #define CSR_RXENDLYTG1_MASK GENMASK_32(10, 0) 1354 /* CSR_RXENDLYTG2 */ 1355 #define CSR_RXENDLYTG2_LSB 0 1356 #define CSR_RXENDLYTG2_MASK GENMASK_32(10, 0) 1357 /* CSR_RXENDLYTG3 */ 1358 #define CSR_RXENDLYTG3_LSB 0 1359 #define CSR_RXENDLYTG3_MASK GENMASK_32(10, 0) 1360 /* CSR_RXCLKDLYTG0 */ 1361 #define CSR_RXCLKDLYTG0_LSB 0 1362 #define CSR_RXCLKDLYTG0_MASK GENMASK_32(5, 0) 1363 /* CSR_RXCLKDLYTG1 */ 1364 #define CSR_RXCLKDLYTG1_LSB 0 1365 #define CSR_RXCLKDLYTG1_MASK GENMASK_32(5, 0) 1366 /* CSR_RXCLKDLYTG2 */ 1367 #define CSR_RXCLKDLYTG2_LSB 0 1368 #define CSR_RXCLKDLYTG2_MASK GENMASK_32(5, 0) 1369 /* CSR_RXCLKDLYTG3 */ 1370 #define CSR_RXCLKDLYTG3_LSB 0 1371 #define CSR_RXCLKDLYTG3_MASK GENMASK_32(5, 0) 1372 /* CSR_RXCLKCDLYTG0 */ 1373 #define CSR_RXCLKCDLYTG0_LSB 0 1374 #define CSR_RXCLKCDLYTG0_MASK GENMASK_32(5, 0) 1375 /* CSR_RXCLKCDLYTG1 */ 1376 #define CSR_RXCLKCDLYTG1_LSB 0 1377 #define CSR_RXCLKCDLYTG1_MASK GENMASK_32(5, 0) 1378 /* CSR_RXCLKCDLYTG2 */ 1379 #define CSR_RXCLKCDLYTG2_LSB 0 1380 #define CSR_RXCLKCDLYTG2_MASK GENMASK_32(5, 0) 1381 /* CSR_RXCLKCDLYTG3 */ 1382 #define CSR_RXCLKCDLYTG3_LSB 0 1383 #define CSR_RXCLKCDLYTG3_MASK GENMASK_32(5, 0) 1384 /* CSR_DQ0LNSEL */ 1385 #define CSR_DQ0LNSEL_LSB 0 1386 #define CSR_DQ0LNSEL_MASK GENMASK_32(2, 0) 1387 /* CSR_DQ1LNSEL */ 1388 #define CSR_DQ1LNSEL_LSB 0 1389 #define CSR_DQ1LNSEL_MASK GENMASK_32(2, 0) 1390 /* CSR_DQ2LNSEL */ 1391 #define CSR_DQ2LNSEL_LSB 0 1392 #define CSR_DQ2LNSEL_MASK GENMASK_32(2, 0) 1393 /* CSR_DQ3LNSEL */ 1394 #define CSR_DQ3LNSEL_LSB 0 1395 #define CSR_DQ3LNSEL_MASK GENMASK_32(2, 0) 1396 /* CSR_DQ4LNSEL */ 1397 #define CSR_DQ4LNSEL_LSB 0 1398 #define CSR_DQ4LNSEL_MASK GENMASK_32(2, 0) 1399 /* CSR_DQ5LNSEL */ 1400 #define CSR_DQ5LNSEL_LSB 0 1401 #define CSR_DQ5LNSEL_MASK GENMASK_32(2, 0) 1402 /* CSR_DQ6LNSEL */ 1403 #define CSR_DQ6LNSEL_LSB 0 1404 #define CSR_DQ6LNSEL_MASK GENMASK_32(2, 0) 1405 /* CSR_DQ7LNSEL */ 1406 #define CSR_DQ7LNSEL_LSB 0 1407 #define CSR_DQ7LNSEL_MASK GENMASK_32(2, 0) 1408 /* CSR_PPTCTLSTATIC */ 1409 #define CSR_PPTCTLSTATIC_LSB 0 1410 #define CSR_PPTCTLSTATIC_MASK GENMASK_32(11, 0) 1411 #define CSR_PPTENDQS2DQTG0_LSB 0 1412 #define CSR_PPTENDQS2DQTG0_MASK BIT(0) 1413 #define CSR_PPTENDQS2DQTG1_LSB 1 1414 #define CSR_PPTENDQS2DQTG1_MASK BIT(1) 1415 #define CSR_DOCBYTESELTG0_LSB 2 1416 #define CSR_DOCBYTESELTG0_MASK BIT(2) 1417 #define CSR_DOCBYTESELTG1_LSB 3 1418 #define CSR_DOCBYTESELTG1_MASK BIT(3) 1419 #define CSR_PPTINFOSEL_LSB 4 1420 #define CSR_PPTINFOSEL_MASK GENMASK_32(7, 4) 1421 #define CSR_PPTENRXENDLYTG0_LSB 8 1422 #define CSR_PPTENRXENDLYTG0_MASK BIT(8) 1423 #define CSR_PPTENRXENDLYTG1_LSB 9 1424 #define CSR_PPTENRXENDLYTG1_MASK BIT(9) 1425 #define CSR_PPTENRXENBACKOFF_LSB 10 1426 #define CSR_PPTENRXENBACKOFF_MASK GENMASK_32(11, 10) 1427 /* CSR_PPTCTLDYN */ 1428 #define CSR_PPTCTLDYN_LSB 0 1429 #define CSR_PPTCTLDYN_MASK GENMASK_32(1, 0) 1430 #define CSR_PPTDQS2DQACTIVE_LSB 0 1431 #define CSR_PPTDQS2DQACTIVE_MASK BIT(0) 1432 #define CSR_PPTENRXENUSEDQSSAMPVAL_LSB 1 1433 #define CSR_PPTENRXENUSEDQSSAMPVAL_MASK BIT(1) 1434 /* CSR_PPTINFO */ 1435 #define CSR_PPTINFO_LSB 0 1436 #define CSR_PPTINFO_MASK GENMASK_32(15, 0) 1437 /* CSR_PPTRXENEVNT */ 1438 #define CSR_PPTRXENEVNT_LSB 0 1439 #define CSR_PPTRXENEVNT_MASK GENMASK_32(1, 0) 1440 #define CSR_PPTRXENINIT_LSB 0 1441 #define CSR_PPTRXENINIT_MASK BIT(0) 1442 #define CSR_PPTRXENMHUI_LSB 1 1443 #define CSR_PPTRXENMHUI_MASK BIT(1) 1444 /* CSR_PPTDQSCNTINVTRNTG0 */ 1445 #define CSR_PPTDQSCNTINVTRNTG0_LSB 0 1446 #define CSR_PPTDQSCNTINVTRNTG0_MASK GENMASK_32(15, 0) 1447 /* CSR_PPTDQSCNTINVTRNTG1 */ 1448 #define CSR_PPTDQSCNTINVTRNTG1_LSB 0 1449 #define CSR_PPTDQSCNTINVTRNTG1_MASK GENMASK_32(15, 0) 1450 /* CSR_DTSMBLANKINGCTRL */ 1451 #define CSR_DTSMBLANKINGCTRL_LSB 0 1452 #define CSR_DTSMBLANKINGCTRL_MASK GENMASK_32(9, 0) 1453 #define CSR_DTSMBLANK_LSB 0 1454 #define CSR_DTSMBLANK_MASK GENMASK_32(9, 0) 1455 /* CSR_TSM0 */ 1456 #define CSR_TSM0_LSB 0 1457 #define CSR_TSM0_MASK GENMASK_32(13, 0) 1458 #define CSR_DTSMENB_LSB 0 1459 #define CSR_DTSMENB_MASK BIT(0) 1460 #define CSR_DTSMDIR_LSB 1 1461 #define CSR_DTSMDIR_MASK BIT(1) 1462 #define CSR_DTSMIGNFRST_LSB 2 1463 #define CSR_DTSMIGNFRST_MASK BIT(2) 1464 #define CSR_DTSMODDPHASE_LSB 3 1465 #define CSR_DTSMODDPHASE_MASK BIT(3) 1466 #define CSR_DTSMFLTPRE_LSB 4 1467 #define CSR_DTSMFLTPRE_MASK BIT(4) 1468 #define CSR_DTSMFLTCUR_LSB 5 1469 #define CSR_DTSMFLTCUR_MASK BIT(5) 1470 #define CSR_DTSMFLTNXT_LSB 6 1471 #define CSR_DTSMFLTNXT_MASK BIT(6) 1472 #define CSR_DTSMFLTVAL_LSB 7 1473 #define CSR_DTSMFLTVAL_MASK GENMASK_32(9, 7) 1474 #define CSR_DTSMMSKBIT_LSB 10 1475 #define CSR_DTSMMSKBIT_MASK GENMASK_32(13, 10) 1476 /* CSR_TSM1 */ 1477 #define CSR_TSM1_LSB 0 1478 #define CSR_TSM1_MASK GENMASK_32(15, 0) 1479 #define CSR_DTSMERRCNT_LSB 0 1480 #define CSR_DTSMERRCNT_MASK GENMASK_32(15, 0) 1481 /* CSR_TSM2 */ 1482 #define CSR_TSM2_LSB 0 1483 #define CSR_TSM2_MASK BIT(0) 1484 #define CSR_DTSMDISERRCHK_LSB 0 1485 #define CSR_DTSMDISERRCHK_MASK BIT(0) 1486 /* CSR_TSM3 */ 1487 #define CSR_TSM3_LSB 0 1488 #define CSR_TSM3_MASK GENMASK_32(9, 0) 1489 #define CSR_DTSMCLRERRCNTMSK_LSB 0 1490 #define CSR_DTSMCLRERRCNTMSK_MASK GENMASK_32(8, 0) 1491 #define CSR_DTSMCLRERRCNT_LSB 9 1492 #define CSR_DTSMCLRERRCNT_MASK BIT(9) 1493 /* CSR_TXCHKDATASELECTS */ 1494 #define CSR_TXCHKDATASELECTS_LSB 0 1495 #define CSR_TXCHKDATASELECTS_MASK GENMASK_32(1, 0) 1496 #define CSR_SELCHKTOTX_LSB 0 1497 #define CSR_SELCHKTOTX_MASK BIT(0) 1498 #define CSR_SELTXTOCHK_LSB 1 1499 #define CSR_SELTXTOCHK_MASK BIT(1) 1500 /* CSR_DTSMUPTHLDXINGIND */ 1501 #define CSR_DTSMUPTHLDXINGIND_LSB 0 1502 #define CSR_DTSMUPTHLDXINGIND_MASK GENMASK_32(8, 0) 1503 /* CSR_DTSMLOTHLDXINGIND */ 1504 #define CSR_DTSMLOTHLDXINGIND_LSB 0 1505 #define CSR_DTSMLOTHLDXINGIND_MASK GENMASK_32(8, 0) 1506 /* CSR_DBYTEALLDTSMCTRL0 */ 1507 #define CSR_DBYTEALLDTSMCTRL0_LSB 0 1508 #define CSR_DBYTEALLDTSMCTRL0_MASK GENMASK_32(8, 0) 1509 #define CSR_DTSMINHIBDTSM_LSB 0 1510 #define CSR_DTSMINHIBDTSM_MASK GENMASK_32(8, 0) 1511 /* CSR_DBYTEALLDTSMCTRL1 */ 1512 #define CSR_DBYTEALLDTSMCTRL1_LSB 0 1513 #define CSR_DBYTEALLDTSMCTRL1_MASK GENMASK_32(8, 0) 1514 #define CSR_DTSMGATEINC_LSB 0 1515 #define CSR_DTSMGATEINC_MASK GENMASK_32(8, 0) 1516 /* CSR_DBYTEALLDTSMCTRL2 */ 1517 #define CSR_DBYTEALLDTSMCTRL2_LSB 0 1518 #define CSR_DBYTEALLDTSMCTRL2_MASK GENMASK_32(8, 0) 1519 #define CSR_DTSMGATEDEC_LSB 0 1520 #define CSR_DTSMGATEDEC_MASK GENMASK_32(8, 0) 1521 /* CSR_TXDQDLYTG0 */ 1522 #define CSR_TXDQDLYTG0_LSB 0 1523 #define CSR_TXDQDLYTG0_MASK GENMASK_32(8, 0) 1524 /* CSR_TXDQDLYTG1 */ 1525 #define CSR_TXDQDLYTG1_LSB 0 1526 #define CSR_TXDQDLYTG1_MASK GENMASK_32(8, 0) 1527 /* CSR_TXDQDLYTG2 */ 1528 #define CSR_TXDQDLYTG2_LSB 0 1529 #define CSR_TXDQDLYTG2_MASK GENMASK_32(8, 0) 1530 /* CSR_TXDQDLYTG3 */ 1531 #define CSR_TXDQDLYTG3_LSB 0 1532 #define CSR_TXDQDLYTG3_MASK GENMASK_32(8, 0) 1533 /* CSR_TXDQSDLYTG0 */ 1534 #define CSR_TXDQSDLYTG0_LSB 0 1535 #define CSR_TXDQSDLYTG0_MASK GENMASK_32(9, 0) 1536 /* CSR_TXDQSDLYTG1 */ 1537 #define CSR_TXDQSDLYTG1_LSB 0 1538 #define CSR_TXDQSDLYTG1_MASK GENMASK_32(9, 0) 1539 /* CSR_TXDQSDLYTG2 */ 1540 #define CSR_TXDQSDLYTG2_LSB 0 1541 #define CSR_TXDQSDLYTG2_MASK GENMASK_32(9, 0) 1542 /* CSR_TXDQSDLYTG3 */ 1543 #define CSR_TXDQSDLYTG3_LSB 0 1544 #define CSR_TXDQSDLYTG3_MASK GENMASK_32(9, 0) 1545 /* CSR_DXLCDLSTATUS_ADDR */ 1546 #define CSR_DXLCDLSTATUS_LSB 0 1547 #define CSR_DXLCDLSTATUS_MASK GENMASK_32(13, 0) 1548 #define CSR_DXLCDLFINESNAPVAL_LSB 0 1549 #define CSR_DXLCDLFINESNAPVAL_MASK GENMASK_32(9, 0) 1550 #define CSR_DXLCDLPHDSNAPVAL_LSB 10 1551 #define CSR_DXLCDLPHDSNAPVAL_MASK BIT(10) 1552 #define CSR_DXLCDLSTICKYLOCK_LSB 11 1553 #define CSR_DXLCDLSTICKYLOCK_MASK BIT(11) 1554 #define CSR_DXLCDLSTICKYUNLOCK_LSB 12 1555 #define CSR_DXLCDLSTICKYUNLOCK_MASK BIT(12) 1556 #define CSR_DXLCDLLIVELOCK_LSB 13 1557 #define CSR_DXLCDLLIVELOCK_MASK BIT(13) 1558 1559 /* MASTER0 register offsets */ 1560 /* CSR_RXFIFOINIT */ 1561 #define CSR_RXFIFOINIT_LSB 0 1562 #define CSR_RXFIFOINIT_MASK GENMASK_32(1, 0) 1563 #define CSR_RXFIFOINITPTR_LSB 0 1564 #define CSR_RXFIFOINITPTR_MASK BIT(0) 1565 #define CSR_INHIBITRXFIFORD_LSB 1 1566 #define CSR_INHIBITRXFIFORD_MASK BIT(1) 1567 /* CSR_FORCECLKDISABLE */ 1568 #define CSR_FORCECLKDISABLE_LSB 0 1569 #define CSR_FORCECLKDISABLE_MASK GENMASK_32(3, 0) 1570 /* CSR_CLOCKINGCTRL */ 1571 #define CSR_CLOCKINGCTRL_LSB 0 1572 #define CSR_CLOCKINGCTRL_MASK GENMASK_32(1, 0) 1573 #define CSR_PCLKENASYNCCTRL_LSB 0 1574 #define CSR_PCLKENASYNCCTRL_MASK BIT(0) 1575 #define CSR_DLLTRACKENCTRL_LSB 1 1576 #define CSR_DLLTRACKENCTRL_MASK BIT(1) 1577 /* CSR_FORCEINTERNALUPDATE */ 1578 #define CSR_FORCEINTERNALUPDATE_LSB 0 1579 #define CSR_FORCEINTERNALUPDATE_MASK BIT(0) 1580 /* CSR_PHYCONFIG */ 1581 #define CSR_PHYCONFIG_LSB 0 1582 #define CSR_PHYCONFIG_MASK GENMASK_32(9, 0) 1583 #define CSR_PHYCONFIGANIBS_LSB 0 1584 #define CSR_PHYCONFIGANIBS_MASK GENMASK_32(3, 0) 1585 #define CSR_PHYCONFIGDBYTES_LSB 4 1586 #define CSR_PHYCONFIGDBYTES_MASK GENMASK_32(7, 4) 1587 #define CSR_PHYCONFIGDFI_LSB 8 1588 #define CSR_PHYCONFIGDFI_MASK GENMASK_32(9, 8) 1589 /* CSR_PGCR */ 1590 #define CSR_PGCR_LSB 0 1591 #define CSR_PGCR_MASK BIT(0) 1592 #define CSR_RXCLKRISEFALLMODE_LSB 0 1593 #define CSR_RXCLKRISEFALLMODE_MASK BIT(0) 1594 /* CSR_TESTBUMPCNTRL1 */ 1595 #define CSR_TESTBUMPCNTRL1_LSB 0 1596 #define CSR_TESTBUMPCNTRL1_MASK GENMASK_32(15, 0) 1597 #define CSR_TESTMAJORMODE_LSB 0 1598 #define CSR_TESTMAJORMODE_MASK GENMASK_32(2, 0) 1599 #define CSR_TESTBIASBYPASSEN_LSB 3 1600 #define CSR_TESTBIASBYPASSEN_MASK BIT(3) 1601 #define CSR_TESTANALOGOUTCTRL_LSB 4 1602 #define CSR_TESTANALOGOUTCTRL_MASK GENMASK_32(7, 4) 1603 #define CSR_TESTGAINCURRADJ_LSB 8 1604 #define CSR_TESTGAINCURRADJ_MASK GENMASK_32(12, 8) 1605 #define CSR_TESTSELEXTERNALVREF_LSB 13 1606 #define CSR_TESTSELEXTERNALVREF_MASK BIT(13) 1607 #define CSR_TESTEXTVREFRANGE_LSB 14 1608 #define CSR_TESTEXTVREFRANGE_MASK BIT(14) 1609 #define CSR_TESTPOWERGATEEN_LSB 15 1610 #define CSR_TESTPOWERGATEEN_MASK BIT(15) 1611 /* CSR_CALUCLKINFO */ 1612 #define CSR_CALUCLKINFO_LSB 0 1613 #define CSR_CALUCLKINFO_MASK GENMASK_32(10, 0) 1614 #define CSR_CALUCLKTICKSPER1US_LSB 0 1615 #define CSR_CALUCLKTICKSPER1US_MASK GENMASK_32(10, 0) 1616 /* CSR_TESTBUMPCNTRL */ 1617 #define CSR_TESTBUMPCNTRL_LSB 0 1618 #define CSR_TESTBUMPCNTRL_MASK GENMASK_32(9, 0) 1619 #define CSR_TESTBUMPEN_LSB 0 1620 #define CSR_TESTBUMPEN_MASK GENMASK_32(1, 0) 1621 #define CSR_TESTBUMPTOGGLE_LSB 2 1622 #define CSR_TESTBUMPTOGGLE_MASK BIT(2) 1623 #define CSR_TESTBUMPDATASEL_LSB 3 1624 #define CSR_TESTBUMPDATASEL_MASK GENMASK_32(8, 3) 1625 #define CSR_FORCEMTESTONALERT_LSB 9 1626 #define CSR_FORCEMTESTONALERT_MASK BIT(9) 1627 /* CSR_SEQ0BDLY0 */ 1628 #define CSR_SEQ0BDLY0_LSB 0 1629 #define CSR_SEQ0BDLY0_MASK GENMASK_32(15, 0) 1630 /* CSR_SEQ0BDLY1 */ 1631 #define CSR_SEQ0BDLY1_LSB 0 1632 #define CSR_SEQ0BDLY1_MASK GENMASK_32(15, 0) 1633 /* CSR_SEQ0BDLY2 */ 1634 #define CSR_SEQ0BDLY2_LSB 0 1635 #define CSR_SEQ0BDLY2_MASK GENMASK_32(15, 0) 1636 /* CSR_SEQ0BDLY3 */ 1637 #define CSR_SEQ0BDLY3_LSB 0 1638 #define CSR_SEQ0BDLY3_MASK GENMASK_32(15, 0) 1639 /* CSR_PHYALERTSTATUS */ 1640 #define CSR_PHYALERTSTATUS_LSB 0 1641 #define CSR_PHYALERTSTATUS_MASK BIT(0) 1642 #define CSR_PHYALERT_LSB 0 1643 #define CSR_PHYALERT_MASK BIT(0) 1644 /* CSR_PPTTRAINSETUP */ 1645 #define CSR_PPTTRAINSETUP_LSB 0 1646 #define CSR_PPTTRAINSETUP_MASK GENMASK_32(6, 0) 1647 #define CSR_PHYMSTRTRAININTERVAL_LSB 0 1648 #define CSR_PHYMSTRTRAININTERVAL_MASK GENMASK_32(3, 0) 1649 #define CSR_PHYMSTRMAXREQTOACK_LSB 4 1650 #define CSR_PHYMSTRMAXREQTOACK_MASK GENMASK_32(6, 4) 1651 /* CSR_PPTTRAINSETUP2 */ 1652 #define CSR_PPTTRAINSETUP2_LSB 0 1653 #define CSR_PPTTRAINSETUP2_MASK GENMASK_32(2, 0) 1654 #define CSR_PHYMSTRFREQOVERRIDE_LSB 0 1655 #define CSR_PHYMSTRFREQOVERRIDE_MASK GENMASK_32(2, 0) 1656 /* CSR_ATESTMODE */ 1657 #define CSR_ATESTMODE_LSB 0 1658 #define CSR_ATESTMODE_MASK GENMASK_32(4, 0) 1659 #define CSR_ATESTPRBSEN_LSB 0 1660 #define CSR_ATESTPRBSEN_MASK BIT(0) 1661 #define CSR_ATESTCLKEN_LSB 1 1662 #define CSR_ATESTCLKEN_MASK BIT(1) 1663 #define CSR_ATESTMODESEL_LSB 2 1664 #define CSR_ATESTMODESEL_MASK GENMASK_32(4, 2) 1665 /* CSR_TXCALBINP */ 1666 #define CSR_TXCALBINP_LSB 0 1667 #define CSR_TXCALBINP_MASK GENMASK_32(4, 0) 1668 /* CSR_TXCALBINN */ 1669 #define CSR_TXCALBINN_LSB 0 1670 #define CSR_TXCALBINN_MASK GENMASK_32(4, 0) 1671 /* CSR_TXCALPOVR */ 1672 #define CSR_TXCALPOVR_LSB 0 1673 #define CSR_TXCALPOVR_MASK GENMASK_32(5, 0) 1674 #define CSR_TXCALBINPOVRVAL_LSB 0 1675 #define CSR_TXCALBINPOVRVAL_MASK GENMASK_32(4, 0) 1676 #define CSR_TXCALBINPOVREN_LSB 5 1677 #define CSR_TXCALBINPOVREN_MASK BIT(5) 1678 /* CSR_TXCALNOVR */ 1679 #define CSR_TXCALNOVR_LSB 0 1680 #define CSR_TXCALNOVR_MASK GENMASK_32(5, 0) 1681 #define CSR_TXCALBINNOVRVAL_LSB 0 1682 #define CSR_TXCALBINNOVRVAL_MASK GENMASK_32(4, 0) 1683 #define CSR_TXCALBINNOVREN_LSB 5 1684 #define CSR_TXCALBINNOVREN_MASK BIT(5) 1685 /* CSR_DFIMODE */ 1686 #define CSR_DFIMODE_LSB 0 1687 #define CSR_DFIMODE_MASK GENMASK_32(2, 0) 1688 #define CSR_DFI0ENABLE_LSB 0 1689 #define CSR_DFI0ENABLE_MASK BIT(0) 1690 #define CSR_DFI1ENABLE_LSB 1 1691 #define CSR_DFI1ENABLE_MASK BIT(1) 1692 #define CSR_DFI1OVERRIDE_LSB 2 1693 #define CSR_DFI1OVERRIDE_MASK BIT(2) 1694 /* CSR_TRISTATEMODECA */ 1695 #define CSR_TRISTATEMODECA_LSB 0 1696 #define CSR_TRISTATEMODECA_MASK GENMASK_32(3, 0) 1697 #define CSR_DISDYNADRTRI_LSB 0 1698 #define CSR_DISDYNADRTRI_MASK BIT(0) 1699 #define CSR_DDR2TMODE_LSB 1 1700 #define CSR_DDR2TMODE_MASK BIT(1) 1701 #define CSR_CKDISVAL_LSB 2 1702 #define CSR_CKDISVAL_MASK GENMASK_32(3, 2) 1703 /* MTESTMUXSEL already defined in ANIBx section */ 1704 /* CSR_MTESTPGMINFO */ 1705 #define CSR_MTESTPGMINFO_LSB 0 1706 #define CSR_MTESTPGMINFO_MASK BIT(0) 1707 /* CSR_DYNPWRDNUP */ 1708 #define CSR_DYNPWRDNUP_LSB 0 1709 #define CSR_DYNPWRDNUP_MASK BIT(0) 1710 #define CSR_DYNPOWERDOWN_LSB 0 1711 #define CSR_DYNPOWERDOWN_MASK BIT(0) 1712 /* CSR_PMIENABLE */ 1713 #define CSR_PMIENABLE_LSB 0 1714 #define CSR_PMIENABLE_MASK BIT(0) 1715 /* CSR_PHYTID */ 1716 #define CSR_PHYTID_LSB 0 1717 #define CSR_PHYTID_MASK GENMASK_32(15, 0) 1718 /* CSR_HWTMRL */ 1719 #define CSR_HWTMRL_LSB 0 1720 #define CSR_HWTMRL_MASK GENMASK_32(4, 0) 1721 /* CSR_DFIPHYUPD */ 1722 #define CSR_DFIPHYUPD_LSB 0 1723 #define CSR_DFIPHYUPD_MASK GENMASK_32(15, 0) 1724 #define CSR_DFIPHYUPDCNT_LSB 0 1725 #define CSR_DFIPHYUPDCNT_MASK GENMASK_32(3, 0) 1726 #define CSR_DFIPHYUPDRESP_LSB 4 1727 #define CSR_DFIPHYUPDRESP_MASK GENMASK_32(6, 4) 1728 #define CSR_DFIPHYUPDMODE_LSB 7 1729 #define CSR_DFIPHYUPDMODE_MASK BIT(7) 1730 #define CSR_DFIPHYUPDTHRESHOLD_LSB 8 1731 #define CSR_DFIPHYUPDTHRESHOLD_MASK GENMASK_32(11, 8) 1732 #define CSR_DFIPHYUPDINTTHRESHOLD_LSB 12 1733 #define CSR_DFIPHYUPDINTTHRESHOLD_MASK GENMASK_32(15, 12) 1734 /* CSR_PDAMRSWRITEMODE */ 1735 #define CSR_PDAMRSWRITEMODE_LSB 0 1736 #define CSR_PDAMRSWRITEMODE_MASK BIT(0) 1737 /* CSR_DFIGEARDOWNCTL */ 1738 #define CSR_DFIGEARDOWNCTL_LSB 0 1739 #define CSR_DFIGEARDOWNCTL_MASK GENMASK_32(1, 0) 1740 /* CSR_DQSPREAMBLECONTROL */ 1741 #define CSR_DQSPREAMBLECONTROL_LSB 0 1742 #define CSR_DQSPREAMBLECONTROL_MASK GENMASK_32(8, 0) 1743 #define CSR_TWOTCKRXDQSPRE_LSB 0 1744 #define CSR_TWOTCKRXDQSPRE_MASK BIT(0) 1745 #define CSR_TWOTCKTXDQSPRE_LSB 1 1746 #define CSR_TWOTCKTXDQSPRE_MASK BIT(1) 1747 #define CSR_POSITIONDFEINIT_LSB 2 1748 #define CSR_POSITIONDFEINIT_MASK GENMASK_32(4, 2) 1749 #define CSR_LP4TGLTWOTCKTXDQSPRE_LSB 5 1750 #define CSR_LP4TGLTWOTCKTXDQSPRE_MASK BIT(5) 1751 #define CSR_LP4POSTAMBLEEXT_LSB 6 1752 #define CSR_LP4POSTAMBLEEXT_MASK BIT(6) 1753 #define CSR_LP4STTCPREBRIDGERXEN_LSB 7 1754 #define CSR_LP4STTCPREBRIDGERXEN_MASK BIT(7) 1755 #define CSR_WDQSEXTENSION_LSB 8 1756 #define CSR_WDQSEXTENSION_MASK BIT(8) 1757 /* CSR_MASTERX4CONFIG */ 1758 #define CSR_MASTERX4CONFIG_LSB 0 1759 #define CSR_MASTERX4CONFIG_MASK GENMASK_32(3, 0) 1760 #define CSR_X4TG_LSB 0 1761 #define CSR_X4TG_MASK GENMASK_32(3, 0) 1762 /* CSR_WRLEVBITS */ 1763 #define CSR_WRLEVBITS_LSB 0 1764 #define CSR_WRLEVBITS_MASK GENMASK_32(7, 0) 1765 #define CSR_WRLEVFORDQSL_LSB 0 1766 #define CSR_WRLEVFORDQSL_MASK GENMASK_32(3, 0) 1767 #define CSR_WRLEVFORDQSU_LSB 4 1768 #define CSR_WRLEVFORDQSU_MASK GENMASK_32(7, 4) 1769 /* CSR_ENABLECSMULTICAST */ 1770 #define CSR_ENABLECSMULTICAST_LSB 0 1771 #define CSR_ENABLECSMULTICAST_MASK BIT(0) 1772 /* CSR_HWTLPCSMULTICAST */ 1773 #define CSR_HWTLPCSMULTICAST_LSB 0 1774 #define CSR_HWTLPCSMULTICAST_MASK BIT(0) 1775 /* CSR_ACX4ANIBDIS */ 1776 #define CSR_ACX4ANIBDIS_LSB 0 1777 #define CSR_ACX4ANIBDIS_MASK GENMASK_32(11, 0) 1778 /* CSR_DMIPINPRESENT */ 1779 #define CSR_DMIPINPRESENT_LSB 0 1780 #define CSR_DMIPINPRESENT_MASK BIT(0) 1781 #define CSR_RDDBIENABLED_LSB 0 1782 #define CSR_RDDBIENABLED_MASK BIT(0) 1783 /* CSR_ARDPTRINITVAL */ 1784 #define CSR_ARDPTRINITVAL_LSB 0 1785 #define CSR_ARDPTRINITVAL_MASK GENMASK_32(3, 0) 1786 /* CSR_DB0LCDLCALPHDETOUT */ 1787 #define CSR_DB0LCDLCALPHDETOUT_LSB 0 1788 #define CSR_DB0LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) 1789 /* CSR_DB1LCDLCALPHDETOUT */ 1790 #define CSR_DB1LCDLCALPHDETOUT_LSB 0 1791 #define CSR_DB1LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) 1792 /* CSR_DB2LCDLCALPHDETOUT */ 1793 #define CSR_DB2LCDLCALPHDETOUT_LSB 0 1794 #define CSR_DB2LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) 1795 /* CSR_DB3LCDLCALPHDETOUT */ 1796 #define CSR_DB3LCDLCALPHDETOUT_LSB 0 1797 #define CSR_DB3LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) 1798 /* CSR_DB4LCDLCALPHDETOUT */ 1799 #define CSR_DB4LCDLCALPHDETOUT_LSB 0 1800 #define CSR_DB4LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) 1801 /* CSR_DB5LCDLCALPHDETOUT */ 1802 #define CSR_DB5LCDLCALPHDETOUT_LSB 0 1803 #define CSR_DB5LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) 1804 /* CSR_DB6LCDLCALPHDETOUT */ 1805 #define CSR_DB6LCDLCALPHDETOUT_LSB 0 1806 #define CSR_DB6LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) 1807 /* CSR_DB7LCDLCALPHDETOUT */ 1808 #define CSR_DB7LCDLCALPHDETOUT_LSB 0 1809 #define CSR_DB7LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) 1810 /* CSR_DB8LCDLCALPHDETOUT */ 1811 #define CSR_DB8LCDLCALPHDETOUT_LSB 0 1812 #define CSR_DB8LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) 1813 /* CSR_DB9LCDLCALPHDETOUT */ 1814 #define CSR_DB9LCDLCALPHDETOUT_LSB 0 1815 #define CSR_DB9LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) 1816 /* CSR_DBYTEDLLMODECNTRL */ 1817 #define CSR_DBYTEDLLMODECNTRL_LSB 1 1818 #define CSR_DBYTEDLLMODECNTRL_MASK BIT(1) 1819 #define CSR_DLLRXPREAMBLEMODE_LSB 1 1820 #define CSR_DLLRXPREAMBLEMODE_MASK BIT(1) 1821 /* CSR_DBYTERXENTRAIN */ 1822 #define CSR_DBYTERXENTRAIN_LSB 0 1823 #define CSR_DBYTERXENTRAIN_MASK BIT(0) 1824 #define CSR_RXENTRAIN_LSB 0 1825 #define CSR_RXENTRAIN_MASK BIT(0) 1826 /* CSR_ANLCDLCALPHDETOUT */ 1827 #define CSR_ANLCDLCALPHDETOUT_LSB 0 1828 #define CSR_ANLCDLCALPHDETOUT_MASK GENMASK_32(11, 0) 1829 /* CSR_CALOFFSETS */ 1830 #define CSR_CALOFFSETS_LSB 0 1831 #define CSR_CALOFFSETS_MASK GENMASK_32(13, 0) 1832 #define CSR_CALCMPR5OFFSET_LSB 0 1833 #define CSR_CALCMPR5OFFSET_MASK GENMASK_32(5, 0) 1834 #define CSR_CALDRVPDTHOFFSET_LSB 6 1835 #define CSR_CALDRVPDTHOFFSET_MASK GENMASK_32(9, 6) 1836 #define CSR_CALDRVPUTHOFFSET_LSB 10 1837 #define CSR_CALDRVPUTHOFFSET_MASK GENMASK_32(13, 10) 1838 /* CSR_SARINITVALS */ 1839 #define CSR_SARINITVALS_LSB 0 1840 #define CSR_SARINITVALS_MASK GENMASK_32(8, 0) 1841 #define CSR_SARINITOFFSET05_LSB 0 1842 #define CSR_SARINITOFFSET05_MASK GENMASK_32(2, 0) 1843 #define CSR_SARINITNINT_LSB 3 1844 #define CSR_SARINITNINT_MASK GENMASK_32(5, 3) 1845 #define CSR_SARINITPEXT_LSB 6 1846 #define CSR_SARINITPEXT_MASK GENMASK_32(8, 6) 1847 /* CSR_CALPEXTOVR */ 1848 #define CSR_CALPEXTOVR_LSB 0 1849 #define CSR_CALPEXTOVR_MASK GENMASK_32(4, 0) 1850 /* CSR_CALCMPR5OVR */ 1851 #define CSR_CALCMPR5OVR_LSB 0 1852 #define CSR_CALCMPR5OVR_MASK GENMASK_32(7, 0) 1853 /* CSR_CALNINTOVR */ 1854 #define CSR_CALNINTOVR_LSB 0 1855 #define CSR_CALNINTOVR_MASK GENMASK_32(4, 0) 1856 /* CSR_CALDRVSTR0 */ 1857 #define CSR_CALDRVSTR0_LSB 0 1858 #define CSR_CALDRVSTR0_MASK GENMASK_32(7, 0) 1859 #define CSR_CALDRVSTRPD50_LSB 0 1860 #define CSR_CALDRVSTRPD50_MASK GENMASK_32(3, 0) 1861 #define CSR_CALDRVSTRPU50_LSB 4 1862 #define CSR_CALDRVSTRPU50_MASK GENMASK_32(7, 4) 1863 /* CSR_PROCODTCTL */ 1864 #define CSR_PROCODTCTL_LSB 0 1865 #define CSR_PROCODTCTL_MASK GENMASK_32(1, 0) 1866 #define CSR_PROCODTALWAYSOFF_LSB 0 1867 #define CSR_PROCODTALWAYSOFF_MASK BIT(0) 1868 #define CSR_PROCODTALWAYSON_LSB 1 1869 #define CSR_PROCODTALWAYSON_MASK BIT(1) 1870 /* CSR_PROCODTTIMECTL */ 1871 #define CSR_PROCODTTIMECTL_LSB 0 1872 #define CSR_PROCODTTIMECTL_MASK GENMASK_32(5, 0) 1873 #define CSR_PODTTAILWIDTH_LSB 0 1874 #define CSR_PODTTAILWIDTH_MASK GENMASK_32(1, 0) 1875 #define CSR_PODTSTARTDELAY_LSB 2 1876 #define CSR_PODTSTARTDELAY_MASK GENMASK_32(3, 2) 1877 #define CSR_PODTTAILWIDTHEXT_LSB 4 1878 #define CSR_PODTTAILWIDTHEXT_MASK GENMASK_32(5, 4) 1879 /* CSR_MEMALERTCONTROL */ 1880 #define CSR_MEMALERTCONTROL_LSB 0 1881 #define CSR_MEMALERTCONTROL_MASK GENMASK_32(15, 0) 1882 #define CSR_MALERTVREFLEVEL_LSB 0 1883 #define CSR_MALERTVREFLEVEL_MASK GENMASK_32(6, 0) 1884 #define CSR_MALERTVREFEXTEN_LSB 7 1885 #define CSR_MALERTVREFEXTEN_MASK BIT(7) 1886 #define CSR_MALERTPUSTREN_LSB 8 1887 #define CSR_MALERTPUSTREN_MASK GENMASK_32(11, 8) 1888 #define CSR_MALERTPUEN_LSB 12 1889 #define CSR_MALERTPUEN_MASK BIT(12) 1890 #define CSR_MALERTRXEN_LSB 13 1891 #define CSR_MALERTRXEN_MASK BIT(13) 1892 #define CSR_MALERTDISABLEVAL_LSB 14 1893 #define CSR_MALERTDISABLEVAL_MASK BIT(14) 1894 #define CSR_MALERTFORCEERROR_LSB 15 1895 #define CSR_MALERTFORCEERROR_MASK BIT(15) 1896 /* CSR_MEMALERTCONTROL2 */ 1897 #define CSR_MEMALERTCONTROL2_LSB 0 1898 #define CSR_MEMALERTCONTROL2_MASK BIT(0) 1899 #define CSR_MALERTSYNCBYPASS_LSB 0 1900 #define CSR_MALERTSYNCBYPASS_MASK BIT(0) 1901 /* CSR_MEMRESETL */ 1902 #define CSR_MEMRESETL_LSB 0 1903 #define CSR_MEMRESETL_MASK GENMASK_32(1, 0) 1904 #define CSR_MEMRESETLVALUE_LSB 0 1905 #define CSR_MEMRESETLVALUE_MASK BIT(0) 1906 #define CSR_PROTECTMEMRESET_LSB 1 1907 #define CSR_PROTECTMEMRESET_MASK BIT(1) 1908 /* CSR_PUBMODE */ 1909 #define CSR_PUBMODE_LSB 0 1910 #define CSR_PUBMODE_MASK BIT(0) 1911 #define CSR_HWTMEMSRC_LSB 0 1912 #define CSR_HWTMEMSRC_MASK BIT(0) 1913 /* CSR_MISCPHYSTATUS */ 1914 #define CSR_MISCPHYSTATUS_LSB 0 1915 #define CSR_MISCPHYSTATUS_MASK GENMASK_32(1, 0) 1916 #define CSR_DCTSANE_LSB 0 1917 #define CSR_DCTSANE_MASK BIT(0) 1918 #define CSR_PORMEMRESET_LSB 1 1919 #define CSR_PORMEMRESET_MASK BIT(1) 1920 /* CSR_CORELOOPBACKSEL */ 1921 #define CSR_CORELOOPBACKSEL_LSB 0 1922 #define CSR_CORELOOPBACKSEL_MASK BIT(0) 1923 /* CSR_DLLTRAINPARAM */ 1924 #define CSR_DLLTRAINPARAM_LSB 0 1925 #define CSR_DLLTRAINPARAM_MASK GENMASK_32(1, 0) 1926 #define CSR_EXTENDPHDTIME_LSB 0 1927 #define CSR_EXTENDPHDTIME_MASK GENMASK_32(1, 0) 1928 /* CSR_HWTLPCSENA */ 1929 #define CSR_HWTLPCSENA_LSB 0 1930 #define CSR_HWTLPCSENA_MASK GENMASK_32(1, 0) 1931 /* CSR_HWTLPCSENB */ 1932 #define CSR_HWTLPCSENB_LSB 0 1933 #define CSR_HWTLPCSENB_MASK GENMASK_32(1, 0) 1934 /* CSR_HWTLPCSENBYPASS */ 1935 #define CSR_HWTLPCSENBYPASS_LSB 0 1936 #define CSR_HWTLPCSENBYPASS_MASK BIT(0) 1937 /* CSR_DFICAMODE */ 1938 #define CSR_DFICAMODE_LSB 0 1939 #define CSR_DFICAMODE_MASK GENMASK_32(3, 0) 1940 #define CSR_DFILP3CAMODE_LSB 0 1941 #define CSR_DFILP3CAMODE_MASK BIT(0) 1942 #define CSR_DFID4CAMODE_LSB 1 1943 #define CSR_DFID4CAMODE_MASK BIT(1) 1944 #define CSR_DFILP4CAMODE_LSB 2 1945 #define CSR_DFILP4CAMODE_MASK BIT(2) 1946 #define CSR_DFID4ALTCAMODE_LSB 3 1947 #define CSR_DFID4ALTCAMODE_MASK BIT(3) 1948 /* CSR_HWTCACTL */ 1949 #define CSR_HWTCACTL_LSB 0 1950 #define CSR_HWTCACTL_MASK BIT(0) 1951 #define CSR_HWTDISDYNADRTRI_LSB 0 1952 #define CSR_HWTDISDYNADRTRI_MASK BIT(0) 1953 /* CSR_HWTCAMODE */ 1954 #define CSR_HWTCAMODE_LSB 0 1955 #define CSR_HWTCAMODE_MASK GENMASK_32(5, 0) 1956 #define CSR_HWTLP3CAMODE_LSB 0 1957 #define CSR_HWTLP3CAMODE_MASK BIT(0) 1958 #define CSR_HWTD4CAMODE_LSB 1 1959 #define CSR_HWTD4CAMODE_MASK BIT(1) 1960 #define CSR_HWTLP4CAMODE_LSB 2 1961 #define CSR_HWTLP4CAMODE_MASK BIT(2) 1962 #define CSR_HWTD4ALTCAMODE_LSB 3 1963 #define CSR_HWTD4ALTCAMODE_MASK BIT(3) 1964 #define CSR_HWTCSINVERT_LSB 4 1965 #define CSR_HWTCSINVERT_MASK BIT(4) 1966 #define CSR_HWTDBIINVERT_LSB 5 1967 #define CSR_HWTDBIINVERT_MASK BIT(5) 1968 /* CSR_DLLCONTROL */ 1969 #define CSR_DLLCONTROL_LSB 0 1970 #define CSR_DLLCONTROL_MASK GENMASK_32(2, 0) 1971 #define CSR_DLLRESETRELOCK_LSB 0 1972 #define CSR_DLLRESETRELOCK_MASK BIT(0) 1973 #define CSR_DLLRESETSLAVE_LSB 1 1974 #define CSR_DLLRESETSLAVE_MASK BIT(1) 1975 #define CSR_DLLRESETRSVD_LSB 2 1976 #define CSR_DLLRESETRSVD_MASK BIT(2) 1977 /* CSR_PULSEDLLUPDATEPHASE */ 1978 #define CSR_PULSEDLLUPDATEPHASE_LSB 0 1979 #define CSR_PULSEDLLUPDATEPHASE_MASK GENMASK_32(7, 0) 1980 #define CSR_PULSEDBYTEDLLUPDATEPHASE_LSB 0 1981 #define CSR_PULSEDBYTEDLLUPDATEPHASE_MASK BIT(0) 1982 #define CSR_PULSEACKDLLUPDATEPHASE_LSB 1 1983 #define CSR_PULSEACKDLLUPDATEPHASE_MASK BIT(1) 1984 #define CSR_PULSEACADLLUPDATEPHASE_LSB 2 1985 #define CSR_PULSEACADLLUPDATEPHASE_MASK BIT(2) 1986 #define CSR_UPDATEPHASEDESTRESERVED_LSB 3 1987 #define CSR_UPDATEPHASEDESTRESERVED_MASK GENMASK_32(5, 3) 1988 #define CSR_TRAINUPDATEPHASEONLONGBUBBLE_LSB 6 1989 #define CSR_TRAINUPDATEPHASEONLONGBUBBLE_MASK BIT(6) 1990 #define CSR_ALWAYSUPDATELCDLPHASE_LSB 7 1991 #define CSR_ALWAYSUPDATELCDLPHASE_MASK BIT(7) 1992 /* CSR_HWTCONTROLOVR0 */ 1993 #define CSR_HWTCONTROLOVR0_LSB 0 1994 #define CSR_HWTCONTROLOVR0_MASK GENMASK_32(12, 0) 1995 #define CSR_HWTCS0OVR0_LSB 0 1996 #define CSR_HWTCS0OVR0_MASK BIT(0) 1997 #define CSR_HWTCS1OVR0_LSB 1 1998 #define CSR_HWTCS1OVR0_MASK BIT(1) 1999 #define CSR_HWTCS2OVR0_LSB 2 2000 #define CSR_HWTCS2OVR0_MASK BIT(2) 2001 #define CSR_HWTCS3OVR0_LSB 3 2002 #define CSR_HWTCS3OVR0_MASK BIT(3) 2003 #define CSR_HWTCKE0OVR0_LSB 4 2004 #define CSR_HWTCKE0OVR0_MASK BIT(4) 2005 #define CSR_HWTCKE1OVR0_LSB 5 2006 #define CSR_HWTCKE1OVR0_MASK BIT(5) 2007 #define CSR_HWTCKE2OVR0_LSB 6 2008 #define CSR_HWTCKE2OVR0_MASK BIT(6) 2009 #define CSR_HWTCKE3OVR0_LSB 7 2010 #define CSR_HWTCKE3OVR0_MASK BIT(7) 2011 #define CSR_HWTODT0OVR0_LSB 8 2012 #define CSR_HWTODT0OVR0_MASK BIT(8) 2013 #define CSR_HWTODT1OVR0_LSB 9 2014 #define CSR_HWTODT1OVR0_MASK BIT(9) 2015 #define CSR_HWTODT2OVR0_LSB 10 2016 #define CSR_HWTODT2OVR0_MASK BIT(10) 2017 #define CSR_HWTODT3OVR0_LSB 11 2018 #define CSR_HWTODT3OVR0_MASK BIT(11) 2019 #define CSR_HWTPARITYOVR0_LSB 12 2020 #define CSR_HWTPARITYOVR0_MASK BIT(12) 2021 /* CSR_HWTCONTROLOVR1 */ 2022 #define CSR_HWTCONTROLOVR1_LSB 0 2023 #define CSR_HWTCONTROLOVR1_MASK GENMASK_32(12, 0) 2024 #define CSR_HWTCS0OVR1_LSB 0 2025 #define CSR_HWTCS0OVR1_MASK BIT(0) 2026 #define CSR_HWTCS1OVR1_LSB 1 2027 #define CSR_HWTCS1OVR1_MASK BIT(1) 2028 #define CSR_HWTCS2OVR1_LSB 2 2029 #define CSR_HWTCS2OVR1_MASK BIT(2) 2030 #define CSR_HWTCS3OVR1_LSB 3 2031 #define CSR_HWTCS3OVR1_MASK BIT(3) 2032 #define CSR_HWTCKE0OVR1_LSB 4 2033 #define CSR_HWTCKE0OVR1_MASK BIT(4) 2034 #define CSR_HWTCKE1OVR1_LSB 5 2035 #define CSR_HWTCKE1OVR1_MASK BIT(5) 2036 #define CSR_HWTCKE2OVR1_LSB 6 2037 #define CSR_HWTCKE2OVR1_MASK BIT(6) 2038 #define CSR_HWTCKE3OVR1_LSB 7 2039 #define CSR_HWTCKE3OVR1_MASK BIT(7) 2040 #define CSR_HWTODT0OVR1_LSB 8 2041 #define CSR_HWTODT0OVR1_MASK BIT(8) 2042 #define CSR_HWTODT1OVR1_LSB 9 2043 #define CSR_HWTODT1OVR1_MASK BIT(9) 2044 #define CSR_HWTODT2OVR1_LSB 10 2045 #define CSR_HWTODT2OVR1_MASK BIT(10) 2046 #define CSR_HWTODT3OVR1_LSB 11 2047 #define CSR_HWTODT3OVR1_MASK BIT(11) 2048 #define CSR_HWTPARITYOVR1_LSB 12 2049 #define CSR_HWTPARITYOVR1_MASK BIT(12) 2050 /* CSR_DLLGAINCTL */ 2051 #define CSR_DLLGAINCTL_LSB 0 2052 #define CSR_DLLGAINCTL_MASK GENMASK_32(11, 0) 2053 #define CSR_DLLGAINIV_LSB 0 2054 #define CSR_DLLGAINIV_MASK GENMASK_32(3, 0) 2055 #define CSR_DLLGAINTV_LSB 4 2056 #define CSR_DLLGAINTV_MASK GENMASK_32(7, 4) 2057 #define CSR_DLLSEEDSEL_LSB 8 2058 #define CSR_DLLSEEDSEL_MASK GENMASK_32(11, 8) 2059 /* CSR_DLLLOCKPARAM */ 2060 #define CSR_DLLLOCKPARAM_LSB 0 2061 #define CSR_DLLLOCKPARAM_MASK GENMASK_32(12, 0) 2062 #define CSR_DISDLLSEEDSEL_LSB 0 2063 #define CSR_DISDLLSEEDSEL_MASK BIT(0) 2064 #define CSR_DISDLLGAINIVSEED_LSB 1 2065 #define CSR_DISDLLGAINIVSEED_MASK BIT(1) 2066 #define CSR_DLLLOCKPARAMSPARE_LSB 2 2067 #define CSR_DLLLOCKPARAMSPARE_MASK GENMASK_32(3, 2) 2068 #define CSR_LCDLSEED0_LSB 4 2069 #define CSR_LCDLSEED0_MASK GENMASK_32(12, 4) 2070 /* CSR_HWTCONTROLVAL0 */ 2071 #define CSR_HWTCONTROLVAL0_LSB 0 2072 #define CSR_HWTCONTROLVAL0_MASK GENMASK_32(12, 0) 2073 #define CSR_HWTCS0VAL0_LSB 0 2074 #define CSR_HWTCS0VAL0_MASK BIT(0) 2075 #define CSR_HWTCS1VAL0_LSB 1 2076 #define CSR_HWTCS1VAL0_MASK BIT(1) 2077 #define CSR_HWTCS2VAL0_LSB 2 2078 #define CSR_HWTCS2VAL0_MASK BIT(2) 2079 #define CSR_HWTCS3VAL0_LSB 3 2080 #define CSR_HWTCS3VAL0_MASK BIT(3) 2081 #define CSR_HWTCKE0VAL0_LSB 4 2082 #define CSR_HWTCKE0VAL0_MASK BIT(4) 2083 #define CSR_HWTCKE1VAL0_LSB 5 2084 #define CSR_HWTCKE1VAL0_MASK BIT(5) 2085 #define CSR_HWTCKE2VAL0_LSB 6 2086 #define CSR_HWTCKE2VAL0_MASK BIT(6) 2087 #define CSR_HWTCKE3VAL0_LSB 7 2088 #define CSR_HWTCKE3VAL0_MASK BIT(7) 2089 #define CSR_HWTODT0VAL0_LSB 8 2090 #define CSR_HWTODT0VAL0_MASK BIT(8) 2091 #define CSR_HWTODT1VAL0_LSB 9 2092 #define CSR_HWTODT1VAL0_MASK BIT(9) 2093 #define CSR_HWTODT2VAL0_LSB 10 2094 #define CSR_HWTODT2VAL0_MASK BIT(10) 2095 #define CSR_HWTODT3VAL0_LSB 11 2096 #define CSR_HWTODT3VAL0_MASK BIT(11) 2097 #define CSR_HWTPARITYVAL0_LSB 12 2098 #define CSR_HWTPARITYVAL0_MASK BIT(12) 2099 /* CSR_HWTCONTROLVAL1 */ 2100 #define CSR_HWTCONTROLVAL1_LSB 0 2101 #define CSR_HWTCONTROLVAL1_MASK GENMASK_32(12, 0) 2102 #define CSR_HWTCS0VAL1_LSB 0 2103 #define CSR_HWTCS0VAL1_MASK BIT(0) 2104 #define CSR_HWTCS1VAL1_LSB 1 2105 #define CSR_HWTCS1VAL1_MASK BIT(1) 2106 #define CSR_HWTCS2VAL1_LSB 2 2107 #define CSR_HWTCS2VAL1_MASK BIT(2) 2108 #define CSR_HWTCS3VAL1_LSB 3 2109 #define CSR_HWTCS3VAL1_MASK BIT(3) 2110 #define CSR_HWTCKE0VAL1_LSB 4 2111 #define CSR_HWTCKE0VAL1_MASK BIT(4) 2112 #define CSR_HWTCKE1VAL1_LSB 5 2113 #define CSR_HWTCKE1VAL1_MASK BIT(5) 2114 #define CSR_HWTCKE2VAL1_LSB 6 2115 #define CSR_HWTCKE2VAL1_MASK BIT(6) 2116 #define CSR_HWTCKE3VAL1_LSB 7 2117 #define CSR_HWTCKE3VAL1_MASK BIT(7) 2118 #define CSR_HWTODT0VAL1_LSB 8 2119 #define CSR_HWTODT0VAL1_MASK BIT(8) 2120 #define CSR_HWTODT1VAL1_LSB 9 2121 #define CSR_HWTODT1VAL1_MASK BIT(9) 2122 #define CSR_HWTODT2VAL1_LSB 10 2123 #define CSR_HWTODT2VAL1_MASK BIT(10) 2124 #define CSR_HWTODT3VAL1_LSB 11 2125 #define CSR_HWTODT3VAL1_MASK BIT(11) 2126 #define CSR_HWTPARITYVAL1_LSB 12 2127 #define CSR_HWTPARITYVAL1_MASK BIT(12) 2128 /* CSR_ACSMGLBLSTART */ 2129 #define CSR_ACSMGLBLSTART_LSB 0 2130 #define CSR_ACSMGLBLSTART_MASK BIT(0) 2131 /* CSR_ACSMGLBLSGLSTPCTRL */ 2132 #define CSR_ACSMGLBLSGLSTPCTRL_LSB 0 2133 #define CSR_ACSMGLBLSGLSTPCTRL_MASK GENMASK_32(1, 0) 2134 #define CSR_ACSMSGLSTPMODE_LSB 0 2135 #define CSR_ACSMSGLSTPMODE_MASK BIT(0) 2136 #define CSR_ACSMSGLSTP_LSB 1 2137 #define CSR_ACSMSGLSTP_MASK BIT(1) 2138 /* CSR_LCDLCALPHASE */ 2139 #define CSR_LCDLCALPHASE_LSB 0 2140 #define CSR_LCDLCALPHASE_MASK GENMASK_32(8, 0) 2141 /* CSR_LCDLCALCTRL */ 2142 #define CSR_LCDLCALCTRL_LSB 0 2143 #define CSR_LCDLCALCTRL_MASK GENMASK_32(6, 0) 2144 #define CSR_LCDLCALMODE_LSB 0 2145 #define CSR_LCDLCALMODE_MASK BIT(0) 2146 #define CSR_LCDLCALSLOWCLKSEL_LSB 1 2147 #define CSR_LCDLCALSLOWCLKSEL_MASK BIT(1) 2148 #define CSR_LCDLCALEN_LSB 2 2149 #define CSR_LCDLCALEN_MASK BIT(2) 2150 #define CSR_LCDLCALPHASEUPDATE_LSB 3 2151 #define CSR_LCDLCALPHASEUPDATE_MASK BIT(3) 2152 #define CSR_LCDLCALCLKEN_LSB 4 2153 #define CSR_LCDLCALCLKEN_MASK BIT(4) 2154 #define CSR_LCDLCALSAMPEN_LSB 5 2155 #define CSR_LCDLCALSAMPEN_MASK BIT(5) 2156 #define CSR_LCDLCALSLOWCLKEN_LSB 6 2157 #define CSR_LCDLCALSLOWCLKEN_MASK BIT(6) 2158 /* CSR_CALRATE */ 2159 #define CSR_CALRATE_LSB 0 2160 #define CSR_CALRATE_MASK GENMASK_32(6, 0) 2161 #define CSR_CALINTERVAL_LSB 0 2162 #define CSR_CALINTERVAL_MASK GENMASK_32(3, 0) 2163 #define CSR_CALRUN_LSB 4 2164 #define CSR_CALRUN_MASK BIT(4) 2165 #define CSR_CALONCE_LSB 5 2166 #define CSR_CALONCE_MASK BIT(5) 2167 #define CSR_DISABLEBACKGROUNDZQUPDATES_LSB 6 2168 #define CSR_DISABLEBACKGROUNDZQUPDATES_MASK BIT(6) 2169 /* CSR_CALZAP */ 2170 #define CSR_CALZAP_LSB 0 2171 #define CSR_CALZAP_MASK BIT(0) 2172 /* CSR_PSTATE */ 2173 #define CSR_PSTATE_LSB 0 2174 #define CSR_PSTATE_MASK GENMASK_32(3, 0) 2175 /* CSR_CALPREDRIVEROVERRIDE */ 2176 #define CSR_CALPREDRIVEROVERRIDE_LSB 0 2177 #define CSR_CALPREDRIVEROVERRIDE_MASK GENMASK_32(7, 0) 2178 #define CSR_TXPREOVN_LSB 0 2179 #define CSR_TXPREOVN_MASK GENMASK_32(3, 0) 2180 #define CSR_TXPREOVP_LSB 4 2181 #define CSR_TXPREOVP_MASK GENMASK_32(7, 4) 2182 /* CSR_PLLOUTGATECONTROL */ 2183 #define CSR_PLLOUTGATECONTROL_LSB 0 2184 #define CSR_PLLOUTGATECONTROL_MASK GENMASK_32(1, 0) 2185 #define CSR_PCLKGATEEN_LSB 0 2186 #define CSR_PCLKGATEEN_MASK BIT(0) 2187 #define CSR_RESERVED2X1_LSB 1 2188 #define CSR_RESERVED2X1_MASK BIT(1) 2189 /* CSR_UCMEMRESETCONTROL */ 2190 #define CSR_UCMEMRESETCONTROL_LSB 0 2191 #define CSR_UCMEMRESETCONTROL_MASK BIT(0) 2192 #define CSR_UCDCTSANE_LSB 0 2193 #define CSR_UCDCTSANE_MASK BIT(0) 2194 /* CSR_PORCONTROL */ 2195 #define CSR_PORCONTROL_LSB 0 2196 #define CSR_PORCONTROL_MASK BIT(0) 2197 #define CSR_PLLDLLLOCKDONE_LSB 0 2198 #define CSR_PLLDLLLOCKDONE_MASK BIT(0) 2199 /* CSR_CALBUSY */ 2200 #define CSR_CALBUSY_LSB 0 2201 #define CSR_CALBUSY_MASK BIT(0) 2202 /* CSR_CALMISC2 */ 2203 #define CSR_CALMISC2_LSB 0 2204 #define CSR_CALMISC2_MASK GENMASK_32(15, 0) 2205 #define CSR_CALNUMVOTES_LSB 0 2206 #define CSR_CALNUMVOTES_MASK GENMASK_32(2, 0) 2207 #define CSR_RESERVED10X3_LSB 3 2208 #define CSR_RESERVED10X3_MASK GENMASK_32(10, 3) 2209 #define CSR_RESERVED11_LSB 11 2210 #define CSR_RESERVED11_MASK BIT(11) 2211 #define CSR_CALCMPTRRESTRIM_LSB 12 2212 #define CSR_CALCMPTRRESTRIM_MASK BIT(12) 2213 #define CSR_CALCANCELROUNDERRDIS_LSB 13 2214 #define CSR_CALCANCELROUNDERRDIS_MASK BIT(13) 2215 #define CSR_CALSLOWCMPANA_LSB 14 2216 #define CSR_CALSLOWCMPANA_MASK BIT(14) 2217 #define CSR_RESERVED15_LSB 15 2218 #define CSR_RESERVED15_MASK BIT(15) 2219 /* CSR_CALMISC */ 2220 #define CSR_CALMISC_LSB 0 2221 #define CSR_CALMISC_MASK GENMASK_32(2, 0) 2222 #define CSR_CALCMPR5DIS_LSB 0 2223 #define CSR_CALCMPR5DIS_MASK BIT(0) 2224 #define CSR_CALNINTDIS_LSB 1 2225 #define CSR_CALNINTDIS_MASK BIT(1) 2226 #define CSR_CALPEXTDIS_LSB 2 2227 #define CSR_CALPEXTDIS_MASK BIT(2) 2228 /* CSR_CALVREFS */ 2229 #define CSR_CALVREFS_LSB 0 2230 #define CSR_CALVREFS_MASK GENMASK_32(1, 0) 2231 /* CSR_CALCMPR5 */ 2232 #define CSR_CALCMPR5_LSB 0 2233 #define CSR_CALCMPR5_MASK GENMASK_32(7, 0) 2234 /* CSR_CALNINT */ 2235 #define CSR_CALNINT_LSB 0 2236 #define CSR_CALNINT_MASK GENMASK_32(4, 0) 2237 #define CSR_CALNINTTHB_LSB 0 2238 #define CSR_CALNINTTHB_MASK GENMASK_32(4, 0) 2239 /* CSR_CALPEXT */ 2240 #define CSR_CALPEXT_LSB 0 2241 #define CSR_CALPEXT_MASK GENMASK_32(4, 0) 2242 #define CSR_CALPEXTTHB_LSB 0 2243 #define CSR_CALPEXTTHB_MASK GENMASK_32(4, 0) 2244 /* CSR_CALCMPINVERT */ 2245 #define CSR_CALCMPINVERT_LSB 0 2246 #define CSR_CALCMPINVERT_MASK GENMASK_32(4, 0) 2247 #define CSR_CMPINVERTCALDAC50_LSB 0 2248 #define CSR_CMPINVERTCALDAC50_MASK BIT(0) 2249 #define CSR_CMPINVERTCALDRVPD50_LSB 1 2250 #define CSR_CMPINVERTCALDRVPD50_MASK BIT(1) 2251 #define CSR_CMPINVERTCALDRVPU50_LSB 2 2252 #define CSR_CMPINVERTCALDRVPU50_MASK BIT(2) 2253 #define CSR_CMPINVERTCALODTPD_LSB 3 2254 #define CSR_CMPINVERTCALODTPD_MASK BIT(3) 2255 #define CSR_CMPINVERTCALODTPU_LSB 4 2256 #define CSR_CMPINVERTCALODTPU_MASK BIT(4) 2257 /* CSR_CALCMPANACNTRL */ 2258 #define CSR_CALCMPANACNTRL_LSB 0 2259 #define CSR_CALCMPANACNTRL_MASK GENMASK_32(9, 0) 2260 #define CSR_CMPRGAINCURRADJ_LSB 0 2261 #define CSR_CMPRGAINCURRADJ_MASK GENMASK_32(7, 0) 2262 #define CSR_CMPRGAINRESADJ_LSB 8 2263 #define CSR_CMPRGAINRESADJ_MASK BIT(8) 2264 #define CSR_CMPRBIASBYPASSEN_LSB 9 2265 #define CSR_CMPRBIASBYPASSEN_MASK BIT(9) 2266 /* CSR_DFIRDDATACSDESTMAP */ 2267 #define CSR_DFIRDDATACSDESTMAP_LSB 0 2268 #define CSR_DFIRDDATACSDESTMAP_MASK GENMASK_32(7, 0) 2269 #define CSR_DFIRDDESTM0_LSB 0 2270 #define CSR_DFIRDDESTM0_MASK GENMASK_32(1, 0) 2271 #define CSR_DFIRDDESTM1_LSB 2 2272 #define CSR_DFIRDDESTM1_MASK GENMASK_32(3, 2) 2273 #define CSR_DFIRDDESTM2_LSB 4 2274 #define CSR_DFIRDDESTM2_MASK GENMASK_32(5, 4) 2275 #define CSR_DFIRDDESTM3_LSB 6 2276 #define CSR_DFIRDDESTM3_MASK GENMASK_32(7, 6) 2277 /* CSR_VREFINGLOBAL */ 2278 #define CSR_VREFINGLOBAL_LSB 0 2279 #define CSR_VREFINGLOBAL_MASK GENMASK_32(14, 0) 2280 #define CSR_GLOBALVREFINSEL_LSB 0 2281 #define CSR_GLOBALVREFINSEL_MASK GENMASK_32(2, 0) 2282 #define CSR_GLOBALVREFINDAC_LSB 3 2283 #define CSR_GLOBALVREFINDAC_MASK GENMASK_32(9, 3) 2284 #define CSR_GLOBALVREFINTRIM_LSB 10 2285 #define CSR_GLOBALVREFINTRIM_MASK GENMASK_32(13, 10) 2286 #define CSR_GLOBALVREFINMODE_LSB 14 2287 #define CSR_GLOBALVREFINMODE_MASK BIT(14) 2288 /* CSR_DFIWRDATACSDESTMAP */ 2289 #define CSR_DFIWRDATACSDESTMAP_LSB 0 2290 #define CSR_DFIWRDATACSDESTMAP_MASK GENMASK_32(7, 0) 2291 #define CSR_DFIWRDESTM0_LSB 0 2292 #define CSR_DFIWRDESTM0_MASK GENMASK_32(1, 0) 2293 #define CSR_DFIWRDESTM1_LSB 2 2294 #define CSR_DFIWRDESTM1_MASK GENMASK_32(3, 2) 2295 #define CSR_DFIWRDESTM2_LSB 4 2296 #define CSR_DFIWRDESTM2_MASK GENMASK_32(5, 4) 2297 #define CSR_DFIWRDESTM3_LSB 6 2298 #define CSR_DFIWRDESTM3_MASK GENMASK_32(7, 6) 2299 /* CSR_MASUPDGOODCTR */ 2300 #define CSR_MASUPDGOODCTR_LSB 0 2301 #define CSR_MASUPDGOODCTR_MASK GENMASK_32(15, 0) 2302 /* CSR_PHYUPD0GOODCTR */ 2303 #define CSR_PHYUPD0GOODCTR_LSB 0 2304 #define CSR_PHYUPD0GOODCTR_MASK GENMASK_32(15, 0) 2305 /* CSR_PHYUPD1GOODCTR */ 2306 #define CSR_PHYUPD1GOODCTR_LSB 0 2307 #define CSR_PHYUPD1GOODCTR_MASK GENMASK_32(15, 0) 2308 /* CSR_CTLUPD0GOODCTR */ 2309 #define CSR_CTLUPD0GOODCTR_LSB 0 2310 #define CSR_CTLUPD0GOODCTR_MASK GENMASK_32(15, 0) 2311 /* CSR_CTLUPD1GOODCTR */ 2312 #define CSR_CTLUPD1GOODCTR_LSB 0 2313 #define CSR_CTLUPD1GOODCTR_MASK GENMASK_32(15, 0) 2314 /* CSR_MASUPDFAILCTR */ 2315 #define CSR_MASUPDFAILCTR_LSB 0 2316 #define CSR_MASUPDFAILCTR_MASK GENMASK_32(15, 0) 2317 /* CSR_PHYUPD0FAILCTR */ 2318 #define CSR_PHYUPD0FAILCTR_LSB 0 2319 #define CSR_PHYUPD0FAILCTR_MASK GENMASK_32(15, 0) 2320 /* CSR_PHYUPD1FAILCTR */ 2321 #define CSR_PHYUPD1FAILCTR_LSB 0 2322 #define CSR_PHYUPD1FAILCTR_MASK GENMASK_32(15, 0) 2323 /* CSR_PHYPERFCTRENABLE */ 2324 #define CSR_PHYPERFCTRENABLE_LSB 0 2325 #define CSR_PHYPERFCTRENABLE_MASK GENMASK_32(7, 0) 2326 #define CSR_MASUPDGOODCTL_LSB 0 2327 #define CSR_MASUPDGOODCTL_MASK BIT(0) 2328 #define CSR_PHYUPD0GOODCTL_LSB 1 2329 #define CSR_PHYUPD0GOODCTL_MASK BIT(1) 2330 #define CSR_PHYUPD1GOODCTL_LSB 2 2331 #define CSR_PHYUPD1GOODCTL_MASK BIT(2) 2332 #define CSR_CTLUPD0GOODCTL_LSB 3 2333 #define CSR_CTLUPD0GOODCTL_MASK BIT(3) 2334 #define CSR_CTLUPD1GOODCTL_LSB 4 2335 #define CSR_CTLUPD1GOODCTL_MASK BIT(4) 2336 #define CSR_MASUPDFAILCTL_LSB 5 2337 #define CSR_MASUPDFAILCTL_MASK BIT(5) 2338 #define CSR_PHYUPD0FAILCTL_LSB 6 2339 #define CSR_PHYUPD0FAILCTL_MASK BIT(6) 2340 #define CSR_PHYUPD1FAILCTL_LSB 7 2341 #define CSR_PHYUPD1FAILCTL_MASK BIT(7) 2342 /* CSR_DFIWRRDDATACSCONFIG */ 2343 #define CSR_DFIWRRDDATACSCONFIG_LSB 0 2344 #define CSR_DFIWRRDDATACSCONFIG_MASK GENMASK_32(1, 0) 2345 #define CSR_DFIWRDATACSPOLARITY_LSB 0 2346 #define CSR_DFIWRDATACSPOLARITY_MASK BIT(0) 2347 #define CSR_DFIRDDATACSPOLARITY_LSB 1 2348 #define CSR_DFIRDDATACSPOLARITY_MASK BIT(1) 2349 /* CSR_PLLPWRDN */ 2350 #define CSR_PLLPWRDN_LSB 0 2351 #define CSR_PLLPWRDN_MASK BIT(0) 2352 /* CSR_PLLRESET */ 2353 #define CSR_PLLRESET_LSB 0 2354 #define CSR_PLLRESET_MASK BIT(0) 2355 /* CSR_PLLCTRL2 */ 2356 #define CSR_PLLCTRL2_LSB 0 2357 #define CSR_PLLCTRL2_MASK GENMASK_32(4, 0) 2358 #define CSR_PLLFREQSEL_LSB 0 2359 #define CSR_PLLFREQSEL_MASK GENMASK_32(4, 0) 2360 /* CSR_PLLCTRL0 */ 2361 #define CSR_PLLCTRL0_LSB 0 2362 #define CSR_PLLCTRL0_MASK GENMASK_32(15, 0) 2363 #define CSR_PLLSTANDBY_LSB 0 2364 #define CSR_PLLSTANDBY_MASK BIT(0) 2365 #define CSR_PLLBYPSEL_LSB 1 2366 #define CSR_PLLBYPSEL_MASK BIT(1) 2367 #define CSR_PLLX2MODE_LSB 2 2368 #define CSR_PLLX2MODE_MASK BIT(2) 2369 #define CSR_PLLOUTBYPEN_LSB 3 2370 #define CSR_PLLOUTBYPEN_MASK BIT(3) 2371 #define CSR_PLLPRESET_LSB 4 2372 #define CSR_PLLPRESET_MASK BIT(4) 2373 #define CSR_PLLBYPASSMODE_LSB 5 2374 #define CSR_PLLBYPASSMODE_MASK BIT(5) 2375 #define CSR_PLLSELDFIFREQRATIO_LSB 6 2376 #define CSR_PLLSELDFIFREQRATIO_MASK BIT(6) 2377 #define CSR_PLLSYNCBUSFLUSH_LSB 7 2378 #define CSR_PLLSYNCBUSFLUSH_MASK BIT(7) 2379 #define CSR_PLLSYNCBUSBYP_LSB 8 2380 #define CSR_PLLSYNCBUSBYP_MASK BIT(8) 2381 #define CSR_PLLRESERVED10X9_LSB 9 2382 #define CSR_PLLRESERVED10X9_MASK GENMASK_32(10, 9) 2383 #define CSR_PLLGEARSHIFT_LSB 11 2384 #define CSR_PLLGEARSHIFT_MASK BIT(11) 2385 #define CSR_PLLLOCKCNTSEL_LSB 12 2386 #define CSR_PLLLOCKCNTSEL_MASK BIT(12) 2387 #define CSR_PLLLOCKPHSEL_LSB 13 2388 #define CSR_PLLLOCKPHSEL_MASK GENMASK_32(14, 13) 2389 #define CSR_PLLSPARECTRL0_LSB 15 2390 #define CSR_PLLSPARECTRL0_MASK BIT(15) 2391 /* CSR_PLLCTRL1 */ 2392 #define CSR_PLLCTRL1_LSB 0 2393 #define CSR_PLLCTRL1_MASK GENMASK_32(8, 0) 2394 #define CSR_PLLCPINTCTRL_LSB 0 2395 #define CSR_PLLCPINTCTRL_MASK GENMASK_32(4, 0) 2396 #define CSR_PLLCPPROPCTRL_LSB 5 2397 #define CSR_PLLCPPROPCTRL_MASK GENMASK_32(8, 5) 2398 /* CSR_PLLTST */ 2399 #define CSR_PLLTST_LSB 0 2400 #define CSR_PLLTST_MASK GENMASK_32(8, 0) 2401 #define CSR_PLLANATSTEN_LSB 0 2402 #define CSR_PLLANATSTEN_MASK BIT(0) 2403 #define CSR_PLLANATSTSEL_LSB 1 2404 #define CSR_PLLANATSTSEL_MASK GENMASK_32(4, 1) 2405 #define CSR_PLLDIGTSTSEL_LSB 5 2406 #define CSR_PLLDIGTSTSEL_MASK GENMASK_32(8, 5) 2407 /* CSR_PLLLOCKSTATUS */ 2408 #define CSR_PLLLOCKSTATUS_LSB 0 2409 #define CSR_PLLLOCKSTATUS_MASK BIT(0) 2410 /* CSR_PLLTESTMODE */ 2411 #define CSR_PLLTESTMODE_LSB 0 2412 #define CSR_PLLTESTMODE_MASK GENMASK_32(15, 0) 2413 /* CSR_PLLCTRL3 */ 2414 #define CSR_PLLCTRL3_LSB 0 2415 #define CSR_PLLCTRL3_MASK GENMASK_32(15, 0) 2416 #define CSR_PLLSPARE_LSB 0 2417 #define CSR_PLLSPARE_MASK GENMASK_32(3, 0) 2418 #define CSR_PLLMAXRANGE_LSB 4 2419 #define CSR_PLLMAXRANGE_MASK GENMASK_32(8, 4) 2420 #define CSR_PLLDACVALIN_LSB 9 2421 #define CSR_PLLDACVALIN_MASK GENMASK_32(13, 9) 2422 #define CSR_PLLFORCECAL_LSB 14 2423 #define CSR_PLLFORCECAL_MASK BIT(14) 2424 #define CSR_PLLENCAL_LSB 15 2425 #define CSR_PLLENCAL_MASK BIT(15) 2426 /* CSR_PLLCTRL4 */ 2427 #define CSR_PLLCTRL4_LSB 0 2428 #define CSR_PLLCTRL4_MASK GENMASK_32(8, 0) 2429 #define CSR_PLLCPINTGSCTRL_LSB 0 2430 #define CSR_PLLCPINTGSCTRL_MASK GENMASK_32(4, 0) 2431 #define CSR_PLLCPPROPGSCTRL_LSB 5 2432 #define CSR_PLLCPPROPGSCTRL_MASK GENMASK_32(8, 5) 2433 /* CSR_PLLENDOFCAL */ 2434 #define CSR_PLLENDOFCAL_LSB 0 2435 #define CSR_PLLENDOFCAL_MASK BIT(0) 2436 /* CSR_PLLSTANDBYEFF */ 2437 #define CSR_PLLSTANDBYEFF_LSB 0 2438 #define CSR_PLLSTANDBYEFF_MASK BIT(0) 2439 /* CSR_PLLDACVALOUT */ 2440 #define CSR_PLLDACVALOUT_LSB 0 2441 #define CSR_PLLDACVALOUT_MASK GENMASK_32(4, 0) 2442 /* CSR_DLYTESTSEQ */ 2443 #define CSR_DLYTESTSEQ_LSB 0 2444 #define CSR_DLYTESTSEQ_MASK GENMASK_32(5, 0) 2445 #define CSR_DLYTESTEN_LSB 0 2446 #define CSR_DLYTESTEN_MASK BIT(0) 2447 #define CSR_DLYTESTCNTINIT_LSB 1 2448 #define CSR_DLYTESTCNTINIT_MASK BIT(1) 2449 #define CSR_DLYTESTENOVERRIDE1_LSB 2 2450 #define CSR_DLYTESTENOVERRIDE1_MASK BIT(2) 2451 #define CSR_DLYTESTENOVERRIDE2_LSB 3 2452 #define CSR_DLYTESTENOVERRIDE2_MASK BIT(3) 2453 #define CSR_SYNCDLYMULTIPLIER_LSB 4 2454 #define CSR_SYNCDLYMULTIPLIER_MASK GENMASK_32(5, 4) 2455 /* CSR_DLYTESTRINGSELDB */ 2456 #define CSR_DLYTESTRINGSELDB_LSB 0 2457 #define CSR_DLYTESTRINGSELDB_MASK GENMASK_32(4, 0) 2458 #define CSR_DLYTESTCUTDB_LSB 0 2459 #define CSR_DLYTESTCUTDB_MASK GENMASK_32(4, 0) 2460 /* CSR_DLYTESTRINGSELAC */ 2461 #define CSR_DLYTESTRINGSELAC_LSB 0 2462 #define CSR_DLYTESTRINGSELAC_MASK GENMASK_32(4, 0) 2463 #define CSR_DLYTESTCUTAC_LSB 0 2464 #define CSR_DLYTESTCUTAC_MASK GENMASK_32(4, 0) 2465 /* CSR_DLYTESTCNTDFICLKIV */ 2466 #define CSR_DLYTESTCNTDFICLKIV_LSB 0 2467 #define CSR_DLYTESTCNTDFICLKIV_MASK GENMASK_32(15, 0) 2468 /* CSR_DLYTESTCNTDFICLK */ 2469 #define CSR_DLYTESTCNTDFICLK_LSB 0 2470 #define CSR_DLYTESTCNTDFICLK_MASK GENMASK_32(15, 0) 2471 /* CSR_DLYTESTCNTRINGOSCDB0 */ 2472 #define CSR_DLYTESTCNTRINGOSCDB0_LSB 0 2473 #define CSR_DLYTESTCNTRINGOSCDB0_MASK GENMASK_32(15, 0) 2474 /* CSR_DLYTESTCNTRINGOSCDB1 */ 2475 #define CSR_DLYTESTCNTRINGOSCDB1_LSB 0 2476 #define CSR_DLYTESTCNTRINGOSCDB1_MASK GENMASK_32(15, 0) 2477 /* CSR_DLYTESTCNTRINGOSCDB2 */ 2478 #define CSR_DLYTESTCNTRINGOSCDB2_LSB 0 2479 #define CSR_DLYTESTCNTRINGOSCDB2_MASK GENMASK_32(15, 0) 2480 /* CSR_DLYTESTCNTRINGOSCDB3 */ 2481 #define CSR_DLYTESTCNTRINGOSCDB3_LSB 0 2482 #define CSR_DLYTESTCNTRINGOSCDB3_MASK GENMASK_32(15, 0) 2483 /* CSR_DLYTESTCNTRINGOSCDB4 */ 2484 #define CSR_DLYTESTCNTRINGOSCDB4_LSB 0 2485 #define CSR_DLYTESTCNTRINGOSCDB4_MASK GENMASK_32(15, 0) 2486 /* CSR_DLYTESTCNTRINGOSCDB5 */ 2487 #define CSR_DLYTESTCNTRINGOSCDB5_LSB 0 2488 #define CSR_DLYTESTCNTRINGOSCDB5_MASK GENMASK_32(15, 0) 2489 /* CSR_DLYTESTCNTRINGOSCDB6 */ 2490 #define CSR_DLYTESTCNTRINGOSCDB6_LSB 0 2491 #define CSR_DLYTESTCNTRINGOSCDB6_MASK GENMASK_32(15, 0) 2492 /* CSR_DLYTESTCNTRINGOSCDB7 */ 2493 #define CSR_DLYTESTCNTRINGOSCDB7_LSB 0 2494 #define CSR_DLYTESTCNTRINGOSCDB7_MASK GENMASK_32(15, 0) 2495 /* CSR_DLYTESTCNTRINGOSCDB8 */ 2496 #define CSR_DLYTESTCNTRINGOSCDB8_LSB 0 2497 #define CSR_DLYTESTCNTRINGOSCDB8_MASK GENMASK_32(15, 0) 2498 /* CSR_DLYTESTCNTRINGOSCDB9 */ 2499 #define CSR_DLYTESTCNTRINGOSCDB9_LSB 0 2500 #define CSR_DLYTESTCNTRINGOSCDB9_MASK GENMASK_32(15, 0) 2501 /* CSR_DLYTESTCNTRINGOSCAC */ 2502 #define CSR_DLYTESTCNTRINGOSCAC_LSB 0 2503 #define CSR_DLYTESTCNTRINGOSCAC_MASK GENMASK_32(15, 0) 2504 /* CSR_MSTLCDLDBGCNTL */ 2505 #define CSR_MSTLCDLDBGCNTL_LSB 0 2506 #define CSR_MSTLCDLDBGCNTL_MASK GENMASK_32(11, 0) 2507 #define CSR_MSTLCDLFINEOVRVAL_LSB 0 2508 #define CSR_MSTLCDLFINEOVRVAL_MASK GENMASK_32(8, 0) 2509 #define CSR_MSTLCDLFINEOVR_LSB 9 2510 #define CSR_MSTLCDLFINEOVR_MASK BIT(9) 2511 #define CSR_MSTLCDLFINESNAP_LSB 10 2512 #define CSR_MSTLCDLFINESNAP_MASK BIT(10) 2513 #define CSR_MSTLCDLTSTENABLE_LSB 11 2514 #define CSR_MSTLCDLTSTENABLE_MASK BIT(11) 2515 /* CSR_MSTLCDL0DBGRES */ 2516 #define CSR_MSTLCDL0DBGRES_LSB 0 2517 #define CSR_MSTLCDL0DBGRES_MASK GENMASK_32(12, 0) 2518 #define CSR_MSTLCDL0FINESNAPVAL_LSB 0 2519 #define CSR_MSTLCDL0FINESNAPVAL_MASK GENMASK_32(8, 0) 2520 #define CSR_MSTLCDL0PHDSNAPVAL_LSB 9 2521 #define CSR_MSTLCDL0PHDSNAPVAL_MASK BIT(9) 2522 #define CSR_MSTLCDL0STICKYLOCK_LSB 10 2523 #define CSR_MSTLCDL0STICKYLOCK_MASK BIT(10) 2524 #define CSR_MSTLCDL0STICKYUNLOCK_LSB 11 2525 #define CSR_MSTLCDL0STICKYUNLOCK_MASK BIT(11) 2526 #define CSR_MSTLCDL0LIVELOCK_LSB 12 2527 #define CSR_MSTLCDL0LIVELOCK_MASK BIT(12) 2528 /* CSR_MSTLCDL1DBGRES */ 2529 #define CSR_MSTLCDL1DBGRES_LSB 0 2530 #define CSR_MSTLCDL1DBGRES_MASK GENMASK_32(12, 0) 2531 #define CSR_MSTLCDL1FINESNAPVAL_LSB 0 2532 #define CSR_MSTLCDL1FINESNAPVAL_MASK GENMASK_32(8, 0) 2533 #define CSR_MSTLCDL1PHDSNAPVAL_LSB 9 2534 #define CSR_MSTLCDL1PHDSNAPVAL_MASK BIT(9) 2535 #define CSR_MSTLCDL1STICKYLOCK_LSB 10 2536 #define CSR_MSTLCDL1STICKYLOCK_MASK BIT(10) 2537 #define CSR_MSTLCDL1STICKYUNLOCK_LSB 11 2538 #define CSR_MSTLCDL1STICKYUNLOCK_MASK BIT(11) 2539 #define CSR_MSTLCDL1LIVELOCK_LSB 12 2540 #define CSR_MSTLCDL1LIVELOCK_MASK BIT(12) 2541 /* CSR_LCDLDBGCNTL */ 2542 #define CSR_LCDLDBGCNTL_LSB 0 2543 #define CSR_LCDLDBGCNTL_MASK GENMASK_32(15, 0) 2544 #define CSR_LCDLFINEOVRVAL_LSB 0 2545 #define CSR_LCDLFINEOVRVAL_MASK GENMASK_32(8, 0) 2546 #define CSR_LCDLFINEOVR_LSB 9 2547 #define CSR_LCDLFINEOVR_MASK BIT(9) 2548 #define CSR_LCDLFINESNAP_LSB 10 2549 #define CSR_LCDLFINESNAP_MASK BIT(10) 2550 #define CSR_LCDLTSTENABLE_LSB 11 2551 #define CSR_LCDLTSTENABLE_MASK BIT(11) 2552 #define CSR_LCDLSTATUSSEL_LSB 12 2553 #define CSR_LCDLSTATUSSEL_MASK GENMASK_32(15, 12) 2554 /* CSR_ACLCDLSTATUS */ 2555 #define CSR_ACLCDLSTATUS_LSB 0 2556 #define CSR_ACLCDLSTATUS_MASK GENMASK_32(13, 0) 2557 #define CSR_ACLCDLFINESNAPVAL_LSB 0 2558 #define CSR_ACLCDLFINESNAPVAL_MASK GENMASK_32(9, 0) 2559 #define CSR_ACLCDLPHDSNAPVAL_LSB 10 2560 #define CSR_ACLCDLPHDSNAPVAL_MASK BIT(10) 2561 #define CSR_ACLCDLSTICKYLOCK_LSB 11 2562 #define CSR_ACLCDLSTICKYLOCK_MASK BIT(11) 2563 #define CSR_ACLCDLSTICKYUNLOCK_LSB 12 2564 #define CSR_ACLCDLSTICKYUNLOCK_MASK BIT(12) 2565 #define CSR_ACLCDLLIVELOCK_LSB 13 2566 #define CSR_ACLCDLLIVELOCK_MASK BIT(13) 2567 /* CSR_CUSTPHYREV */ 2568 #define CSR_CUSTPHYREV_LSB 0 2569 #define CSR_CUSTPHYREV_MASK GENMASK_32(5, 0) 2570 /* CSR_PHYREV */ 2571 #define CSR_PHYREV_LSB 0 2572 #define CSR_PHYREV_MASK GENMASK_32(15, 0) 2573 #define CSR_PHYMNR_LSB 0 2574 #define CSR_PHYMNR_MASK GENMASK_32(3, 0) 2575 #define CSR_PHYMDR_LSB 4 2576 #define CSR_PHYMDR_MASK GENMASK_32(7, 4) 2577 #define CSR_PHYMJR_LSB 8 2578 #define CSR_PHYMJR_MASK GENMASK_32(15, 8) 2579 /* CSR_LP3EXITSEQ0BSTARTVECTOR */ 2580 #define CSR_LP3EXITSEQ0BSTARTVECTOR_LSB 0 2581 #define CSR_LP3EXITSEQ0BSTARTVECTOR_MASK GENMASK_32(7, 0) 2582 #define CSR_LP3EXITSEQ0BSTARTVECPLLENABLED_LSB 0 2583 #define CSR_LP3EXITSEQ0BSTARTVECPLLENABLED_MASK GENMASK_32(3, 0) 2584 #define CSR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_LSB 4 2585 #define CSR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_MASK GENMASK_32(7, 4) 2586 /* CSR_DFIFREQXLAT0 */ 2587 #define CSR_DFIFREQXLAT0_LSB 0 2588 #define CSR_DFIFREQXLAT0_MASK GENMASK_32(15, 0) 2589 #define CSR_DFIFREQXLATVAL0_LSB 0 2590 #define CSR_DFIFREQXLATVAL0_MASK GENMASK_32(3, 0) 2591 #define CSR_DFIFREQXLATVAL1_LSB 4 2592 #define CSR_DFIFREQXLATVAL1_MASK GENMASK_32(7, 4) 2593 #define CSR_DFIFREQXLATVAL2_LSB 8 2594 #define CSR_DFIFREQXLATVAL2_MASK GENMASK_32(11, 8) 2595 #define CSR_DFIFREQXLATVAL3_LSB 12 2596 #define CSR_DFIFREQXLATVAL3_MASK GENMASK_32(15, 12) 2597 /* CSR_DFIFREQXLAT1 */ 2598 #define CSR_DFIFREQXLAT1_LSB 0 2599 #define CSR_DFIFREQXLAT1_MASK GENMASK_32(15, 0) 2600 #define CSR_DFIFREQXLATVAL4_LSB 0 2601 #define CSR_DFIFREQXLATVAL4_MASK GENMASK_32(3, 0) 2602 #define CSR_DFIFREQXLATVAL5_LSB 4 2603 #define CSR_DFIFREQXLATVAL5_MASK GENMASK_32(7, 4) 2604 #define CSR_DFIFREQXLATVAL6_LSB 8 2605 #define CSR_DFIFREQXLATVAL6_MASK GENMASK_32(11, 8) 2606 #define CSR_DFIFREQXLATVAL7_LSB 12 2607 #define CSR_DFIFREQXLATVAL7_MASK GENMASK_32(15, 12) 2608 /* CSR_DFIFREQXLAT2 */ 2609 #define CSR_DFIFREQXLAT2_LSB 0 2610 #define CSR_DFIFREQXLAT2_MASK GENMASK_32(15, 0) 2611 #define CSR_DFIFREQXLATVAL8_LSB 0 2612 #define CSR_DFIFREQXLATVAL8_MASK GENMASK_32(3, 0) 2613 #define CSR_DFIFREQXLATVAL9_LSB 4 2614 #define CSR_DFIFREQXLATVAL9_MASK GENMASK_32(7, 4) 2615 #define CSR_DFIFREQXLATVAL10_LSB 8 2616 #define CSR_DFIFREQXLATVAL10_MASK GENMASK_32(11, 8) 2617 #define CSR_DFIFREQXLATVAL11_LSB 12 2618 #define CSR_DFIFREQXLATVAL11_MASK GENMASK_32(15, 12) 2619 /* CSR_DFIFREQXLAT3 */ 2620 #define CSR_DFIFREQXLAT3_LSB 0 2621 #define CSR_DFIFREQXLAT3_MASK GENMASK_32(15, 0) 2622 #define CSR_DFIFREQXLATVAL12_LSB 0 2623 #define CSR_DFIFREQXLATVAL12_MASK GENMASK_32(3, 0) 2624 #define CSR_DFIFREQXLATVAL13_LSB 4 2625 #define CSR_DFIFREQXLATVAL13_MASK GENMASK_32(7, 4) 2626 #define CSR_DFIFREQXLATVAL14_LSB 8 2627 #define CSR_DFIFREQXLATVAL14_MASK GENMASK_32(11, 8) 2628 #define CSR_DFIFREQXLATVAL15_LSB 12 2629 #define CSR_DFIFREQXLATVAL15_MASK GENMASK_32(15, 12) 2630 /* CSR_DFIFREQXLAT4 */ 2631 #define CSR_DFIFREQXLAT4_LSB 0 2632 #define CSR_DFIFREQXLAT4_MASK GENMASK_32(15, 0) 2633 #define CSR_DFIFREQXLATVAL16_LSB 0 2634 #define CSR_DFIFREQXLATVAL16_MASK GENMASK_32(3, 0) 2635 #define CSR_DFIFREQXLATVAL17_LSB 4 2636 #define CSR_DFIFREQXLATVAL17_MASK GENMASK_32(7, 4) 2637 #define CSR_DFIFREQXLATVAL18_LSB 8 2638 #define CSR_DFIFREQXLATVAL18_MASK GENMASK_32(11, 8) 2639 #define CSR_DFIFREQXLATVAL19_LSB 12 2640 #define CSR_DFIFREQXLATVAL19_MASK GENMASK_32(15, 12) 2641 /* CSR_DFIFREQXLAT5 */ 2642 #define CSR_DFIFREQXLAT5_LSB 0 2643 #define CSR_DFIFREQXLAT5_MASK GENMASK_32(15, 0) 2644 #define CSR_DFIFREQXLATVAL20_LSB 0 2645 #define CSR_DFIFREQXLATVAL20_MASK GENMASK_32(3, 0) 2646 #define CSR_DFIFREQXLATVAL21_LSB 4 2647 #define CSR_DFIFREQXLATVAL21_MASK GENMASK_32(7, 4) 2648 #define CSR_DFIFREQXLATVAL22_LSB 8 2649 #define CSR_DFIFREQXLATVAL22_MASK GENMASK_32(11, 8) 2650 #define CSR_DFIFREQXLATVAL23_LSB 12 2651 #define CSR_DFIFREQXLATVAL23_MASK GENMASK_32(15, 12) 2652 /* CSR_DFIFREQXLAT6 */ 2653 #define CSR_DFIFREQXLAT6_LSB 0 2654 #define CSR_DFIFREQXLAT6_MASK GENMASK_32(15, 0) 2655 #define CSR_DFIFREQXLATVAL24_LSB 0 2656 #define CSR_DFIFREQXLATVAL24_MASK GENMASK_32(3, 0) 2657 #define CSR_DFIFREQXLATVAL25_LSB 4 2658 #define CSR_DFIFREQXLATVAL25_MASK GENMASK_32(7, 4) 2659 #define CSR_DFIFREQXLATVAL26_LSB 8 2660 #define CSR_DFIFREQXLATVAL26_MASK GENMASK_32(11, 8) 2661 #define CSR_DFIFREQXLATVAL27_LSB 12 2662 #define CSR_DFIFREQXLATVAL27_MASK GENMASK_32(15, 12) 2663 /* CSR_DFIFREQXLAT7 */ 2664 #define CSR_DFIFREQXLAT7_LSB 0 2665 #define CSR_DFIFREQXLAT7_MASK GENMASK_32(15, 0) 2666 #define CSR_DFIFREQXLATVAL28_LSB 0 2667 #define CSR_DFIFREQXLATVAL28_MASK GENMASK_32(3, 0) 2668 #define CSR_DFIFREQXLATVAL29_LSB 4 2669 #define CSR_DFIFREQXLATVAL29_MASK GENMASK_32(7, 4) 2670 #define CSR_DFIFREQXLATVAL30_LSB 8 2671 #define CSR_DFIFREQXLATVAL30_MASK GENMASK_32(11, 8) 2672 #define CSR_DFIFREQXLATVAL31_LSB 12 2673 #define CSR_DFIFREQXLATVAL31_MASK GENMASK_32(15, 12) 2674 /* CSR_TXRDPTRINIT */ 2675 #define CSR_TXRDPTRINIT_LSB 0 2676 #define CSR_TXRDPTRINIT_MASK BIT(0) 2677 /* CSR_DFIINITCOMPLETE */ 2678 #define CSR_DFIINITCOMPLETE_LSB 0 2679 #define CSR_DFIINITCOMPLETE_MASK BIT(0) 2680 /* CSR_DFIFREQRATIO */ 2681 #define CSR_DFIFREQRATIO_LSB 0 2682 #define CSR_DFIFREQRATIO_MASK GENMASK_32(1, 0) 2683 /* CSR_RXFIFOCHECKS */ 2684 #define CSR_RXFIFOCHECKS_LSB 0 2685 #define CSR_RXFIFOCHECKS_MASK BIT(0) 2686 #define CSR_DOFREQUENTRXFIFOCHECKS_LSB 0 2687 #define CSR_DOFREQUENTRXFIFOCHECKS_MASK BIT(0) 2688 /* CSR_MTESTDTOCTRL */ 2689 #define CSR_MTESTDTOCTRL_LSB 0 2690 #define CSR_MTESTDTOCTRL_MASK BIT(0) 2691 #define CSR_MTESTDTOEN_LSB 0 2692 #define CSR_MTESTDTOEN_MASK BIT(0) 2693 /* CSR_MAPCAA0TODFI */ 2694 #define CSR_MAPCAA0TODFI_LSB 0 2695 #define CSR_MAPCAA0TODFI_MASK GENMASK_32(3, 0) 2696 /* CSR_MAPCAA1TODFI */ 2697 #define CSR_MAPCAA1TODFI_LSB 0 2698 #define CSR_MAPCAA1TODFI_MASK GENMASK_32(3, 0) 2699 /* CSR_MAPCAA2TODFI */ 2700 #define CSR_MAPCAA2TODFI_LSB 0 2701 #define CSR_MAPCAA2TODFI_MASK GENMASK_32(3, 0) 2702 /* CSR_MAPCAA3TODFI */ 2703 #define CSR_MAPCAA3TODFI_LSB 0 2704 #define CSR_MAPCAA3TODFI_MASK GENMASK_32(3, 0) 2705 /* CSR_MAPCAA4TODFI */ 2706 #define CSR_MAPCAA4TODFI_LSB 0 2707 #define CSR_MAPCAA4TODFI_MASK GENMASK_32(3, 0) 2708 /* CSR_MAPCAA5TODFI */ 2709 #define CSR_MAPCAA5TODFI_LSB 0 2710 #define CSR_MAPCAA5TODFI_MASK GENMASK_32(3, 0) 2711 /* CSR_MAPCAA6TODFI */ 2712 #define CSR_MAPCAA6TODFI_LSB 0 2713 #define CSR_MAPCAA6TODFI_MASK GENMASK_32(3, 0) 2714 /* CSR_MAPCAA7TODFI */ 2715 #define CSR_MAPCAA7TODFI_LSB 0 2716 #define CSR_MAPCAA7TODFI_MASK GENMASK_32(3, 0) 2717 /* CSR_MAPCAA8TODFI */ 2718 #define CSR_MAPCAA8TODFI_LSB 0 2719 #define CSR_MAPCAA8TODFI_MASK GENMASK_32(3, 0) 2720 /* CSR_MAPCAA9TODFI */ 2721 #define CSR_MAPCAA9TODFI_LSB 0 2722 #define CSR_MAPCAA9TODFI_MASK GENMASK_32(3, 0) 2723 /* CSR_MAPCAB0TODFI */ 2724 #define CSR_MAPCAB0TODFI_LSB 0 2725 #define CSR_MAPCAB0TODFI_MASK GENMASK_32(3, 0) 2726 /* CSR_MAPCAB1TODFI */ 2727 #define CSR_MAPCAB1TODFI_LSB 0 2728 #define CSR_MAPCAB1TODFI_MASK GENMASK_32(3, 0) 2729 /* CSR_MAPCAB2TODFI */ 2730 #define CSR_MAPCAB2TODFI_LSB 0 2731 #define CSR_MAPCAB2TODFI_MASK GENMASK_32(3, 0) 2732 /* CSR_MAPCAB3TODFI */ 2733 #define CSR_MAPCAB3TODFI_LSB 0 2734 #define CSR_MAPCAB3TODFI_MASK GENMASK_32(3, 0) 2735 /* CSR_MAPCAB4TODFI */ 2736 #define CSR_MAPCAB4TODFI_LSB 0 2737 #define CSR_MAPCAB4TODFI_MASK GENMASK_32(3, 0) 2738 /* CSR_MAPCAB5TODFI */ 2739 #define CSR_MAPCAB5TODFI_LSB 0 2740 #define CSR_MAPCAB5TODFI_MASK GENMASK_32(3, 0) 2741 /* CSR_MAPCAB6TODFI */ 2742 #define CSR_MAPCAB6TODFI_LSB 0 2743 #define CSR_MAPCAB6TODFI_MASK GENMASK_32(3, 0) 2744 /* CSR_MAPCAB7TODFI */ 2745 #define CSR_MAPCAB7TODFI_LSB 0 2746 #define CSR_MAPCAB7TODFI_MASK GENMASK_32(3, 0) 2747 /* CSR_MAPCAB8TODFI */ 2748 #define CSR_MAPCAB8TODFI_LSB 0 2749 #define CSR_MAPCAB8TODFI_MASK GENMASK_32(3, 0) 2750 /* CSR_MAPCAB9TODFI */ 2751 #define CSR_MAPCAB9TODFI_LSB 0 2752 #define CSR_MAPCAB9TODFI_MASK GENMASK_32(3, 0) 2753 /* CSR_PHYINTERRUPTENABLE */ 2754 #define CSR_PHYINTERRUPTENABLE_LSB 0 2755 #define CSR_PHYINTERRUPTENABLE_MASK GENMASK_32(15, 0) 2756 #define CSR_PHYTRNGCMPLTEN_LSB 0 2757 #define CSR_PHYTRNGCMPLTEN_MASK BIT(0) 2758 #define CSR_PHYINITCMPLTEN_LSB 1 2759 #define CSR_PHYINITCMPLTEN_MASK BIT(1) 2760 #define CSR_PHYTRNGFAILEN_LSB 2 2761 #define CSR_PHYTRNGFAILEN_MASK BIT(2) 2762 #define CSR_PHYFWRESERVEDEN_LSB 3 2763 #define CSR_PHYFWRESERVEDEN_MASK GENMASK_32(7, 3) 2764 #define CSR_PHYVTDRIFTALARMEN_LSB 8 2765 #define CSR_PHYVTDRIFTALARMEN_MASK GENMASK_32(9, 8) 2766 #define CSR_PHYRXFIFOCHECKEN_LSB 10 2767 #define CSR_PHYRXFIFOCHECKEN_MASK BIT(10) 2768 #define CSR_PHYHWRESERVEDEN_LSB 11 2769 #define CSR_PHYHWRESERVEDEN_MASK GENMASK_32(15, 11) 2770 /* CSR_PHYINTERRUPTFWCONTROL */ 2771 #define CSR_PHYINTERRUPTFWCONTROL_LSB 0 2772 #define CSR_PHYINTERRUPTFWCONTROL_MASK GENMASK_32(7, 0) 2773 #define CSR_PHYTRNGCMPLTFW_LSB 0 2774 #define CSR_PHYTRNGCMPLTFW_MASK BIT(0) 2775 #define CSR_PHYINITCMPLTFW_LSB 1 2776 #define CSR_PHYINITCMPLTFW_MASK BIT(1) 2777 #define CSR_PHYTRNGFAILFW_LSB 2 2778 #define CSR_PHYTRNGFAILFW_MASK BIT(2) 2779 #define CSR_PHYFWRESERVEDFW_LSB 3 2780 #define CSR_PHYFWRESERVEDFW_MASK GENMASK_32(7, 3) 2781 /* CSR_PHYINTERRUPTMASK */ 2782 #define CSR_PHYINTERRUPTMASK_LSB 0 2783 #define CSR_PHYINTERRUPTMASK_MASK GENMASK_32(15, 0) 2784 #define CSR_PHYTRNGCMPLTMSK_LSB 0 2785 #define CSR_PHYTRNGCMPLTMSK_MASK BIT(0) 2786 #define CSR_PHYINITCMPLTMSK_LSB 1 2787 #define CSR_PHYINITCMPLTMSK_MASK BIT(1) 2788 #define CSR_PHYTRNGFAILMSK_LSB 2 2789 #define CSR_PHYTRNGFAILMSK_MASK BIT(2) 2790 #define CSR_PHYFWRESERVEDMSK_LSB 3 2791 #define CSR_PHYFWRESERVEDMSK_MASK GENMASK_32(7, 3) 2792 #define CSR_PHYVTDRIFTALARMMSK_LSB 8 2793 #define CSR_PHYVTDRIFTALARMMSK_MASK GENMASK_32(9, 8) 2794 #define CSR_PHYRXFIFOCHECKMSK_LSB 10 2795 #define CSR_PHYRXFIFOCHECKMSK_MASK BIT(10) 2796 #define CSR_PHYHWRESERVEDMSK_LSB 11 2797 #define CSR_PHYHWRESERVEDMSK_MASK GENMASK_32(15, 11) 2798 /* CSR_PHYINTERRUPTCLEAR */ 2799 #define CSR_PHYINTERRUPTCLEAR_LSB 0 2800 #define CSR_PHYINTERRUPTCLEAR_MASK GENMASK_32(15, 0) 2801 #define CSR_PHYTRNGCMPLTCLR_LSB 0 2802 #define CSR_PHYTRNGCMPLTCLR_MASK BIT(0) 2803 #define CSR_PHYINITCMPLTCLR_LSB 1 2804 #define CSR_PHYINITCMPLTCLR_MASK BIT(1) 2805 #define CSR_PHYTRNGFAILCLR_LSB 2 2806 #define CSR_PHYTRNGFAILCLR_MASK BIT(2) 2807 #define CSR_PHYFWRESERVEDCLR_LSB 3 2808 #define CSR_PHYFWRESERVEDCLR_MASK GENMASK_32(7, 3) 2809 #define CSR_PHYVTDRIFTALARMCLR_LSB 8 2810 #define CSR_PHYVTDRIFTALARMCLR_MASK GENMASK_32(9, 8) 2811 #define CSR_PHYRXFIFOCHECKCLR_LSB 10 2812 #define CSR_PHYRXFIFOCHECKCLR_MASK BIT(10) 2813 #define CSR_PHYHWRESERVEDCLR_LSB 11 2814 #define CSR_PHYHWRESERVEDCLR_MASK GENMASK_32(15, 11) 2815 /* CSR_PHYINTERRUPTSTATUS */ 2816 #define CSR_PHYINTERRUPTSTATUS_LSB 0 2817 #define CSR_PHYINTERRUPTSTATUS_MASK GENMASK_32(15, 0) 2818 #define CSR_PHYTRNGCMPLT_LSB 0 2819 #define CSR_PHYTRNGCMPLT_MASK BIT(0) 2820 #define CSR_PHYINITCMPLT_LSB 1 2821 #define CSR_PHYINITCMPLT_MASK BIT(1) 2822 #define CSR_PHYTRNGFAIL_LSB 2 2823 #define CSR_PHYTRNGFAIL_MASK BIT(2) 2824 #define CSR_PHYFWRESERVED_LSB 3 2825 #define CSR_PHYFWRESERVED_MASK GENMASK_32(7, 3) 2826 #define CSR_VTDRIFTALARM_LSB 8 2827 #define CSR_VTDRIFTALARM_MASK GENMASK_32(9, 8) 2828 #define CSR_PHYRXFIFOCHECK_LSB 10 2829 #define CSR_PHYRXFIFOCHECK_MASK BIT(10) 2830 #define CSR_PHYHWRESERVED_LSB 11 2831 #define CSR_PHYHWRESERVED_MASK GENMASK_32(15, 11) 2832 /* CSR_HWTSWIZZLEHWTADDRESS0 */ 2833 #define CSR_HWTSWIZZLEHWTADDRESS0_LSB 0 2834 #define CSR_HWTSWIZZLEHWTADDRESS0_MASK GENMASK_32(4, 0) 2835 /* CSR_HWTSWIZZLEHWTADDRESS1 */ 2836 #define CSR_HWTSWIZZLEHWTADDRESS1_LSB 0 2837 #define CSR_HWTSWIZZLEHWTADDRESS1_MASK GENMASK_32(4, 0) 2838 /* CSR_HWTSWIZZLEHWTADDRESS2 */ 2839 #define CSR_HWTSWIZZLEHWTADDRESS2_LSB 0 2840 #define CSR_HWTSWIZZLEHWTADDRESS2_MASK GENMASK_32(4, 0) 2841 /* CSR_HWTSWIZZLEHWTADDRESS3 */ 2842 #define CSR_HWTSWIZZLEHWTADDRESS3_LSB 0 2843 #define CSR_HWTSWIZZLEHWTADDRESS3_MASK GENMASK_32(4, 0) 2844 /* CSR_HWTSWIZZLEHWTADDRESS4 */ 2845 #define CSR_HWTSWIZZLEHWTADDRESS4_LSB 0 2846 #define CSR_HWTSWIZZLEHWTADDRESS4_MASK GENMASK_32(4, 0) 2847 /* CSR_HWTSWIZZLEHWTADDRESS5 */ 2848 #define CSR_HWTSWIZZLEHWTADDRESS5_LSB 0 2849 #define CSR_HWTSWIZZLEHWTADDRESS5_MASK GENMASK_32(4, 0) 2850 /* CSR_HWTSWIZZLEHWTADDRESS6 */ 2851 #define CSR_HWTSWIZZLEHWTADDRESS6_LSB 0 2852 #define CSR_HWTSWIZZLEHWTADDRESS6_MASK GENMASK_32(4, 0) 2853 /* CSR_HWTSWIZZLEHWTADDRESS7 */ 2854 #define CSR_HWTSWIZZLEHWTADDRESS7_LSB 0 2855 #define CSR_HWTSWIZZLEHWTADDRESS7_MASK GENMASK_32(4, 0) 2856 /* CSR_HWTSWIZZLEHWTADDRESS8 */ 2857 #define CSR_HWTSWIZZLEHWTADDRESS8_LSB 0 2858 #define CSR_HWTSWIZZLEHWTADDRESS8_MASK GENMASK_32(4, 0) 2859 /* CSR_HWTSWIZZLEHWTADDRESS9 */ 2860 #define CSR_HWTSWIZZLEHWTADDRESS9_LSB 0 2861 #define CSR_HWTSWIZZLEHWTADDRESS9_MASK GENMASK_32(4, 0) 2862 /* CSR_HWTSWIZZLEHWTADDRESS10 */ 2863 #define CSR_HWTSWIZZLEHWTADDRESS10_LSB 0 2864 #define CSR_HWTSWIZZLEHWTADDRESS10_MASK GENMASK_32(4, 0) 2865 /* CSR_HWTSWIZZLEHWTADDRESS11 */ 2866 #define CSR_HWTSWIZZLEHWTADDRESS11_LSB 0 2867 #define CSR_HWTSWIZZLEHWTADDRESS11_MASK GENMASK_32(4, 0) 2868 /* CSR_HWTSWIZZLEHWTADDRESS12 */ 2869 #define CSR_HWTSWIZZLEHWTADDRESS12_LSB 0 2870 #define CSR_HWTSWIZZLEHWTADDRESS12_MASK GENMASK_32(4, 0) 2871 /* CSR_HWTSWIZZLEHWTADDRESS13 */ 2872 #define CSR_HWTSWIZZLEHWTADDRESS13_LSB 0 2873 #define CSR_HWTSWIZZLEHWTADDRESS13_MASK GENMASK_32(4, 0) 2874 /* CSR_HWTSWIZZLEHWTADDRESS14 */ 2875 #define CSR_HWTSWIZZLEHWTADDRESS14_LSB 0 2876 #define CSR_HWTSWIZZLEHWTADDRESS14_MASK GENMASK_32(4, 0) 2877 /* CSR_HWTSWIZZLEHWTADDRESS15 */ 2878 #define CSR_HWTSWIZZLEHWTADDRESS15_LSB 0 2879 #define CSR_HWTSWIZZLEHWTADDRESS15_MASK GENMASK_32(4, 0) 2880 /* CSR_HWTSWIZZLEHWTADDRESS17 */ 2881 #define CSR_HWTSWIZZLEHWTADDRESS17_LSB 0 2882 #define CSR_HWTSWIZZLEHWTADDRESS17_MASK GENMASK_32(4, 0) 2883 /* CSR_HWTSWIZZLEHWTACTN */ 2884 #define CSR_HWTSWIZZLEHWTACTN_LSB 0 2885 #define CSR_HWTSWIZZLEHWTACTN_MASK GENMASK_32(4, 0) 2886 /* CSR_HWTSWIZZLEHWTBANK0 */ 2887 #define CSR_HWTSWIZZLEHWTBANK0_LSB 0 2888 #define CSR_HWTSWIZZLEHWTBANK0_MASK GENMASK_32(4, 0) 2889 /* CSR_HWTSWIZZLEHWTBANK1 */ 2890 #define CSR_HWTSWIZZLEHWTBANK1_LSB 0 2891 #define CSR_HWTSWIZZLEHWTBANK1_MASK GENMASK_32(4, 0) 2892 /* CSR_HWTSWIZZLEHWTBANK2 */ 2893 #define CSR_HWTSWIZZLEHWTBANK2_LSB 0 2894 #define CSR_HWTSWIZZLEHWTBANK2_MASK GENMASK_32(4, 0) 2895 /* CSR_HWTSWIZZLEHWTBG0 */ 2896 #define CSR_HWTSWIZZLEHWTBG0_LSB 0 2897 #define CSR_HWTSWIZZLEHWTBG0_MASK GENMASK_32(4, 0) 2898 /* CSR_HWTSWIZZLEHWTBG1 */ 2899 #define CSR_HWTSWIZZLEHWTBG1_LSB 0 2900 #define CSR_HWTSWIZZLEHWTBG1_MASK GENMASK_32(4, 0) 2901 /* CSR_HWTSWIZZLEHWTCASN */ 2902 #define CSR_HWTSWIZZLEHWTCASN_LSB 0 2903 #define CSR_HWTSWIZZLEHWTCASN_MASK GENMASK_32(4, 0) 2904 /* CSR_HWTSWIZZLEHWTRASN */ 2905 #define CSR_HWTSWIZZLEHWTRASN_LSB 0 2906 #define CSR_HWTSWIZZLEHWTRASN_MASK GENMASK_32(4, 0) 2907 /* CSR_HWTSWIZZLEHWTWEN */ 2908 #define CSR_HWTSWIZZLEHWTWEN_LSB 0 2909 #define CSR_HWTSWIZZLEHWTWEN_MASK GENMASK_32(4, 0) 2910 /* CSR_HWTSWIZZLEHWTPARITYIN */ 2911 #define CSR_HWTSWIZZLEHWTPARITYIN_LSB 0 2912 #define CSR_HWTSWIZZLEHWTPARITYIN_MASK GENMASK_32(4, 0) 2913 /* CSR_DFIHANDSHAKEDELAYS0 */ 2914 #define CSR_DFIHANDSHAKEDELAYS0_LSB 0 2915 #define CSR_DFIHANDSHAKEDELAYS0_MASK GENMASK_32(15, 0) 2916 #define CSR_PHYUPDACKDELAY0_LSB 0 2917 #define CSR_PHYUPDACKDELAY0_MASK GENMASK_32(3, 0) 2918 #define CSR_PHYUPDREQDELAY0_LSB 4 2919 #define CSR_PHYUPDREQDELAY0_MASK GENMASK_32(7, 4) 2920 #define CSR_CTRLUPDACKDELAY0_LSB 8 2921 #define CSR_CTRLUPDACKDELAY0_MASK GENMASK_32(11, 8) 2922 #define CSR_CTRLUPDREQDELAY0_LSB 12 2923 #define CSR_CTRLUPDREQDELAY0_MASK GENMASK_32(15, 12) 2924 /* CSR_DFIHANDSHAKEDELAYS1 */ 2925 #define CSR_DFIHANDSHAKEDELAYS1_LSB 0 2926 #define CSR_DFIHANDSHAKEDELAYS1_MASK GENMASK_32(15, 0) 2927 #define CSR_PHYUPDACKDELAY1_LSB 0 2928 #define CSR_PHYUPDACKDELAY1_MASK GENMASK_32(3, 0) 2929 #define CSR_PHYUPDREQDELAY1_LSB 4 2930 #define CSR_PHYUPDREQDELAY1_MASK GENMASK_32(7, 4) 2931 #define CSR_CTRLUPDACKDELAY1_LSB 8 2932 #define CSR_CTRLUPDACKDELAY1_MASK GENMASK_32(11, 8) 2933 #define CSR_CTRLUPDREQDELAY1_LSB 12 2934 #define CSR_CTRLUPDREQDELAY1_MASK GENMASK_32(15, 12) 2935 /* CSR_REMOTEIMPCAL */ 2936 #define CSR_REMOTEIMPCAL_LSB 0 2937 #define CSR_REMOTEIMPCAL_MASK GENMASK_32(1, 0) 2938 #define CSR_CALIBSLAVE_LSB 0 2939 #define CSR_CALIBSLAVE_MASK BIT(0) 2940 #define CSR_SLAVECODEUPDATED_LSB 1 2941 #define CSR_SLAVECODEUPDATED_MASK BIT(1) 2942 /* CSR_ACLOOPBACKCTL */ 2943 #define CSR_ACLOOPBACKCTL_LSB 0 2944 #define CSR_ACLOOPBACKCTL_MASK GENMASK_32(1, 0) 2945 #define CSR_TERMINATION_LSB 0 2946 #define CSR_TERMINATION_MASK BIT(0) 2947 #define CSR_NOISECANCEL_LSB 1 2948 #define CSR_NOISECANCEL_MASK BIT(1) 2949 2950 /* ACSM0 register offsets */ 2951 /* CSR_ACSMSEQ0X0 */ 2952 #define CSR_ACSMSEQ0X0_LSB 0 2953 #define CSR_ACSMSEQ0X0_MASK GENMASK_32(15, 0) 2954 #define CSR_ACSMMCLKDLY0_LSB 0 2955 #define CSR_ACSMMCLKDLY0_MASK GENMASK_32(7, 0) 2956 #define CSR_ACSMDDRWE0_LSB 8 2957 #define CSR_ACSMDDRWE0_MASK BIT(8) 2958 #define CSR_ACSMDDRCAS0_LSB 9 2959 #define CSR_ACSMDDRCAS0_MASK BIT(9) 2960 #define CSR_ACSMDDRRAS0_LSB 10 2961 #define CSR_ACSMDDRRAS0_MASK BIT(10) 2962 #define CSR_ACSMDDRCKESET0_LSB 11 2963 #define CSR_ACSMDDRCKESET0_MASK BIT(11) 2964 #define CSR_ACSMDDRCKECLR0_LSB 12 2965 #define CSR_ACSMDDRCKECLR0_MASK BIT(12) 2966 #define CSR_ACSMSEQGATECMD0_LSB 13 2967 #define CSR_ACSMSEQGATECMD0_MASK BIT(13) 2968 #define CSR_ACSMSEQTERM0_LSB 14 2969 #define CSR_ACSMSEQTERM0_MASK BIT(14) 2970 #define CSR_ACSMLP3CA30_LSB 15 2971 #define CSR_ACSMLP3CA30_MASK BIT(15) 2972 /* CSR_ACSMSEQ0X1 */ 2973 #define CSR_ACSMSEQ0X1_LSB 0 2974 #define CSR_ACSMSEQ0X1_MASK GENMASK_32(15, 0) 2975 #define CSR_ACSMMCLKDLY1_LSB 0 2976 #define CSR_ACSMMCLKDLY1_MASK GENMASK_32(7, 0) 2977 #define CSR_ACSMDDRWE1_LSB 8 2978 #define CSR_ACSMDDRWE1_MASK BIT(8) 2979 #define CSR_ACSMDDRCAS1_LSB 9 2980 #define CSR_ACSMDDRCAS1_MASK BIT(9) 2981 #define CSR_ACSMDDRRAS1_LSB 10 2982 #define CSR_ACSMDDRRAS1_MASK BIT(10) 2983 #define CSR_ACSMDDRCKESET1_LSB 11 2984 #define CSR_ACSMDDRCKESET1_MASK BIT(11) 2985 #define CSR_ACSMDDRCKECLR1_LSB 12 2986 #define CSR_ACSMDDRCKECLR1_MASK BIT(12) 2987 #define CSR_ACSMSEQGATECMD1_LSB 13 2988 #define CSR_ACSMSEQGATECMD1_MASK BIT(13) 2989 #define CSR_ACSMSEQTERM1_LSB 14 2990 #define CSR_ACSMSEQTERM1_MASK BIT(14) 2991 #define CSR_ACSMLP3CA31_LSB 15 2992 #define CSR_ACSMLP3CA31_MASK BIT(15) 2993 /* CSR_ACSMSEQ0X2 */ 2994 #define CSR_ACSMSEQ0X2_LSB 0 2995 #define CSR_ACSMSEQ0X2_MASK GENMASK_32(15, 0) 2996 #define CSR_ACSMMCLKDLY2_LSB 0 2997 #define CSR_ACSMMCLKDLY2_MASK GENMASK_32(7, 0) 2998 #define CSR_ACSMDDRWE2_LSB 8 2999 #define CSR_ACSMDDRWE2_MASK BIT(8) 3000 #define CSR_ACSMDDRCAS2_LSB 9 3001 #define CSR_ACSMDDRCAS2_MASK BIT(9) 3002 #define CSR_ACSMDDRRAS2_LSB 10 3003 #define CSR_ACSMDDRRAS2_MASK BIT(10) 3004 #define CSR_ACSMDDRCKESET2_LSB 11 3005 #define CSR_ACSMDDRCKESET2_MASK BIT(11) 3006 #define CSR_ACSMDDRCKECLR2_LSB 12 3007 #define CSR_ACSMDDRCKECLR2_MASK BIT(12) 3008 #define CSR_ACSMSEQGATECMD2_LSB 13 3009 #define CSR_ACSMSEQGATECMD2_MASK BIT(13) 3010 #define CSR_ACSMSEQTERM2_LSB 14 3011 #define CSR_ACSMSEQTERM2_MASK BIT(14) 3012 #define CSR_ACSMLP3CA32_LSB 15 3013 #define CSR_ACSMLP3CA32_MASK BIT(15) 3014 /* CSR_ACSMSEQ0X3 */ 3015 #define CSR_ACSMSEQ0X3_LSB 0 3016 #define CSR_ACSMSEQ0X3_MASK GENMASK_32(15, 0) 3017 #define CSR_ACSMMCLKDLY3_LSB 0 3018 #define CSR_ACSMMCLKDLY3_MASK GENMASK_32(7, 0) 3019 #define CSR_ACSMDDRWE3_LSB 8 3020 #define CSR_ACSMDDRWE3_MASK BIT(8) 3021 #define CSR_ACSMDDRCAS3_LSB 9 3022 #define CSR_ACSMDDRCAS3_MASK BIT(9) 3023 #define CSR_ACSMDDRRAS3_LSB 10 3024 #define CSR_ACSMDDRRAS3_MASK BIT(10) 3025 #define CSR_ACSMDDRCKESET3_LSB 11 3026 #define CSR_ACSMDDRCKESET3_MASK BIT(11) 3027 #define CSR_ACSMDDRCKECLR3_LSB 12 3028 #define CSR_ACSMDDRCKECLR3_MASK BIT(12) 3029 #define CSR_ACSMSEQGATECMD3_LSB 13 3030 #define CSR_ACSMSEQGATECMD3_MASK BIT(13) 3031 #define CSR_ACSMSEQTERM3_LSB 14 3032 #define CSR_ACSMSEQTERM3_MASK BIT(14) 3033 #define CSR_ACSMLP3CA33_LSB 15 3034 #define CSR_ACSMLP3CA33_MASK BIT(15) 3035 /* CSR_ACSMSEQ0X4 */ 3036 #define CSR_ACSMSEQ0X4_LSB 0 3037 #define CSR_ACSMSEQ0X4_MASK GENMASK_32(15, 0) 3038 #define CSR_ACSMMCLKDLY4_LSB 0 3039 #define CSR_ACSMMCLKDLY4_MASK GENMASK_32(7, 0) 3040 #define CSR_ACSMDDRWE4_LSB 8 3041 #define CSR_ACSMDDRWE4_MASK BIT(8) 3042 #define CSR_ACSMDDRCAS4_LSB 9 3043 #define CSR_ACSMDDRCAS4_MASK BIT(9) 3044 #define CSR_ACSMDDRRAS4_LSB 10 3045 #define CSR_ACSMDDRRAS4_MASK BIT(10) 3046 #define CSR_ACSMDDRCKESET4_LSB 11 3047 #define CSR_ACSMDDRCKESET4_MASK BIT(11) 3048 #define CSR_ACSMDDRCKECLR4_LSB 12 3049 #define CSR_ACSMDDRCKECLR4_MASK BIT(12) 3050 #define CSR_ACSMSEQGATECMD4_LSB 13 3051 #define CSR_ACSMSEQGATECMD4_MASK BIT(13) 3052 #define CSR_ACSMSEQTERM4_LSB 14 3053 #define CSR_ACSMSEQTERM4_MASK BIT(14) 3054 #define CSR_ACSMLP3CA34_LSB 15 3055 #define CSR_ACSMLP3CA34_MASK BIT(15) 3056 /* CSR_ACSMSEQ0X5 */ 3057 #define CSR_ACSMSEQ0X5_LSB 0 3058 #define CSR_ACSMSEQ0X5_MASK GENMASK_32(15, 0) 3059 #define CSR_ACSMMCLKDLY5_LSB 0 3060 #define CSR_ACSMMCLKDLY5_MASK GENMASK_32(7, 0) 3061 #define CSR_ACSMDDRWE5_LSB 8 3062 #define CSR_ACSMDDRWE5_MASK BIT(8) 3063 #define CSR_ACSMDDRCAS5_LSB 9 3064 #define CSR_ACSMDDRCAS5_MASK BIT(9) 3065 #define CSR_ACSMDDRRAS5_LSB 10 3066 #define CSR_ACSMDDRRAS5_MASK BIT(10) 3067 #define CSR_ACSMDDRCKESET5_LSB 11 3068 #define CSR_ACSMDDRCKESET5_MASK BIT(11) 3069 #define CSR_ACSMDDRCKECLR5_LSB 12 3070 #define CSR_ACSMDDRCKECLR5_MASK BIT(12) 3071 #define CSR_ACSMSEQGATECMD5_LSB 13 3072 #define CSR_ACSMSEQGATECMD5_MASK BIT(13) 3073 #define CSR_ACSMSEQTERM5_LSB 14 3074 #define CSR_ACSMSEQTERM5_MASK BIT(14) 3075 #define CSR_ACSMLP3CA35_LSB 15 3076 #define CSR_ACSMLP3CA35_MASK BIT(15) 3077 /* CSR_ACSMSEQ0X6 */ 3078 #define CSR_ACSMSEQ0X6_LSB 0 3079 #define CSR_ACSMSEQ0X6_MASK GENMASK_32(15, 0) 3080 #define CSR_ACSMMCLKDLY6_LSB 0 3081 #define CSR_ACSMMCLKDLY6_MASK GENMASK_32(7, 0) 3082 #define CSR_ACSMDDRWE6_LSB 8 3083 #define CSR_ACSMDDRWE6_MASK BIT(8) 3084 #define CSR_ACSMDDRCAS6_LSB 9 3085 #define CSR_ACSMDDRCAS6_MASK BIT(9) 3086 #define CSR_ACSMDDRRAS6_LSB 10 3087 #define CSR_ACSMDDRRAS6_MASK BIT(10) 3088 #define CSR_ACSMDDRCKESET6_LSB 11 3089 #define CSR_ACSMDDRCKESET6_MASK BIT(11) 3090 #define CSR_ACSMDDRCKECLR6_LSB 12 3091 #define CSR_ACSMDDRCKECLR6_MASK BIT(12) 3092 #define CSR_ACSMSEQGATECMD6_LSB 13 3093 #define CSR_ACSMSEQGATECMD6_MASK BIT(13) 3094 #define CSR_ACSMSEQTERM6_LSB 14 3095 #define CSR_ACSMSEQTERM6_MASK BIT(14) 3096 #define CSR_ACSMLP3CA36_LSB 15 3097 #define CSR_ACSMLP3CA36_MASK BIT(15) 3098 /* CSR_ACSMSEQ0X7 */ 3099 #define CSR_ACSMSEQ0X7_LSB 0 3100 #define CSR_ACSMSEQ0X7_MASK GENMASK_32(15, 0) 3101 #define CSR_ACSMMCLKDLY7_LSB 0 3102 #define CSR_ACSMMCLKDLY7_MASK GENMASK_32(7, 0) 3103 #define CSR_ACSMDDRWE7_LSB 8 3104 #define CSR_ACSMDDRWE7_MASK BIT(8) 3105 #define CSR_ACSMDDRCAS7_LSB 9 3106 #define CSR_ACSMDDRCAS7_MASK BIT(9) 3107 #define CSR_ACSMDDRRAS7_LSB 10 3108 #define CSR_ACSMDDRRAS7_MASK BIT(10) 3109 #define CSR_ACSMDDRCKESET7_LSB 11 3110 #define CSR_ACSMDDRCKESET7_MASK BIT(11) 3111 #define CSR_ACSMDDRCKECLR7_LSB 12 3112 #define CSR_ACSMDDRCKECLR7_MASK BIT(12) 3113 #define CSR_ACSMSEQGATECMD7_LSB 13 3114 #define CSR_ACSMSEQGATECMD7_MASK BIT(13) 3115 #define CSR_ACSMSEQTERM7_LSB 14 3116 #define CSR_ACSMSEQTERM7_MASK BIT(14) 3117 #define CSR_ACSMLP3CA37_LSB 15 3118 #define CSR_ACSMLP3CA37_MASK BIT(15) 3119 /* CSR_ACSMSEQ0X8 */ 3120 #define CSR_ACSMSEQ0X8_LSB 0 3121 #define CSR_ACSMSEQ0X8_MASK GENMASK_32(15, 0) 3122 #define CSR_ACSMMCLKDLY8_LSB 0 3123 #define CSR_ACSMMCLKDLY8_MASK GENMASK_32(7, 0) 3124 #define CSR_ACSMDDRWE8_LSB 8 3125 #define CSR_ACSMDDRWE8_MASK BIT(8) 3126 #define CSR_ACSMDDRCAS8_LSB 9 3127 #define CSR_ACSMDDRCAS8_MASK BIT(9) 3128 #define CSR_ACSMDDRRAS8_LSB 10 3129 #define CSR_ACSMDDRRAS8_MASK BIT(10) 3130 #define CSR_ACSMDDRCKESET8_LSB 11 3131 #define CSR_ACSMDDRCKESET8_MASK BIT(11) 3132 #define CSR_ACSMDDRCKECLR8_LSB 12 3133 #define CSR_ACSMDDRCKECLR8_MASK BIT(12) 3134 #define CSR_ACSMSEQGATECMD8_LSB 13 3135 #define CSR_ACSMSEQGATECMD8_MASK BIT(13) 3136 #define CSR_ACSMSEQTERM8_LSB 14 3137 #define CSR_ACSMSEQTERM8_MASK BIT(14) 3138 #define CSR_ACSMLP3CA38_LSB 15 3139 #define CSR_ACSMLP3CA38_MASK BIT(15) 3140 /* CSR_ACSMSEQ0X9 */ 3141 #define CSR_ACSMSEQ0X9_LSB 0 3142 #define CSR_ACSMSEQ0X9_MASK GENMASK_32(15, 0) 3143 #define CSR_ACSMMCLKDLY9_LSB 0 3144 #define CSR_ACSMMCLKDLY9_MASK GENMASK_32(7, 0) 3145 #define CSR_ACSMDDRWE9_LSB 8 3146 #define CSR_ACSMDDRWE9_MASK BIT(8) 3147 #define CSR_ACSMDDRCAS9_LSB 9 3148 #define CSR_ACSMDDRCAS9_MASK BIT(9) 3149 #define CSR_ACSMDDRRAS9_LSB 10 3150 #define CSR_ACSMDDRRAS9_MASK BIT(10) 3151 #define CSR_ACSMDDRCKESET9_LSB 11 3152 #define CSR_ACSMDDRCKESET9_MASK BIT(11) 3153 #define CSR_ACSMDDRCKECLR9_LSB 12 3154 #define CSR_ACSMDDRCKECLR9_MASK BIT(12) 3155 #define CSR_ACSMSEQGATECMD9_LSB 13 3156 #define CSR_ACSMSEQGATECMD9_MASK BIT(13) 3157 #define CSR_ACSMSEQTERM9_LSB 14 3158 #define CSR_ACSMSEQTERM9_MASK BIT(14) 3159 #define CSR_ACSMLP3CA39_LSB 15 3160 #define CSR_ACSMLP3CA39_MASK BIT(15) 3161 /* CSR_ACSMSEQ0X10 */ 3162 #define CSR_ACSMSEQ0X10_LSB 0 3163 #define CSR_ACSMSEQ0X10_MASK GENMASK_32(15, 0) 3164 #define CSR_ACSMMCLKDLY10_LSB 0 3165 #define CSR_ACSMMCLKDLY10_MASK GENMASK_32(7, 0) 3166 #define CSR_ACSMDDRWE10_LSB 8 3167 #define CSR_ACSMDDRWE10_MASK BIT(8) 3168 #define CSR_ACSMDDRCAS10_LSB 9 3169 #define CSR_ACSMDDRCAS10_MASK BIT(9) 3170 #define CSR_ACSMDDRRAS10_LSB 10 3171 #define CSR_ACSMDDRRAS10_MASK BIT(10) 3172 #define CSR_ACSMDDRCKESET10_LSB 11 3173 #define CSR_ACSMDDRCKESET10_MASK BIT(11) 3174 #define CSR_ACSMDDRCKECLR10_LSB 12 3175 #define CSR_ACSMDDRCKECLR10_MASK BIT(12) 3176 #define CSR_ACSMSEQGATECMD10_LSB 13 3177 #define CSR_ACSMSEQGATECMD10_MASK BIT(13) 3178 #define CSR_ACSMSEQTERM10_LSB 14 3179 #define CSR_ACSMSEQTERM10_MASK BIT(14) 3180 #define CSR_ACSMLP3CA310_LSB 15 3181 #define CSR_ACSMLP3CA310_MASK BIT(15) 3182 /* CSR_ACSMSEQ0X11 */ 3183 #define CSR_ACSMSEQ0X11_LSB 0 3184 #define CSR_ACSMSEQ0X11_MASK GENMASK_32(15, 0) 3185 #define CSR_ACSMMCLKDLY11_LSB 0 3186 #define CSR_ACSMMCLKDLY11_MASK GENMASK_32(7, 0) 3187 #define CSR_ACSMDDRWE11_LSB 8 3188 #define CSR_ACSMDDRWE11_MASK BIT(8) 3189 #define CSR_ACSMDDRCAS11_LSB 9 3190 #define CSR_ACSMDDRCAS11_MASK BIT(9) 3191 #define CSR_ACSMDDRRAS11_LSB 10 3192 #define CSR_ACSMDDRRAS11_MASK BIT(10) 3193 #define CSR_ACSMDDRCKESET11_LSB 11 3194 #define CSR_ACSMDDRCKESET11_MASK BIT(11) 3195 #define CSR_ACSMDDRCKECLR11_LSB 12 3196 #define CSR_ACSMDDRCKECLR11_MASK BIT(12) 3197 #define CSR_ACSMSEQGATECMD11_LSB 13 3198 #define CSR_ACSMSEQGATECMD11_MASK BIT(13) 3199 #define CSR_ACSMSEQTERM11_LSB 14 3200 #define CSR_ACSMSEQTERM11_MASK BIT(14) 3201 #define CSR_ACSMLP3CA311_LSB 15 3202 #define CSR_ACSMLP3CA311_MASK BIT(15) 3203 /* CSR_ACSMSEQ0X12 */ 3204 #define CSR_ACSMSEQ0X12_LSB 0 3205 #define CSR_ACSMSEQ0X12_MASK GENMASK_32(15, 0) 3206 #define CSR_ACSMMCLKDLY12_LSB 0 3207 #define CSR_ACSMMCLKDLY12_MASK GENMASK_32(7, 0) 3208 #define CSR_ACSMDDRWE12_LSB 8 3209 #define CSR_ACSMDDRWE12_MASK BIT(8) 3210 #define CSR_ACSMDDRCAS12_LSB 9 3211 #define CSR_ACSMDDRCAS12_MASK BIT(9) 3212 #define CSR_ACSMDDRRAS12_LSB 10 3213 #define CSR_ACSMDDRRAS12_MASK BIT(10) 3214 #define CSR_ACSMDDRCKESET12_LSB 11 3215 #define CSR_ACSMDDRCKESET12_MASK BIT(11) 3216 #define CSR_ACSMDDRCKECLR12_LSB 12 3217 #define CSR_ACSMDDRCKECLR12_MASK BIT(12) 3218 #define CSR_ACSMSEQGATECMD12_LSB 13 3219 #define CSR_ACSMSEQGATECMD12_MASK BIT(13) 3220 #define CSR_ACSMSEQTERM12_LSB 14 3221 #define CSR_ACSMSEQTERM12_MASK BIT(14) 3222 #define CSR_ACSMLP3CA312_LSB 15 3223 #define CSR_ACSMLP3CA312_MASK BIT(15) 3224 /* CSR_ACSMSEQ0X13 */ 3225 #define CSR_ACSMSEQ0X13_LSB 0 3226 #define CSR_ACSMSEQ0X13_MASK GENMASK_32(15, 0) 3227 #define CSR_ACSMMCLKDLY13_LSB 0 3228 #define CSR_ACSMMCLKDLY13_MASK GENMASK_32(7, 0) 3229 #define CSR_ACSMDDRWE13_LSB 8 3230 #define CSR_ACSMDDRWE13_MASK BIT(8) 3231 #define CSR_ACSMDDRCAS13_LSB 9 3232 #define CSR_ACSMDDRCAS13_MASK BIT(9) 3233 #define CSR_ACSMDDRRAS13_LSB 10 3234 #define CSR_ACSMDDRRAS13_MASK BIT(10) 3235 #define CSR_ACSMDDRCKESET13_LSB 11 3236 #define CSR_ACSMDDRCKESET13_MASK BIT(11) 3237 #define CSR_ACSMDDRCKECLR13_LSB 12 3238 #define CSR_ACSMDDRCKECLR13_MASK BIT(12) 3239 #define CSR_ACSMSEQGATECMD13_LSB 13 3240 #define CSR_ACSMSEQGATECMD13_MASK BIT(13) 3241 #define CSR_ACSMSEQTERM13_LSB 14 3242 #define CSR_ACSMSEQTERM13_MASK BIT(14) 3243 #define CSR_ACSMLP3CA313_LSB 15 3244 #define CSR_ACSMLP3CA313_MASK BIT(15) 3245 /* CSR_ACSMSEQ0X14 */ 3246 #define CSR_ACSMSEQ0X14_LSB 0 3247 #define CSR_ACSMSEQ0X14_MASK GENMASK_32(15, 0) 3248 #define CSR_ACSMMCLKDLY14_LSB 0 3249 #define CSR_ACSMMCLKDLY14_MASK GENMASK_32(7, 0) 3250 #define CSR_ACSMDDRWE14_LSB 8 3251 #define CSR_ACSMDDRWE14_MASK BIT(8) 3252 #define CSR_ACSMDDRCAS14_LSB 9 3253 #define CSR_ACSMDDRCAS14_MASK BIT(9) 3254 #define CSR_ACSMDDRRAS14_LSB 10 3255 #define CSR_ACSMDDRRAS14_MASK BIT(10) 3256 #define CSR_ACSMDDRCKESET14_LSB 11 3257 #define CSR_ACSMDDRCKESET14_MASK BIT(11) 3258 #define CSR_ACSMDDRCKECLR14_LSB 12 3259 #define CSR_ACSMDDRCKECLR14_MASK BIT(12) 3260 #define CSR_ACSMSEQGATECMD14_LSB 13 3261 #define CSR_ACSMSEQGATECMD14_MASK BIT(13) 3262 #define CSR_ACSMSEQTERM14_LSB 14 3263 #define CSR_ACSMSEQTERM14_MASK BIT(14) 3264 #define CSR_ACSMLP3CA314_LSB 15 3265 #define CSR_ACSMLP3CA314_MASK BIT(15) 3266 /* CSR_ACSMSEQ0X15 */ 3267 #define CSR_ACSMSEQ0X15_LSB 0 3268 #define CSR_ACSMSEQ0X15_MASK GENMASK_32(15, 0) 3269 #define CSR_ACSMMCLKDLY15_LSB 0 3270 #define CSR_ACSMMCLKDLY15_MASK GENMASK_32(7, 0) 3271 #define CSR_ACSMDDRWE15_LSB 8 3272 #define CSR_ACSMDDRWE15_MASK BIT(8) 3273 #define CSR_ACSMDDRCAS15_LSB 9 3274 #define CSR_ACSMDDRCAS15_MASK BIT(9) 3275 #define CSR_ACSMDDRRAS15_LSB 10 3276 #define CSR_ACSMDDRRAS15_MASK BIT(10) 3277 #define CSR_ACSMDDRCKESET15_LSB 11 3278 #define CSR_ACSMDDRCKESET15_MASK BIT(11) 3279 #define CSR_ACSMDDRCKECLR15_LSB 12 3280 #define CSR_ACSMDDRCKECLR15_MASK BIT(12) 3281 #define CSR_ACSMSEQGATECMD15_LSB 13 3282 #define CSR_ACSMSEQGATECMD15_MASK BIT(13) 3283 #define CSR_ACSMSEQTERM15_LSB 14 3284 #define CSR_ACSMSEQTERM15_MASK BIT(14) 3285 #define CSR_ACSMLP3CA315_LSB 15 3286 #define CSR_ACSMLP3CA315_MASK BIT(15) 3287 /* CSR_ACSMSEQ0X16 */ 3288 #define CSR_ACSMSEQ0X16_LSB 0 3289 #define CSR_ACSMSEQ0X16_MASK GENMASK_32(15, 0) 3290 #define CSR_ACSMMCLKDLY16_LSB 0 3291 #define CSR_ACSMMCLKDLY16_MASK GENMASK_32(7, 0) 3292 #define CSR_ACSMDDRWE16_LSB 8 3293 #define CSR_ACSMDDRWE16_MASK BIT(8) 3294 #define CSR_ACSMDDRCAS16_LSB 9 3295 #define CSR_ACSMDDRCAS16_MASK BIT(9) 3296 #define CSR_ACSMDDRRAS16_LSB 10 3297 #define CSR_ACSMDDRRAS16_MASK BIT(10) 3298 #define CSR_ACSMDDRCKESET16_LSB 11 3299 #define CSR_ACSMDDRCKESET16_MASK BIT(11) 3300 #define CSR_ACSMDDRCKECLR16_LSB 12 3301 #define CSR_ACSMDDRCKECLR16_MASK BIT(12) 3302 #define CSR_ACSMSEQGATECMD16_LSB 13 3303 #define CSR_ACSMSEQGATECMD16_MASK BIT(13) 3304 #define CSR_ACSMSEQTERM16_LSB 14 3305 #define CSR_ACSMSEQTERM16_MASK BIT(14) 3306 #define CSR_ACSMLP3CA316_LSB 15 3307 #define CSR_ACSMLP3CA316_MASK BIT(15) 3308 /* CSR_ACSMSEQ0X17 */ 3309 #define CSR_ACSMSEQ0X17_LSB 0 3310 #define CSR_ACSMSEQ0X17_MASK GENMASK_32(15, 0) 3311 #define CSR_ACSMMCLKDLY17_LSB 0 3312 #define CSR_ACSMMCLKDLY17_MASK GENMASK_32(7, 0) 3313 #define CSR_ACSMDDRWE17_LSB 8 3314 #define CSR_ACSMDDRWE17_MASK BIT(8) 3315 #define CSR_ACSMDDRCAS17_LSB 9 3316 #define CSR_ACSMDDRCAS17_MASK BIT(9) 3317 #define CSR_ACSMDDRRAS17_LSB 10 3318 #define CSR_ACSMDDRRAS17_MASK BIT(10) 3319 #define CSR_ACSMDDRCKESET17_LSB 11 3320 #define CSR_ACSMDDRCKESET17_MASK BIT(11) 3321 #define CSR_ACSMDDRCKECLR17_LSB 12 3322 #define CSR_ACSMDDRCKECLR17_MASK BIT(12) 3323 #define CSR_ACSMSEQGATECMD17_LSB 13 3324 #define CSR_ACSMSEQGATECMD17_MASK BIT(13) 3325 #define CSR_ACSMSEQTERM17_LSB 14 3326 #define CSR_ACSMSEQTERM17_MASK BIT(14) 3327 #define CSR_ACSMLP3CA317_LSB 15 3328 #define CSR_ACSMLP3CA317_MASK BIT(15) 3329 /* CSR_ACSMSEQ0X18 */ 3330 #define CSR_ACSMSEQ0X18_LSB 0 3331 #define CSR_ACSMSEQ0X18_MASK GENMASK_32(15, 0) 3332 #define CSR_ACSMMCLKDLY18_LSB 0 3333 #define CSR_ACSMMCLKDLY18_MASK GENMASK_32(7, 0) 3334 #define CSR_ACSMDDRWE18_LSB 8 3335 #define CSR_ACSMDDRWE18_MASK BIT(8) 3336 #define CSR_ACSMDDRCAS18_LSB 9 3337 #define CSR_ACSMDDRCAS18_MASK BIT(9) 3338 #define CSR_ACSMDDRRAS18_LSB 10 3339 #define CSR_ACSMDDRRAS18_MASK BIT(10) 3340 #define CSR_ACSMDDRCKESET18_LSB 11 3341 #define CSR_ACSMDDRCKESET18_MASK BIT(11) 3342 #define CSR_ACSMDDRCKECLR18_LSB 12 3343 #define CSR_ACSMDDRCKECLR18_MASK BIT(12) 3344 #define CSR_ACSMSEQGATECMD18_LSB 13 3345 #define CSR_ACSMSEQGATECMD18_MASK BIT(13) 3346 #define CSR_ACSMSEQTERM18_LSB 14 3347 #define CSR_ACSMSEQTERM18_MASK BIT(14) 3348 #define CSR_ACSMLP3CA318_LSB 15 3349 #define CSR_ACSMLP3CA318_MASK BIT(15) 3350 /* CSR_ACSMSEQ0X19 */ 3351 #define CSR_ACSMSEQ0X19_LSB 0 3352 #define CSR_ACSMSEQ0X19_MASK GENMASK_32(15, 0) 3353 #define CSR_ACSMMCLKDLY19_LSB 0 3354 #define CSR_ACSMMCLKDLY19_MASK GENMASK_32(7, 0) 3355 #define CSR_ACSMDDRWE19_LSB 8 3356 #define CSR_ACSMDDRWE19_MASK BIT(8) 3357 #define CSR_ACSMDDRCAS19_LSB 9 3358 #define CSR_ACSMDDRCAS19_MASK BIT(9) 3359 #define CSR_ACSMDDRRAS19_LSB 10 3360 #define CSR_ACSMDDRRAS19_MASK BIT(10) 3361 #define CSR_ACSMDDRCKESET19_LSB 11 3362 #define CSR_ACSMDDRCKESET19_MASK BIT(11) 3363 #define CSR_ACSMDDRCKECLR19_LSB 12 3364 #define CSR_ACSMDDRCKECLR19_MASK BIT(12) 3365 #define CSR_ACSMSEQGATECMD19_LSB 13 3366 #define CSR_ACSMSEQGATECMD19_MASK BIT(13) 3367 #define CSR_ACSMSEQTERM19_LSB 14 3368 #define CSR_ACSMSEQTERM19_MASK BIT(14) 3369 #define CSR_ACSMLP3CA319_LSB 15 3370 #define CSR_ACSMLP3CA319_MASK BIT(15) 3371 /* CSR_ACSMSEQ0X20 */ 3372 #define CSR_ACSMSEQ0X20_LSB 0 3373 #define CSR_ACSMSEQ0X20_MASK GENMASK_32(15, 0) 3374 #define CSR_ACSMMCLKDLY20_LSB 0 3375 #define CSR_ACSMMCLKDLY20_MASK GENMASK_32(7, 0) 3376 #define CSR_ACSMDDRWE20_LSB 8 3377 #define CSR_ACSMDDRWE20_MASK BIT(8) 3378 #define CSR_ACSMDDRCAS20_LSB 9 3379 #define CSR_ACSMDDRCAS20_MASK BIT(9) 3380 #define CSR_ACSMDDRRAS20_LSB 10 3381 #define CSR_ACSMDDRRAS20_MASK BIT(10) 3382 #define CSR_ACSMDDRCKESET20_LSB 11 3383 #define CSR_ACSMDDRCKESET20_MASK BIT(11) 3384 #define CSR_ACSMDDRCKECLR20_LSB 12 3385 #define CSR_ACSMDDRCKECLR20_MASK BIT(12) 3386 #define CSR_ACSMSEQGATECMD20_LSB 13 3387 #define CSR_ACSMSEQGATECMD20_MASK BIT(13) 3388 #define CSR_ACSMSEQTERM20_LSB 14 3389 #define CSR_ACSMSEQTERM20_MASK BIT(14) 3390 #define CSR_ACSMLP3CA320_LSB 15 3391 #define CSR_ACSMLP3CA320_MASK BIT(15) 3392 /* CSR_ACSMSEQ0X21 */ 3393 #define CSR_ACSMSEQ0X21_LSB 0 3394 #define CSR_ACSMSEQ0X21_MASK GENMASK_32(15, 0) 3395 #define CSR_ACSMMCLKDLY21_LSB 0 3396 #define CSR_ACSMMCLKDLY21_MASK GENMASK_32(7, 0) 3397 #define CSR_ACSMDDRWE21_LSB 8 3398 #define CSR_ACSMDDRWE21_MASK BIT(8) 3399 #define CSR_ACSMDDRCAS21_LSB 9 3400 #define CSR_ACSMDDRCAS21_MASK BIT(9) 3401 #define CSR_ACSMDDRRAS21_LSB 10 3402 #define CSR_ACSMDDRRAS21_MASK BIT(10) 3403 #define CSR_ACSMDDRCKESET21_LSB 11 3404 #define CSR_ACSMDDRCKESET21_MASK BIT(11) 3405 #define CSR_ACSMDDRCKECLR21_LSB 12 3406 #define CSR_ACSMDDRCKECLR21_MASK BIT(12) 3407 #define CSR_ACSMSEQGATECMD21_LSB 13 3408 #define CSR_ACSMSEQGATECMD21_MASK BIT(13) 3409 #define CSR_ACSMSEQTERM21_LSB 14 3410 #define CSR_ACSMSEQTERM21_MASK BIT(14) 3411 #define CSR_ACSMLP3CA321_LSB 15 3412 #define CSR_ACSMLP3CA321_MASK BIT(15) 3413 /* CSR_ACSMSEQ0X22 */ 3414 #define CSR_ACSMSEQ0X22_LSB 0 3415 #define CSR_ACSMSEQ0X22_MASK GENMASK_32(15, 0) 3416 #define CSR_ACSMMCLKDLY22_LSB 0 3417 #define CSR_ACSMMCLKDLY22_MASK GENMASK_32(7, 0) 3418 #define CSR_ACSMDDRWE22_LSB 8 3419 #define CSR_ACSMDDRWE22_MASK BIT(8) 3420 #define CSR_ACSMDDRCAS22_LSB 9 3421 #define CSR_ACSMDDRCAS22_MASK BIT(9) 3422 #define CSR_ACSMDDRRAS22_LSB 10 3423 #define CSR_ACSMDDRRAS22_MASK BIT(10) 3424 #define CSR_ACSMDDRCKESET22_LSB 11 3425 #define CSR_ACSMDDRCKESET22_MASK BIT(11) 3426 #define CSR_ACSMDDRCKECLR22_LSB 12 3427 #define CSR_ACSMDDRCKECLR22_MASK BIT(12) 3428 #define CSR_ACSMSEQGATECMD22_LSB 13 3429 #define CSR_ACSMSEQGATECMD22_MASK BIT(13) 3430 #define CSR_ACSMSEQTERM22_LSB 14 3431 #define CSR_ACSMSEQTERM22_MASK BIT(14) 3432 #define CSR_ACSMLP3CA322_LSB 15 3433 #define CSR_ACSMLP3CA322_MASK BIT(15) 3434 /* CSR_ACSMSEQ0X23 */ 3435 #define CSR_ACSMSEQ0X23_LSB 0 3436 #define CSR_ACSMSEQ0X23_MASK GENMASK_32(15, 0) 3437 #define CSR_ACSMMCLKDLY23_LSB 0 3438 #define CSR_ACSMMCLKDLY23_MASK GENMASK_32(7, 0) 3439 #define CSR_ACSMDDRWE23_LSB 8 3440 #define CSR_ACSMDDRWE23_MASK BIT(8) 3441 #define CSR_ACSMDDRCAS23_LSB 9 3442 #define CSR_ACSMDDRCAS23_MASK BIT(9) 3443 #define CSR_ACSMDDRRAS23_LSB 10 3444 #define CSR_ACSMDDRRAS23_MASK BIT(10) 3445 #define CSR_ACSMDDRCKESET23_LSB 11 3446 #define CSR_ACSMDDRCKESET23_MASK BIT(11) 3447 #define CSR_ACSMDDRCKECLR23_LSB 12 3448 #define CSR_ACSMDDRCKECLR23_MASK BIT(12) 3449 #define CSR_ACSMSEQGATECMD23_LSB 13 3450 #define CSR_ACSMSEQGATECMD23_MASK BIT(13) 3451 #define CSR_ACSMSEQTERM23_LSB 14 3452 #define CSR_ACSMSEQTERM23_MASK BIT(14) 3453 #define CSR_ACSMLP3CA323_LSB 15 3454 #define CSR_ACSMLP3CA323_MASK BIT(15) 3455 /* CSR_ACSMSEQ0X24 */ 3456 #define CSR_ACSMSEQ0X24_LSB 0 3457 #define CSR_ACSMSEQ0X24_MASK GENMASK_32(15, 0) 3458 #define CSR_ACSMMCLKDLY24_LSB 0 3459 #define CSR_ACSMMCLKDLY24_MASK GENMASK_32(7, 0) 3460 #define CSR_ACSMDDRWE24_LSB 8 3461 #define CSR_ACSMDDRWE24_MASK BIT(8) 3462 #define CSR_ACSMDDRCAS24_LSB 9 3463 #define CSR_ACSMDDRCAS24_MASK BIT(9) 3464 #define CSR_ACSMDDRRAS24_LSB 10 3465 #define CSR_ACSMDDRRAS24_MASK BIT(10) 3466 #define CSR_ACSMDDRCKESET24_LSB 11 3467 #define CSR_ACSMDDRCKESET24_MASK BIT(11) 3468 #define CSR_ACSMDDRCKECLR24_LSB 12 3469 #define CSR_ACSMDDRCKECLR24_MASK BIT(12) 3470 #define CSR_ACSMSEQGATECMD24_LSB 13 3471 #define CSR_ACSMSEQGATECMD24_MASK BIT(13) 3472 #define CSR_ACSMSEQTERM24_LSB 14 3473 #define CSR_ACSMSEQTERM24_MASK BIT(14) 3474 #define CSR_ACSMLP3CA324_LSB 15 3475 #define CSR_ACSMLP3CA324_MASK BIT(15) 3476 /* CSR_ACSMSEQ0X25 */ 3477 #define CSR_ACSMSEQ0X25_LSB 0 3478 #define CSR_ACSMSEQ0X25_MASK GENMASK_32(15, 0) 3479 #define CSR_ACSMMCLKDLY25_LSB 0 3480 #define CSR_ACSMMCLKDLY25_MASK GENMASK_32(7, 0) 3481 #define CSR_ACSMDDRWE25_LSB 8 3482 #define CSR_ACSMDDRWE25_MASK BIT(8) 3483 #define CSR_ACSMDDRCAS25_LSB 9 3484 #define CSR_ACSMDDRCAS25_MASK BIT(9) 3485 #define CSR_ACSMDDRRAS25_LSB 10 3486 #define CSR_ACSMDDRRAS25_MASK BIT(10) 3487 #define CSR_ACSMDDRCKESET25_LSB 11 3488 #define CSR_ACSMDDRCKESET25_MASK BIT(11) 3489 #define CSR_ACSMDDRCKECLR25_LSB 12 3490 #define CSR_ACSMDDRCKECLR25_MASK BIT(12) 3491 #define CSR_ACSMSEQGATECMD25_LSB 13 3492 #define CSR_ACSMSEQGATECMD25_MASK BIT(13) 3493 #define CSR_ACSMSEQTERM25_LSB 14 3494 #define CSR_ACSMSEQTERM25_MASK BIT(14) 3495 #define CSR_ACSMLP3CA325_LSB 15 3496 #define CSR_ACSMLP3CA325_MASK BIT(15) 3497 /* CSR_ACSMSEQ0X26 */ 3498 #define CSR_ACSMSEQ0X26_LSB 0 3499 #define CSR_ACSMSEQ0X26_MASK GENMASK_32(15, 0) 3500 #define CSR_ACSMMCLKDLY26_LSB 0 3501 #define CSR_ACSMMCLKDLY26_MASK GENMASK_32(7, 0) 3502 #define CSR_ACSMDDRWE26_LSB 8 3503 #define CSR_ACSMDDRWE26_MASK BIT(8) 3504 #define CSR_ACSMDDRCAS26_LSB 9 3505 #define CSR_ACSMDDRCAS26_MASK BIT(9) 3506 #define CSR_ACSMDDRRAS26_LSB 10 3507 #define CSR_ACSMDDRRAS26_MASK BIT(10) 3508 #define CSR_ACSMDDRCKESET26_LSB 11 3509 #define CSR_ACSMDDRCKESET26_MASK BIT(11) 3510 #define CSR_ACSMDDRCKECLR26_LSB 12 3511 #define CSR_ACSMDDRCKECLR26_MASK BIT(12) 3512 #define CSR_ACSMSEQGATECMD26_LSB 13 3513 #define CSR_ACSMSEQGATECMD26_MASK BIT(13) 3514 #define CSR_ACSMSEQTERM26_LSB 14 3515 #define CSR_ACSMSEQTERM26_MASK BIT(14) 3516 #define CSR_ACSMLP3CA326_LSB 15 3517 #define CSR_ACSMLP3CA326_MASK BIT(15) 3518 /* CSR_ACSMSEQ0X27 */ 3519 #define CSR_ACSMSEQ0X27_LSB 0 3520 #define CSR_ACSMSEQ0X27_MASK GENMASK_32(15, 0) 3521 #define CSR_ACSMMCLKDLY27_LSB 0 3522 #define CSR_ACSMMCLKDLY27_MASK GENMASK_32(7, 0) 3523 #define CSR_ACSMDDRWE27_LSB 8 3524 #define CSR_ACSMDDRWE27_MASK BIT(8) 3525 #define CSR_ACSMDDRCAS27_LSB 9 3526 #define CSR_ACSMDDRCAS27_MASK BIT(9) 3527 #define CSR_ACSMDDRRAS27_LSB 10 3528 #define CSR_ACSMDDRRAS27_MASK BIT(10) 3529 #define CSR_ACSMDDRCKESET27_LSB 11 3530 #define CSR_ACSMDDRCKESET27_MASK BIT(11) 3531 #define CSR_ACSMDDRCKECLR27_LSB 12 3532 #define CSR_ACSMDDRCKECLR27_MASK BIT(12) 3533 #define CSR_ACSMSEQGATECMD27_LSB 13 3534 #define CSR_ACSMSEQGATECMD27_MASK BIT(13) 3535 #define CSR_ACSMSEQTERM27_LSB 14 3536 #define CSR_ACSMSEQTERM27_MASK BIT(14) 3537 #define CSR_ACSMLP3CA327_LSB 15 3538 #define CSR_ACSMLP3CA327_MASK BIT(15) 3539 /* CSR_ACSMSEQ0X28 */ 3540 #define CSR_ACSMSEQ0X28_LSB 0 3541 #define CSR_ACSMSEQ0X28_MASK GENMASK_32(15, 0) 3542 #define CSR_ACSMMCLKDLY28_LSB 0 3543 #define CSR_ACSMMCLKDLY28_MASK GENMASK_32(7, 0) 3544 #define CSR_ACSMDDRWE28_LSB 8 3545 #define CSR_ACSMDDRWE28_MASK BIT(8) 3546 #define CSR_ACSMDDRCAS28_LSB 9 3547 #define CSR_ACSMDDRCAS28_MASK BIT(9) 3548 #define CSR_ACSMDDRRAS28_LSB 10 3549 #define CSR_ACSMDDRRAS28_MASK BIT(10) 3550 #define CSR_ACSMDDRCKESET28_LSB 11 3551 #define CSR_ACSMDDRCKESET28_MASK BIT(11) 3552 #define CSR_ACSMDDRCKECLR28_LSB 12 3553 #define CSR_ACSMDDRCKECLR28_MASK BIT(12) 3554 #define CSR_ACSMSEQGATECMD28_LSB 13 3555 #define CSR_ACSMSEQGATECMD28_MASK BIT(13) 3556 #define CSR_ACSMSEQTERM28_LSB 14 3557 #define CSR_ACSMSEQTERM28_MASK BIT(14) 3558 #define CSR_ACSMLP3CA328_LSB 15 3559 #define CSR_ACSMLP3CA328_MASK BIT(15) 3560 /* CSR_ACSMSEQ0X29 */ 3561 #define CSR_ACSMSEQ0X29_LSB 0 3562 #define CSR_ACSMSEQ0X29_MASK GENMASK_32(15, 0) 3563 #define CSR_ACSMMCLKDLY29_LSB 0 3564 #define CSR_ACSMMCLKDLY29_MASK GENMASK_32(7, 0) 3565 #define CSR_ACSMDDRWE29_LSB 8 3566 #define CSR_ACSMDDRWE29_MASK BIT(8) 3567 #define CSR_ACSMDDRCAS29_LSB 9 3568 #define CSR_ACSMDDRCAS29_MASK BIT(9) 3569 #define CSR_ACSMDDRRAS29_LSB 10 3570 #define CSR_ACSMDDRRAS29_MASK BIT(10) 3571 #define CSR_ACSMDDRCKESET29_LSB 11 3572 #define CSR_ACSMDDRCKESET29_MASK BIT(11) 3573 #define CSR_ACSMDDRCKECLR29_LSB 12 3574 #define CSR_ACSMDDRCKECLR29_MASK BIT(12) 3575 #define CSR_ACSMSEQGATECMD29_LSB 13 3576 #define CSR_ACSMSEQGATECMD29_MASK BIT(13) 3577 #define CSR_ACSMSEQTERM29_LSB 14 3578 #define CSR_ACSMSEQTERM29_MASK BIT(14) 3579 #define CSR_ACSMLP3CA329_LSB 15 3580 #define CSR_ACSMLP3CA329_MASK BIT(15) 3581 /* CSR_ACSMSEQ0X30 */ 3582 #define CSR_ACSMSEQ0X30_LSB 0 3583 #define CSR_ACSMSEQ0X30_MASK GENMASK_32(15, 0) 3584 #define CSR_ACSMMCLKDLY30_LSB 0 3585 #define CSR_ACSMMCLKDLY30_MASK GENMASK_32(7, 0) 3586 #define CSR_ACSMDDRWE30_LSB 8 3587 #define CSR_ACSMDDRWE30_MASK BIT(8) 3588 #define CSR_ACSMDDRCAS30_LSB 9 3589 #define CSR_ACSMDDRCAS30_MASK BIT(9) 3590 #define CSR_ACSMDDRRAS30_LSB 10 3591 #define CSR_ACSMDDRRAS30_MASK BIT(10) 3592 #define CSR_ACSMDDRCKESET30_LSB 11 3593 #define CSR_ACSMDDRCKESET30_MASK BIT(11) 3594 #define CSR_ACSMDDRCKECLR30_LSB 12 3595 #define CSR_ACSMDDRCKECLR30_MASK BIT(12) 3596 #define CSR_ACSMSEQGATECMD30_LSB 13 3597 #define CSR_ACSMSEQGATECMD30_MASK BIT(13) 3598 #define CSR_ACSMSEQTERM30_LSB 14 3599 #define CSR_ACSMSEQTERM30_MASK BIT(14) 3600 #define CSR_ACSMLP3CA330_LSB 15 3601 #define CSR_ACSMLP3CA330_MASK BIT(15) 3602 /* CSR_ACSMSEQ0X31 */ 3603 #define CSR_ACSMSEQ0X31_LSB 0 3604 #define CSR_ACSMSEQ0X31_MASK GENMASK_32(15, 0) 3605 #define CSR_ACSMMCLKDLY31_LSB 0 3606 #define CSR_ACSMMCLKDLY31_MASK GENMASK_32(7, 0) 3607 #define CSR_ACSMDDRWE31_LSB 8 3608 #define CSR_ACSMDDRWE31_MASK BIT(8) 3609 #define CSR_ACSMDDRCAS31_LSB 9 3610 #define CSR_ACSMDDRCAS31_MASK BIT(9) 3611 #define CSR_ACSMDDRRAS31_LSB 10 3612 #define CSR_ACSMDDRRAS31_MASK BIT(10) 3613 #define CSR_ACSMDDRCKESET31_LSB 11 3614 #define CSR_ACSMDDRCKESET31_MASK BIT(11) 3615 #define CSR_ACSMDDRCKECLR31_LSB 12 3616 #define CSR_ACSMDDRCKECLR31_MASK BIT(12) 3617 #define CSR_ACSMSEQGATECMD31_LSB 13 3618 #define CSR_ACSMSEQGATECMD31_MASK BIT(13) 3619 #define CSR_ACSMSEQTERM31_LSB 14 3620 #define CSR_ACSMSEQTERM31_MASK BIT(14) 3621 #define CSR_ACSMLP3CA331_LSB 15 3622 #define CSR_ACSMLP3CA331_MASK BIT(15) 3623 /* CSR_ACSMSEQ1X0 */ 3624 #define CSR_ACSMSEQ1X0_LSB 0 3625 #define CSR_ACSMSEQ1X0_MASK GENMASK_32(15, 0) 3626 #define CSR_ACSMDDRCS0_LSB 0 3627 #define CSR_ACSMDDRCS0_MASK GENMASK_32(7, 0) 3628 #define CSR_ACSMSAVEGEN0_LSB 8 3629 #define CSR_ACSMSAVEGEN0_MASK BIT(8) 3630 #define CSR_ACSMLOADCHK0_LSB 9 3631 #define CSR_ACSMLOADCHK0_MASK BIT(9) 3632 #define CSR_ACSMNORXENB0_LSB 10 3633 #define CSR_ACSMNORXENB0_MASK BIT(10) 3634 #define CSR_ACSMNORXVAL0_LSB 11 3635 #define CSR_ACSMNORXVAL0_MASK BIT(11) 3636 #define CSR_ACSMDDRBNK0_LSB 12 3637 #define CSR_ACSMDDRBNK0_MASK GENMASK_32(15, 12) 3638 /* CSR_ACSMSEQ1X1 */ 3639 #define CSR_ACSMSEQ1X1_LSB 0 3640 #define CSR_ACSMSEQ1X1_MASK GENMASK_32(15, 0) 3641 #define CSR_ACSMDDRCS1_LSB 0 3642 #define CSR_ACSMDDRCS1_MASK GENMASK_32(7, 0) 3643 #define CSR_ACSMSAVEGEN1_LSB 8 3644 #define CSR_ACSMSAVEGEN1_MASK BIT(8) 3645 #define CSR_ACSMLOADCHK1_LSB 9 3646 #define CSR_ACSMLOADCHK1_MASK BIT(9) 3647 #define CSR_ACSMNORXENB1_LSB 10 3648 #define CSR_ACSMNORXENB1_MASK BIT(10) 3649 #define CSR_ACSMNORXVAL1_LSB 11 3650 #define CSR_ACSMNORXVAL1_MASK BIT(11) 3651 #define CSR_ACSMDDRBNK1_LSB 12 3652 #define CSR_ACSMDDRBNK1_MASK GENMASK_32(15, 12) 3653 /* CSR_ACSMSEQ1X2 */ 3654 #define CSR_ACSMSEQ1X2_LSB 0 3655 #define CSR_ACSMSEQ1X2_MASK GENMASK_32(15, 0) 3656 #define CSR_ACSMDDRCS2_LSB 0 3657 #define CSR_ACSMDDRCS2_MASK GENMASK_32(7, 0) 3658 #define CSR_ACSMSAVEGEN2_LSB 8 3659 #define CSR_ACSMSAVEGEN2_MASK BIT(8) 3660 #define CSR_ACSMLOADCHK2_LSB 9 3661 #define CSR_ACSMLOADCHK2_MASK BIT(9) 3662 #define CSR_ACSMNORXENB2_LSB 10 3663 #define CSR_ACSMNORXENB2_MASK BIT(10) 3664 #define CSR_ACSMNORXVAL2_LSB 11 3665 #define CSR_ACSMNORXVAL2_MASK BIT(11) 3666 #define CSR_ACSMDDRBNK2_LSB 12 3667 #define CSR_ACSMDDRBNK2_MASK GENMASK_32(15, 12) 3668 /* CSR_ACSMSEQ1X3 */ 3669 #define CSR_ACSMSEQ1X3_LSB 0 3670 #define CSR_ACSMSEQ1X3_MASK GENMASK_32(15, 0) 3671 #define CSR_ACSMDDRCS3_LSB 0 3672 #define CSR_ACSMDDRCS3_MASK GENMASK_32(7, 0) 3673 #define CSR_ACSMSAVEGEN3_LSB 8 3674 #define CSR_ACSMSAVEGEN3_MASK BIT(8) 3675 #define CSR_ACSMLOADCHK3_LSB 9 3676 #define CSR_ACSMLOADCHK3_MASK BIT(9) 3677 #define CSR_ACSMNORXENB3_LSB 10 3678 #define CSR_ACSMNORXENB3_MASK BIT(10) 3679 #define CSR_ACSMNORXVAL3_LSB 11 3680 #define CSR_ACSMNORXVAL3_MASK BIT(11) 3681 #define CSR_ACSMDDRBNK3_LSB 12 3682 #define CSR_ACSMDDRBNK3_MASK GENMASK_32(15, 12) 3683 /* CSR_ACSMSEQ1X4 */ 3684 #define CSR_ACSMSEQ1X4_LSB 0 3685 #define CSR_ACSMSEQ1X4_MASK GENMASK_32(15, 0) 3686 #define CSR_ACSMDDRCS4_LSB 0 3687 #define CSR_ACSMDDRCS4_MASK GENMASK_32(7, 0) 3688 #define CSR_ACSMSAVEGEN4_LSB 8 3689 #define CSR_ACSMSAVEGEN4_MASK BIT(8) 3690 #define CSR_ACSMLOADCHK4_LSB 9 3691 #define CSR_ACSMLOADCHK4_MASK BIT(9) 3692 #define CSR_ACSMNORXENB4_LSB 10 3693 #define CSR_ACSMNORXENB4_MASK BIT(10) 3694 #define CSR_ACSMNORXVAL4_LSB 11 3695 #define CSR_ACSMNORXVAL4_MASK BIT(11) 3696 #define CSR_ACSMDDRBNK4_LSB 12 3697 #define CSR_ACSMDDRBNK4_MASK GENMASK_32(15, 12) 3698 /* CSR_ACSMSEQ1X5 */ 3699 #define CSR_ACSMSEQ1X5_LSB 0 3700 #define CSR_ACSMSEQ1X5_MASK GENMASK_32(15, 0) 3701 #define CSR_ACSMDDRCS5_LSB 0 3702 #define CSR_ACSMDDRCS5_MASK GENMASK_32(7, 0) 3703 #define CSR_ACSMSAVEGEN5_LSB 8 3704 #define CSR_ACSMSAVEGEN5_MASK BIT(8) 3705 #define CSR_ACSMLOADCHK5_LSB 9 3706 #define CSR_ACSMLOADCHK5_MASK BIT(9) 3707 #define CSR_ACSMNORXENB5_LSB 10 3708 #define CSR_ACSMNORXENB5_MASK BIT(10) 3709 #define CSR_ACSMNORXVAL5_LSB 11 3710 #define CSR_ACSMNORXVAL5_MASK BIT(11) 3711 #define CSR_ACSMDDRBNK5_LSB 12 3712 #define CSR_ACSMDDRBNK5_MASK GENMASK_32(15, 12) 3713 /* CSR_ACSMSEQ1X6 */ 3714 #define CSR_ACSMSEQ1X6_LSB 0 3715 #define CSR_ACSMSEQ1X6_MASK GENMASK_32(15, 0) 3716 #define CSR_ACSMDDRCS6_LSB 0 3717 #define CSR_ACSMDDRCS6_MASK GENMASK_32(7, 0) 3718 #define CSR_ACSMSAVEGEN6_LSB 8 3719 #define CSR_ACSMSAVEGEN6_MASK BIT(8) 3720 #define CSR_ACSMLOADCHK6_LSB 9 3721 #define CSR_ACSMLOADCHK6_MASK BIT(9) 3722 #define CSR_ACSMNORXENB6_LSB 10 3723 #define CSR_ACSMNORXENB6_MASK BIT(10) 3724 #define CSR_ACSMNORXVAL6_LSB 11 3725 #define CSR_ACSMNORXVAL6_MASK BIT(11) 3726 #define CSR_ACSMDDRBNK6_LSB 12 3727 #define CSR_ACSMDDRBNK6_MASK GENMASK_32(15, 12) 3728 /* CSR_ACSMSEQ1X7 */ 3729 #define CSR_ACSMSEQ1X7_LSB 0 3730 #define CSR_ACSMSEQ1X7_MASK GENMASK_32(15, 0) 3731 #define CSR_ACSMDDRCS7_LSB 0 3732 #define CSR_ACSMDDRCS7_MASK GENMASK_32(7, 0) 3733 #define CSR_ACSMSAVEGEN7_LSB 8 3734 #define CSR_ACSMSAVEGEN7_MASK BIT(8) 3735 #define CSR_ACSMLOADCHK7_LSB 9 3736 #define CSR_ACSMLOADCHK7_MASK BIT(9) 3737 #define CSR_ACSMNORXENB7_LSB 10 3738 #define CSR_ACSMNORXENB7_MASK BIT(10) 3739 #define CSR_ACSMNORXVAL7_LSB 11 3740 #define CSR_ACSMNORXVAL7_MASK BIT(11) 3741 #define CSR_ACSMDDRBNK7_LSB 12 3742 #define CSR_ACSMDDRBNK7_MASK GENMASK_32(15, 12) 3743 /* CSR_ACSMSEQ1X8 */ 3744 #define CSR_ACSMSEQ1X8_LSB 0 3745 #define CSR_ACSMSEQ1X8_MASK GENMASK_32(15, 0) 3746 #define CSR_ACSMDDRCS8_LSB 0 3747 #define CSR_ACSMDDRCS8_MASK GENMASK_32(7, 0) 3748 #define CSR_ACSMSAVEGEN8_LSB 8 3749 #define CSR_ACSMSAVEGEN8_MASK BIT(8) 3750 #define CSR_ACSMLOADCHK8_LSB 9 3751 #define CSR_ACSMLOADCHK8_MASK BIT(9) 3752 #define CSR_ACSMNORXENB8_LSB 10 3753 #define CSR_ACSMNORXENB8_MASK BIT(10) 3754 #define CSR_ACSMNORXVAL8_LSB 11 3755 #define CSR_ACSMNORXVAL8_MASK BIT(11) 3756 #define CSR_ACSMDDRBNK8_LSB 12 3757 #define CSR_ACSMDDRBNK8_MASK GENMASK_32(15, 12) 3758 /* CSR_ACSMSEQ1X9 */ 3759 #define CSR_ACSMSEQ1X9_LSB 0 3760 #define CSR_ACSMSEQ1X9_MASK GENMASK_32(15, 0) 3761 #define CSR_ACSMDDRCS9_LSB 0 3762 #define CSR_ACSMDDRCS9_MASK GENMASK_32(7, 0) 3763 #define CSR_ACSMSAVEGEN9_LSB 8 3764 #define CSR_ACSMSAVEGEN9_MASK BIT(8) 3765 #define CSR_ACSMLOADCHK9_LSB 9 3766 #define CSR_ACSMLOADCHK9_MASK BIT(9) 3767 #define CSR_ACSMNORXENB9_LSB 10 3768 #define CSR_ACSMNORXENB9_MASK BIT(10) 3769 #define CSR_ACSMNORXVAL9_LSB 11 3770 #define CSR_ACSMNORXVAL9_MASK BIT(11) 3771 #define CSR_ACSMDDRBNK9_LSB 12 3772 #define CSR_ACSMDDRBNK9_MASK GENMASK_32(15, 12) 3773 /* CSR_ACSMSEQ1X10 */ 3774 #define CSR_ACSMSEQ1X10_LSB 0 3775 #define CSR_ACSMSEQ1X10_MASK GENMASK_32(15, 0) 3776 #define CSR_ACSMDDRCS10_LSB 0 3777 #define CSR_ACSMDDRCS10_MASK GENMASK_32(7, 0) 3778 #define CSR_ACSMSAVEGEN10_LSB 8 3779 #define CSR_ACSMSAVEGEN10_MASK BIT(8) 3780 #define CSR_ACSMLOADCHK10_LSB 9 3781 #define CSR_ACSMLOADCHK10_MASK BIT(9) 3782 #define CSR_ACSMNORXENB10_LSB 10 3783 #define CSR_ACSMNORXENB10_MASK BIT(10) 3784 #define CSR_ACSMNORXVAL10_LSB 11 3785 #define CSR_ACSMNORXVAL10_MASK BIT(11) 3786 #define CSR_ACSMDDRBNK10_LSB 12 3787 #define CSR_ACSMDDRBNK10_MASK GENMASK_32(15, 12) 3788 /* CSR_ACSMSEQ1X11 */ 3789 #define CSR_ACSMSEQ1X11_LSB 0 3790 #define CSR_ACSMSEQ1X11_MASK GENMASK_32(15, 0) 3791 #define CSR_ACSMDDRCS11_LSB 0 3792 #define CSR_ACSMDDRCS11_MASK GENMASK_32(7, 0) 3793 #define CSR_ACSMSAVEGEN11_LSB 8 3794 #define CSR_ACSMSAVEGEN11_MASK BIT(8) 3795 #define CSR_ACSMLOADCHK11_LSB 9 3796 #define CSR_ACSMLOADCHK11_MASK BIT(9) 3797 #define CSR_ACSMNORXENB11_LSB 10 3798 #define CSR_ACSMNORXENB11_MASK BIT(10) 3799 #define CSR_ACSMNORXVAL11_LSB 11 3800 #define CSR_ACSMNORXVAL11_MASK BIT(11) 3801 #define CSR_ACSMDDRBNK11_LSB 12 3802 #define CSR_ACSMDDRBNK11_MASK GENMASK_32(15, 12) 3803 /* CSR_ACSMSEQ1X12 */ 3804 #define CSR_ACSMSEQ1X12_LSB 0 3805 #define CSR_ACSMSEQ1X12_MASK GENMASK_32(15, 0) 3806 #define CSR_ACSMDDRCS12_LSB 0 3807 #define CSR_ACSMDDRCS12_MASK GENMASK_32(7, 0) 3808 #define CSR_ACSMSAVEGEN12_LSB 8 3809 #define CSR_ACSMSAVEGEN12_MASK BIT(8) 3810 #define CSR_ACSMLOADCHK12_LSB 9 3811 #define CSR_ACSMLOADCHK12_MASK BIT(9) 3812 #define CSR_ACSMNORXENB12_LSB 10 3813 #define CSR_ACSMNORXENB12_MASK BIT(10) 3814 #define CSR_ACSMNORXVAL12_LSB 11 3815 #define CSR_ACSMNORXVAL12_MASK BIT(11) 3816 #define CSR_ACSMDDRBNK12_LSB 12 3817 #define CSR_ACSMDDRBNK12_MASK GENMASK_32(15, 12) 3818 /* CSR_ACSMSEQ1X13 */ 3819 #define CSR_ACSMSEQ1X13_LSB 0 3820 #define CSR_ACSMSEQ1X13_MASK GENMASK_32(15, 0) 3821 #define CSR_ACSMDDRCS13_LSB 0 3822 #define CSR_ACSMDDRCS13_MASK GENMASK_32(7, 0) 3823 #define CSR_ACSMSAVEGEN13_LSB 8 3824 #define CSR_ACSMSAVEGEN13_MASK BIT(8) 3825 #define CSR_ACSMLOADCHK13_LSB 9 3826 #define CSR_ACSMLOADCHK13_MASK BIT(9) 3827 #define CSR_ACSMNORXENB13_LSB 10 3828 #define CSR_ACSMNORXENB13_MASK BIT(10) 3829 #define CSR_ACSMNORXVAL13_LSB 11 3830 #define CSR_ACSMNORXVAL13_MASK BIT(11) 3831 #define CSR_ACSMDDRBNK13_LSB 12 3832 #define CSR_ACSMDDRBNK13_MASK GENMASK_32(15, 12) 3833 /* CSR_ACSMSEQ1X14 */ 3834 #define CSR_ACSMSEQ1X14_LSB 0 3835 #define CSR_ACSMSEQ1X14_MASK GENMASK_32(15, 0) 3836 #define CSR_ACSMDDRCS14_LSB 0 3837 #define CSR_ACSMDDRCS14_MASK GENMASK_32(7, 0) 3838 #define CSR_ACSMSAVEGEN14_LSB 8 3839 #define CSR_ACSMSAVEGEN14_MASK BIT(8) 3840 #define CSR_ACSMLOADCHK14_LSB 9 3841 #define CSR_ACSMLOADCHK14_MASK BIT(9) 3842 #define CSR_ACSMNORXENB14_LSB 10 3843 #define CSR_ACSMNORXENB14_MASK BIT(10) 3844 #define CSR_ACSMNORXVAL14_LSB 11 3845 #define CSR_ACSMNORXVAL14_MASK BIT(11) 3846 #define CSR_ACSMDDRBNK14_LSB 12 3847 #define CSR_ACSMDDRBNK14_MASK GENMASK_32(15, 12) 3848 /* CSR_ACSMSEQ1X15 */ 3849 #define CSR_ACSMSEQ1X15_LSB 0 3850 #define CSR_ACSMSEQ1X15_MASK GENMASK_32(15, 0) 3851 #define CSR_ACSMDDRCS15_LSB 0 3852 #define CSR_ACSMDDRCS15_MASK GENMASK_32(7, 0) 3853 #define CSR_ACSMSAVEGEN15_LSB 8 3854 #define CSR_ACSMSAVEGEN15_MASK BIT(8) 3855 #define CSR_ACSMLOADCHK15_LSB 9 3856 #define CSR_ACSMLOADCHK15_MASK BIT(9) 3857 #define CSR_ACSMNORXENB15_LSB 10 3858 #define CSR_ACSMNORXENB15_MASK BIT(10) 3859 #define CSR_ACSMNORXVAL15_LSB 11 3860 #define CSR_ACSMNORXVAL15_MASK BIT(11) 3861 #define CSR_ACSMDDRBNK15_LSB 12 3862 #define CSR_ACSMDDRBNK15_MASK GENMASK_32(15, 12) 3863 /* CSR_ACSMSEQ1X16 */ 3864 #define CSR_ACSMSEQ1X16_LSB 0 3865 #define CSR_ACSMSEQ1X16_MASK GENMASK_32(15, 0) 3866 #define CSR_ACSMDDRCS16_LSB 0 3867 #define CSR_ACSMDDRCS16_MASK GENMASK_32(7, 0) 3868 #define CSR_ACSMSAVEGEN16_LSB 8 3869 #define CSR_ACSMSAVEGEN16_MASK BIT(8) 3870 #define CSR_ACSMLOADCHK16_LSB 9 3871 #define CSR_ACSMLOADCHK16_MASK BIT(9) 3872 #define CSR_ACSMNORXENB16_LSB 10 3873 #define CSR_ACSMNORXENB16_MASK BIT(10) 3874 #define CSR_ACSMNORXVAL16_LSB 11 3875 #define CSR_ACSMNORXVAL16_MASK BIT(11) 3876 #define CSR_ACSMDDRBNK16_LSB 12 3877 #define CSR_ACSMDDRBNK16_MASK GENMASK_32(15, 12) 3878 /* CSR_ACSMSEQ1X17 */ 3879 #define CSR_ACSMSEQ1X17_LSB 0 3880 #define CSR_ACSMSEQ1X17_MASK GENMASK_32(15, 0) 3881 #define CSR_ACSMDDRCS17_LSB 0 3882 #define CSR_ACSMDDRCS17_MASK GENMASK_32(7, 0) 3883 #define CSR_ACSMSAVEGEN17_LSB 8 3884 #define CSR_ACSMSAVEGEN17_MASK BIT(8) 3885 #define CSR_ACSMLOADCHK17_LSB 9 3886 #define CSR_ACSMLOADCHK17_MASK BIT(9) 3887 #define CSR_ACSMNORXENB17_LSB 10 3888 #define CSR_ACSMNORXENB17_MASK BIT(10) 3889 #define CSR_ACSMNORXVAL17_LSB 11 3890 #define CSR_ACSMNORXVAL17_MASK BIT(11) 3891 #define CSR_ACSMDDRBNK17_LSB 12 3892 #define CSR_ACSMDDRBNK17_MASK GENMASK_32(15, 12) 3893 /* CSR_ACSMSEQ1X18 */ 3894 #define CSR_ACSMSEQ1X18_LSB 0 3895 #define CSR_ACSMSEQ1X18_MASK GENMASK_32(15, 0) 3896 #define CSR_ACSMDDRCS18_LSB 0 3897 #define CSR_ACSMDDRCS18_MASK GENMASK_32(7, 0) 3898 #define CSR_ACSMSAVEGEN18_LSB 8 3899 #define CSR_ACSMSAVEGEN18_MASK BIT(8) 3900 #define CSR_ACSMLOADCHK18_LSB 9 3901 #define CSR_ACSMLOADCHK18_MASK BIT(9) 3902 #define CSR_ACSMNORXENB18_LSB 10 3903 #define CSR_ACSMNORXENB18_MASK BIT(10) 3904 #define CSR_ACSMNORXVAL18_LSB 11 3905 #define CSR_ACSMNORXVAL18_MASK BIT(11) 3906 #define CSR_ACSMDDRBNK18_LSB 12 3907 #define CSR_ACSMDDRBNK18_MASK GENMASK_32(15, 12) 3908 /* CSR_ACSMSEQ1X19 */ 3909 #define CSR_ACSMSEQ1X19_LSB 0 3910 #define CSR_ACSMSEQ1X19_MASK GENMASK_32(15, 0) 3911 #define CSR_ACSMDDRCS19_LSB 0 3912 #define CSR_ACSMDDRCS19_MASK GENMASK_32(7, 0) 3913 #define CSR_ACSMSAVEGEN19_LSB 8 3914 #define CSR_ACSMSAVEGEN19_MASK BIT(8) 3915 #define CSR_ACSMLOADCHK19_LSB 9 3916 #define CSR_ACSMLOADCHK19_MASK BIT(9) 3917 #define CSR_ACSMNORXENB19_LSB 10 3918 #define CSR_ACSMNORXENB19_MASK BIT(10) 3919 #define CSR_ACSMNORXVAL19_LSB 11 3920 #define CSR_ACSMNORXVAL19_MASK BIT(11) 3921 #define CSR_ACSMDDRBNK19_LSB 12 3922 #define CSR_ACSMDDRBNK19_MASK GENMASK_32(15, 12) 3923 /* CSR_ACSMSEQ1X20 */ 3924 #define CSR_ACSMSEQ1X20_LSB 0 3925 #define CSR_ACSMSEQ1X20_MASK GENMASK_32(15, 0) 3926 #define CSR_ACSMDDRCS20_LSB 0 3927 #define CSR_ACSMDDRCS20_MASK GENMASK_32(7, 0) 3928 #define CSR_ACSMSAVEGEN20_LSB 8 3929 #define CSR_ACSMSAVEGEN20_MASK BIT(8) 3930 #define CSR_ACSMLOADCHK20_LSB 9 3931 #define CSR_ACSMLOADCHK20_MASK BIT(9) 3932 #define CSR_ACSMNORXENB20_LSB 10 3933 #define CSR_ACSMNORXENB20_MASK BIT(10) 3934 #define CSR_ACSMNORXVAL20_LSB 11 3935 #define CSR_ACSMNORXVAL20_MASK BIT(11) 3936 #define CSR_ACSMDDRBNK20_LSB 12 3937 #define CSR_ACSMDDRBNK20_MASK GENMASK_32(15, 12) 3938 /* CSR_ACSMSEQ1X21 */ 3939 #define CSR_ACSMSEQ1X21_LSB 0 3940 #define CSR_ACSMSEQ1X21_MASK GENMASK_32(15, 0) 3941 #define CSR_ACSMDDRCS21_LSB 0 3942 #define CSR_ACSMDDRCS21_MASK GENMASK_32(7, 0) 3943 #define CSR_ACSMSAVEGEN21_LSB 8 3944 #define CSR_ACSMSAVEGEN21_MASK BIT(8) 3945 #define CSR_ACSMLOADCHK21_LSB 9 3946 #define CSR_ACSMLOADCHK21_MASK BIT(9) 3947 #define CSR_ACSMNORXENB21_LSB 10 3948 #define CSR_ACSMNORXENB21_MASK BIT(10) 3949 #define CSR_ACSMNORXVAL21_LSB 11 3950 #define CSR_ACSMNORXVAL21_MASK BIT(11) 3951 #define CSR_ACSMDDRBNK21_LSB 12 3952 #define CSR_ACSMDDRBNK21_MASK GENMASK_32(15, 12) 3953 /* CSR_ACSMSEQ1X22 */ 3954 #define CSR_ACSMSEQ1X22_LSB 0 3955 #define CSR_ACSMSEQ1X22_MASK GENMASK_32(15, 0) 3956 #define CSR_ACSMDDRCS22_LSB 0 3957 #define CSR_ACSMDDRCS22_MASK GENMASK_32(7, 0) 3958 #define CSR_ACSMSAVEGEN22_LSB 8 3959 #define CSR_ACSMSAVEGEN22_MASK BIT(8) 3960 #define CSR_ACSMLOADCHK22_LSB 9 3961 #define CSR_ACSMLOADCHK22_MASK BIT(9) 3962 #define CSR_ACSMNORXENB22_LSB 10 3963 #define CSR_ACSMNORXENB22_MASK BIT(10) 3964 #define CSR_ACSMNORXVAL22_LSB 11 3965 #define CSR_ACSMNORXVAL22_MASK BIT(11) 3966 #define CSR_ACSMDDRBNK22_LSB 12 3967 #define CSR_ACSMDDRBNK22_MASK GENMASK_32(15, 12) 3968 /* CSR_ACSMSEQ1X23 */ 3969 #define CSR_ACSMSEQ1X23_LSB 0 3970 #define CSR_ACSMSEQ1X23_MASK GENMASK_32(15, 0) 3971 #define CSR_ACSMDDRCS23_LSB 0 3972 #define CSR_ACSMDDRCS23_MASK GENMASK_32(7, 0) 3973 #define CSR_ACSMSAVEGEN23_LSB 8 3974 #define CSR_ACSMSAVEGEN23_MASK BIT(8) 3975 #define CSR_ACSMLOADCHK23_LSB 9 3976 #define CSR_ACSMLOADCHK23_MASK BIT(9) 3977 #define CSR_ACSMNORXENB23_LSB 10 3978 #define CSR_ACSMNORXENB23_MASK BIT(10) 3979 #define CSR_ACSMNORXVAL23_LSB 11 3980 #define CSR_ACSMNORXVAL23_MASK BIT(11) 3981 #define CSR_ACSMDDRBNK23_LSB 12 3982 #define CSR_ACSMDDRBNK23_MASK GENMASK_32(15, 12) 3983 /* CSR_ACSMSEQ1X24 */ 3984 #define CSR_ACSMSEQ1X24_LSB 0 3985 #define CSR_ACSMSEQ1X24_MASK GENMASK_32(15, 0) 3986 #define CSR_ACSMDDRCS24_LSB 0 3987 #define CSR_ACSMDDRCS24_MASK GENMASK_32(7, 0) 3988 #define CSR_ACSMSAVEGEN24_LSB 8 3989 #define CSR_ACSMSAVEGEN24_MASK BIT(8) 3990 #define CSR_ACSMLOADCHK24_LSB 9 3991 #define CSR_ACSMLOADCHK24_MASK BIT(9) 3992 #define CSR_ACSMNORXENB24_LSB 10 3993 #define CSR_ACSMNORXENB24_MASK BIT(10) 3994 #define CSR_ACSMNORXVAL24_LSB 11 3995 #define CSR_ACSMNORXVAL24_MASK BIT(11) 3996 #define CSR_ACSMDDRBNK24_LSB 12 3997 #define CSR_ACSMDDRBNK24_MASK GENMASK_32(15, 12) 3998 /* CSR_ACSMSEQ1X25 */ 3999 #define CSR_ACSMSEQ1X25_LSB 0 4000 #define CSR_ACSMSEQ1X25_MASK GENMASK_32(15, 0) 4001 #define CSR_ACSMDDRCS25_LSB 0 4002 #define CSR_ACSMDDRCS25_MASK GENMASK_32(7, 0) 4003 #define CSR_ACSMSAVEGEN25_LSB 8 4004 #define CSR_ACSMSAVEGEN25_MASK BIT(8) 4005 #define CSR_ACSMLOADCHK25_LSB 9 4006 #define CSR_ACSMLOADCHK25_MASK BIT(9) 4007 #define CSR_ACSMNORXENB25_LSB 10 4008 #define CSR_ACSMNORXENB25_MASK BIT(10) 4009 #define CSR_ACSMNORXVAL25_LSB 11 4010 #define CSR_ACSMNORXVAL25_MASK BIT(11) 4011 #define CSR_ACSMDDRBNK25_LSB 12 4012 #define CSR_ACSMDDRBNK25_MASK GENMASK_32(15, 12) 4013 /* CSR_ACSMSEQ1X26 */ 4014 #define CSR_ACSMSEQ1X26_LSB 0 4015 #define CSR_ACSMSEQ1X26_MASK GENMASK_32(15, 0) 4016 #define CSR_ACSMDDRCS26_LSB 0 4017 #define CSR_ACSMDDRCS26_MASK GENMASK_32(7, 0) 4018 #define CSR_ACSMSAVEGEN26_LSB 8 4019 #define CSR_ACSMSAVEGEN26_MASK BIT(8) 4020 #define CSR_ACSMLOADCHK26_LSB 9 4021 #define CSR_ACSMLOADCHK26_MASK BIT(9) 4022 #define CSR_ACSMNORXENB26_LSB 10 4023 #define CSR_ACSMNORXENB26_MASK BIT(10) 4024 #define CSR_ACSMNORXVAL26_LSB 11 4025 #define CSR_ACSMNORXVAL26_MASK BIT(11) 4026 #define CSR_ACSMDDRBNK26_LSB 12 4027 #define CSR_ACSMDDRBNK26_MASK GENMASK_32(15, 12) 4028 /* CSR_ACSMSEQ1X27 */ 4029 #define CSR_ACSMSEQ1X27_LSB 0 4030 #define CSR_ACSMSEQ1X27_MASK GENMASK_32(15, 0) 4031 #define CSR_ACSMDDRCS27_LSB 0 4032 #define CSR_ACSMDDRCS27_MASK GENMASK_32(7, 0) 4033 #define CSR_ACSMSAVEGEN27_LSB 8 4034 #define CSR_ACSMSAVEGEN27_MASK BIT(8) 4035 #define CSR_ACSMLOADCHK27_LSB 9 4036 #define CSR_ACSMLOADCHK27_MASK BIT(9) 4037 #define CSR_ACSMNORXENB27_LSB 10 4038 #define CSR_ACSMNORXENB27_MASK BIT(10) 4039 #define CSR_ACSMNORXVAL27_LSB 11 4040 #define CSR_ACSMNORXVAL27_MASK BIT(11) 4041 #define CSR_ACSMDDRBNK27_LSB 12 4042 #define CSR_ACSMDDRBNK27_MASK GENMASK_32(15, 12) 4043 /* CSR_ACSMSEQ1X28 */ 4044 #define CSR_ACSMSEQ1X28_LSB 0 4045 #define CSR_ACSMSEQ1X28_MASK GENMASK_32(15, 0) 4046 #define CSR_ACSMDDRCS28_LSB 0 4047 #define CSR_ACSMDDRCS28_MASK GENMASK_32(7, 0) 4048 #define CSR_ACSMSAVEGEN28_LSB 8 4049 #define CSR_ACSMSAVEGEN28_MASK BIT(8) 4050 #define CSR_ACSMLOADCHK28_LSB 9 4051 #define CSR_ACSMLOADCHK28_MASK BIT(9) 4052 #define CSR_ACSMNORXENB28_LSB 10 4053 #define CSR_ACSMNORXENB28_MASK BIT(10) 4054 #define CSR_ACSMNORXVAL28_LSB 11 4055 #define CSR_ACSMNORXVAL28_MASK BIT(11) 4056 #define CSR_ACSMDDRBNK28_LSB 12 4057 #define CSR_ACSMDDRBNK28_MASK GENMASK_32(15, 12) 4058 /* CSR_ACSMSEQ1X29 */ 4059 #define CSR_ACSMSEQ1X29_LSB 0 4060 #define CSR_ACSMSEQ1X29_MASK GENMASK_32(15, 0) 4061 #define CSR_ACSMDDRCS29_LSB 0 4062 #define CSR_ACSMDDRCS29_MASK GENMASK_32(7, 0) 4063 #define CSR_ACSMSAVEGEN29_LSB 8 4064 #define CSR_ACSMSAVEGEN29_MASK BIT(8) 4065 #define CSR_ACSMLOADCHK29_LSB 9 4066 #define CSR_ACSMLOADCHK29_MASK BIT(9) 4067 #define CSR_ACSMNORXENB29_LSB 10 4068 #define CSR_ACSMNORXENB29_MASK BIT(10) 4069 #define CSR_ACSMNORXVAL29_LSB 11 4070 #define CSR_ACSMNORXVAL29_MASK BIT(11) 4071 #define CSR_ACSMDDRBNK29_LSB 12 4072 #define CSR_ACSMDDRBNK29_MASK GENMASK_32(15, 12) 4073 /* CSR_ACSMSEQ1X30 */ 4074 #define CSR_ACSMSEQ1X30_LSB 0 4075 #define CSR_ACSMSEQ1X30_MASK GENMASK_32(15, 0) 4076 #define CSR_ACSMDDRCS30_LSB 0 4077 #define CSR_ACSMDDRCS30_MASK GENMASK_32(7, 0) 4078 #define CSR_ACSMSAVEGEN30_LSB 8 4079 #define CSR_ACSMSAVEGEN30_MASK BIT(8) 4080 #define CSR_ACSMLOADCHK30_LSB 9 4081 #define CSR_ACSMLOADCHK30_MASK BIT(9) 4082 #define CSR_ACSMNORXENB30_LSB 10 4083 #define CSR_ACSMNORXENB30_MASK BIT(10) 4084 #define CSR_ACSMNORXVAL30_LSB 11 4085 #define CSR_ACSMNORXVAL30_MASK BIT(11) 4086 #define CSR_ACSMDDRBNK30_LSB 12 4087 #define CSR_ACSMDDRBNK30_MASK GENMASK_32(15, 12) 4088 /* CSR_ACSMSEQ1X31 */ 4089 #define CSR_ACSMSEQ1X31_LSB 0 4090 #define CSR_ACSMSEQ1X31_MASK GENMASK_32(15, 0) 4091 #define CSR_ACSMDDRCS31_LSB 0 4092 #define CSR_ACSMDDRCS31_MASK GENMASK_32(7, 0) 4093 #define CSR_ACSMSAVEGEN31_LSB 8 4094 #define CSR_ACSMSAVEGEN31_MASK BIT(8) 4095 #define CSR_ACSMLOADCHK31_LSB 9 4096 #define CSR_ACSMLOADCHK31_MASK BIT(9) 4097 #define CSR_ACSMNORXENB31_LSB 10 4098 #define CSR_ACSMNORXENB31_MASK BIT(10) 4099 #define CSR_ACSMNORXVAL31_LSB 11 4100 #define CSR_ACSMNORXVAL31_MASK BIT(11) 4101 #define CSR_ACSMDDRBNK31_LSB 12 4102 #define CSR_ACSMDDRBNK31_MASK GENMASK_32(15, 12) 4103 /* CSR_ACSMSEQ2X0 */ 4104 #define CSR_ACSMSEQ2X0_LSB 0 4105 #define CSR_ACSMSEQ2X0_MASK GENMASK_32(15, 0) 4106 #define CSR_ACSMDDRADRX15X0X0_LSB 0 4107 #define CSR_ACSMDDRADRX15X0X0_MASK GENMASK_32(15, 0) 4108 /* CSR_ACSMSEQ2X1 */ 4109 #define CSR_ACSMSEQ2X1_LSB 0 4110 #define CSR_ACSMSEQ2X1_MASK GENMASK_32(15, 0) 4111 #define CSR_ACSMDDRADRX15X0X1_LSB 0 4112 #define CSR_ACSMDDRADRX15X0X1_MASK GENMASK_32(15, 0) 4113 /* CSR_ACSMSEQ2X2 */ 4114 #define CSR_ACSMSEQ2X2_LSB 0 4115 #define CSR_ACSMSEQ2X2_MASK GENMASK_32(15, 0) 4116 #define CSR_ACSMDDRADRX15X0X2_LSB 0 4117 #define CSR_ACSMDDRADRX15X0X2_MASK GENMASK_32(15, 0) 4118 /* CSR_ACSMSEQ2X3 */ 4119 #define CSR_ACSMSEQ2X3_LSB 0 4120 #define CSR_ACSMSEQ2X3_MASK GENMASK_32(15, 0) 4121 #define CSR_ACSMDDRADRX15X0X3_LSB 0 4122 #define CSR_ACSMDDRADRX15X0X3_MASK GENMASK_32(15, 0) 4123 /* CSR_ACSMSEQ2X4 */ 4124 #define CSR_ACSMSEQ2X4_LSB 0 4125 #define CSR_ACSMSEQ2X4_MASK GENMASK_32(15, 0) 4126 #define CSR_ACSMDDRADRX15X0X4_LSB 0 4127 #define CSR_ACSMDDRADRX15X0X4_MASK GENMASK_32(15, 0) 4128 /* CSR_ACSMSEQ2X5 */ 4129 #define CSR_ACSMSEQ2X5_LSB 0 4130 #define CSR_ACSMSEQ2X5_MASK GENMASK_32(15, 0) 4131 #define CSR_ACSMDDRADRX15X0X5_LSB 0 4132 #define CSR_ACSMDDRADRX15X0X5_MASK GENMASK_32(15, 0) 4133 /* CSR_ACSMSEQ2X6 */ 4134 #define CSR_ACSMSEQ2X6_LSB 0 4135 #define CSR_ACSMSEQ2X6_MASK GENMASK_32(15, 0) 4136 #define CSR_ACSMDDRADRX15X0X6_LSB 0 4137 #define CSR_ACSMDDRADRX15X0X6_MASK GENMASK_32(15, 0) 4138 /* CSR_ACSMSEQ2X7 */ 4139 #define CSR_ACSMSEQ2X7_LSB 0 4140 #define CSR_ACSMSEQ2X7_MASK GENMASK_32(15, 0) 4141 #define CSR_ACSMDDRADRX15X0X7_LSB 0 4142 #define CSR_ACSMDDRADRX15X0X7_MASK GENMASK_32(15, 0) 4143 /* CSR_ACSMSEQ2X8 */ 4144 #define CSR_ACSMSEQ2X8_LSB 0 4145 #define CSR_ACSMSEQ2X8_MASK GENMASK_32(15, 0) 4146 #define CSR_ACSMDDRADRX15X0X8_LSB 0 4147 #define CSR_ACSMDDRADRX15X0X8_MASK GENMASK_32(15, 0) 4148 /* CSR_ACSMSEQ2X9 */ 4149 #define CSR_ACSMSEQ2X9_LSB 0 4150 #define CSR_ACSMSEQ2X9_MASK GENMASK_32(15, 0) 4151 #define CSR_ACSMDDRADRX15X0X9_LSB 0 4152 #define CSR_ACSMDDRADRX15X0X9_MASK GENMASK_32(15, 0) 4153 /* CSR_ACSMSEQ2X10 */ 4154 #define CSR_ACSMSEQ2X10_LSB 0 4155 #define CSR_ACSMSEQ2X10_MASK GENMASK_32(15, 0) 4156 #define CSR_ACSMDDRADRX15X0X10_LSB 0 4157 #define CSR_ACSMDDRADRX15X0X10_MASK GENMASK_32(15, 0) 4158 /* CSR_ACSMSEQ2X11 */ 4159 #define CSR_ACSMSEQ2X11_LSB 0 4160 #define CSR_ACSMSEQ2X11_MASK GENMASK_32(15, 0) 4161 #define CSR_ACSMDDRADRX15X0X11_LSB 0 4162 #define CSR_ACSMDDRADRX15X0X11_MASK GENMASK_32(15, 0) 4163 /* CSR_ACSMSEQ2X12 */ 4164 #define CSR_ACSMSEQ2X12_LSB 0 4165 #define CSR_ACSMSEQ2X12_MASK GENMASK_32(15, 0) 4166 #define CSR_ACSMDDRADRX15X0X12_LSB 0 4167 #define CSR_ACSMDDRADRX15X0X12_MASK GENMASK_32(15, 0) 4168 /* CSR_ACSMSEQ2X13 */ 4169 #define CSR_ACSMSEQ2X13_LSB 0 4170 #define CSR_ACSMSEQ2X13_MASK GENMASK_32(15, 0) 4171 #define CSR_ACSMDDRADRX15X0X13_LSB 0 4172 #define CSR_ACSMDDRADRX15X0X13_MASK GENMASK_32(15, 0) 4173 /* CSR_ACSMSEQ2X14 */ 4174 #define CSR_ACSMSEQ2X14_LSB 0 4175 #define CSR_ACSMSEQ2X14_MASK GENMASK_32(15, 0) 4176 #define CSR_ACSMDDRADRX15X0X14_LSB 0 4177 #define CSR_ACSMDDRADRX15X0X14_MASK GENMASK_32(15, 0) 4178 /* CSR_ACSMSEQ2X15 */ 4179 #define CSR_ACSMSEQ2X15_LSB 0 4180 #define CSR_ACSMSEQ2X15_MASK GENMASK_32(15, 0) 4181 #define CSR_ACSMDDRADRX15X0X15_LSB 0 4182 #define CSR_ACSMDDRADRX15X0X15_MASK GENMASK_32(15, 0) 4183 /* CSR_ACSMSEQ2X16 */ 4184 #define CSR_ACSMSEQ2X16_LSB 0 4185 #define CSR_ACSMSEQ2X16_MASK GENMASK_32(15, 0) 4186 #define CSR_ACSMDDRADRX15X0X16_LSB 0 4187 #define CSR_ACSMDDRADRX15X0X16_MASK GENMASK_32(15, 0) 4188 /* CSR_ACSMSEQ2X17 */ 4189 #define CSR_ACSMSEQ2X17_LSB 0 4190 #define CSR_ACSMSEQ2X17_MASK GENMASK_32(15, 0) 4191 #define CSR_ACSMDDRADRX15X0X17_LSB 0 4192 #define CSR_ACSMDDRADRX15X0X17_MASK GENMASK_32(15, 0) 4193 /* CSR_ACSMSEQ2X18 */ 4194 #define CSR_ACSMSEQ2X18_LSB 0 4195 #define CSR_ACSMSEQ2X18_MASK GENMASK_32(15, 0) 4196 #define CSR_ACSMDDRADRX15X0X18_LSB 0 4197 #define CSR_ACSMDDRADRX15X0X18_MASK GENMASK_32(15, 0) 4198 /* CSR_ACSMSEQ2X19 */ 4199 #define CSR_ACSMSEQ2X19_LSB 0 4200 #define CSR_ACSMSEQ2X19_MASK GENMASK_32(15, 0) 4201 #define CSR_ACSMDDRADRX15X0X19_LSB 0 4202 #define CSR_ACSMDDRADRX15X0X19_MASK GENMASK_32(15, 0) 4203 /* CSR_ACSMSEQ2X20 */ 4204 #define CSR_ACSMSEQ2X20_LSB 0 4205 #define CSR_ACSMSEQ2X20_MASK GENMASK_32(15, 0) 4206 #define CSR_ACSMDDRADRX15X0X20_LSB 0 4207 #define CSR_ACSMDDRADRX15X0X20_MASK GENMASK_32(15, 0) 4208 /* CSR_ACSMSEQ2X21 */ 4209 #define CSR_ACSMSEQ2X21_LSB 0 4210 #define CSR_ACSMSEQ2X21_MASK GENMASK_32(15, 0) 4211 #define CSR_ACSMDDRADRX15X0X21_LSB 0 4212 #define CSR_ACSMDDRADRX15X0X21_MASK GENMASK_32(15, 0) 4213 /* CSR_ACSMSEQ2X22 */ 4214 #define CSR_ACSMSEQ2X22_LSB 0 4215 #define CSR_ACSMSEQ2X22_MASK GENMASK_32(15, 0) 4216 #define CSR_ACSMDDRADRX15X0X22_LSB 0 4217 #define CSR_ACSMDDRADRX15X0X22_MASK GENMASK_32(15, 0) 4218 /* CSR_ACSMSEQ2X23 */ 4219 #define CSR_ACSMSEQ2X23_LSB 0 4220 #define CSR_ACSMSEQ2X23_MASK GENMASK_32(15, 0) 4221 #define CSR_ACSMDDRADRX15X0X23_LSB 0 4222 #define CSR_ACSMDDRADRX15X0X23_MASK GENMASK_32(15, 0) 4223 /* CSR_ACSMSEQ2X24 */ 4224 #define CSR_ACSMSEQ2X24_LSB 0 4225 #define CSR_ACSMSEQ2X24_MASK GENMASK_32(15, 0) 4226 #define CSR_ACSMDDRADRX15X0X24_LSB 0 4227 #define CSR_ACSMDDRADRX15X0X24_MASK GENMASK_32(15, 0) 4228 /* CSR_ACSMSEQ2X25 */ 4229 #define CSR_ACSMSEQ2X25_LSB 0 4230 #define CSR_ACSMSEQ2X25_MASK GENMASK_32(15, 0) 4231 #define CSR_ACSMDDRADRX15X0X25_LSB 0 4232 #define CSR_ACSMDDRADRX15X0X25_MASK GENMASK_32(15, 0) 4233 /* CSR_ACSMSEQ2X26 */ 4234 #define CSR_ACSMSEQ2X26_LSB 0 4235 #define CSR_ACSMSEQ2X26_MASK GENMASK_32(15, 0) 4236 #define CSR_ACSMDDRADRX15X0X26_LSB 0 4237 #define CSR_ACSMDDRADRX15X0X26_MASK GENMASK_32(15, 0) 4238 /* CSR_ACSMSEQ2X27 */ 4239 #define CSR_ACSMSEQ2X27_LSB 0 4240 #define CSR_ACSMSEQ2X27_MASK GENMASK_32(15, 0) 4241 #define CSR_ACSMDDRADRX15X0X27_LSB 0 4242 #define CSR_ACSMDDRADRX15X0X27_MASK GENMASK_32(15, 0) 4243 /* CSR_ACSMSEQ2X28 */ 4244 #define CSR_ACSMSEQ2X28_LSB 0 4245 #define CSR_ACSMSEQ2X28_MASK GENMASK_32(15, 0) 4246 #define CSR_ACSMDDRADRX15X0X28_LSB 0 4247 #define CSR_ACSMDDRADRX15X0X28_MASK GENMASK_32(15, 0) 4248 /* CSR_ACSMSEQ2X29 */ 4249 #define CSR_ACSMSEQ2X29_LSB 0 4250 #define CSR_ACSMSEQ2X29_MASK GENMASK_32(15, 0) 4251 #define CSR_ACSMDDRADRX15X0X29_LSB 0 4252 #define CSR_ACSMDDRADRX15X0X29_MASK GENMASK_32(15, 0) 4253 /* CSR_ACSMSEQ2X30 */ 4254 #define CSR_ACSMSEQ2X30_LSB 0 4255 #define CSR_ACSMSEQ2X30_MASK GENMASK_32(15, 0) 4256 #define CSR_ACSMDDRADRX15X0X30_LSB 0 4257 #define CSR_ACSMDDRADRX15X0X30_MASK GENMASK_32(15, 0) 4258 /* CSR_ACSMSEQ2X31 */ 4259 #define CSR_ACSMSEQ2X31_LSB 0 4260 #define CSR_ACSMSEQ2X31_MASK GENMASK_32(15, 0) 4261 #define CSR_ACSMDDRADRX15X0X31_LSB 0 4262 #define CSR_ACSMDDRADRX15X0X31_MASK GENMASK_32(15, 0) 4263 /* CSR_ACSMSEQ3X0 */ 4264 #define CSR_ACSMSEQ3X0_LSB 0 4265 #define CSR_ACSMSEQ3X0_MASK GENMASK_32(15, 0) 4266 #define CSR_ACSMCMDREPCNT0_LSB 0 4267 #define CSR_ACSMCMDREPCNT0_MASK GENMASK_32(7, 0) 4268 #define CSR_ACSMADRADV0_LSB 8 4269 #define CSR_ACSMADRADV0_MASK GENMASK_32(9, 8) 4270 #define CSR_ACSMBNKADV0_LSB 10 4271 #define CSR_ACSMBNKADV0_MASK GENMASK_32(11, 10) 4272 #define CSR_ACSMADRSELLOAD0_LSB 12 4273 #define CSR_ACSMADRSELLOAD0_MASK GENMASK_32(13, 12) 4274 #define CSR_ACSMBNKSELLOAD0_LSB 14 4275 #define CSR_ACSMBNKSELLOAD0_MASK BIT(14) 4276 #define CSR_ACSMLONGBUBBLE0_LSB 15 4277 #define CSR_ACSMLONGBUBBLE0_MASK BIT(15) 4278 /* CSR_ACSMSEQ3X1 */ 4279 #define CSR_ACSMSEQ3X1_LSB 0 4280 #define CSR_ACSMSEQ3X1_MASK GENMASK_32(15, 0) 4281 #define CSR_ACSMCMDREPCNT1_LSB 0 4282 #define CSR_ACSMCMDREPCNT1_MASK GENMASK_32(7, 0) 4283 #define CSR_ACSMADRADV1_LSB 8 4284 #define CSR_ACSMADRADV1_MASK GENMASK_32(9, 8) 4285 #define CSR_ACSMBNKADV1_LSB 10 4286 #define CSR_ACSMBNKADV1_MASK GENMASK_32(11, 10) 4287 #define CSR_ACSMADRSELLOAD1_LSB 12 4288 #define CSR_ACSMADRSELLOAD1_MASK GENMASK_32(13, 12) 4289 #define CSR_ACSMBNKSELLOAD1_LSB 14 4290 #define CSR_ACSMBNKSELLOAD1_MASK BIT(14) 4291 #define CSR_ACSMLONGBUBBLE1_LSB 15 4292 #define CSR_ACSMLONGBUBBLE1_MASK BIT(15) 4293 /* CSR_ACSMSEQ3X2 */ 4294 #define CSR_ACSMSEQ3X2_LSB 0 4295 #define CSR_ACSMSEQ3X2_MASK GENMASK_32(15, 0) 4296 #define CSR_ACSMCMDREPCNT2_LSB 0 4297 #define CSR_ACSMCMDREPCNT2_MASK GENMASK_32(7, 0) 4298 #define CSR_ACSMADRADV2_LSB 8 4299 #define CSR_ACSMADRADV2_MASK GENMASK_32(9, 8) 4300 #define CSR_ACSMBNKADV2_LSB 10 4301 #define CSR_ACSMBNKADV2_MASK GENMASK_32(11, 10) 4302 #define CSR_ACSMADRSELLOAD2_LSB 12 4303 #define CSR_ACSMADRSELLOAD2_MASK GENMASK_32(13, 12) 4304 #define CSR_ACSMBNKSELLOAD2_LSB 14 4305 #define CSR_ACSMBNKSELLOAD2_MASK BIT(14) 4306 #define CSR_ACSMLONGBUBBLE2_LSB 15 4307 #define CSR_ACSMLONGBUBBLE2_MASK BIT(15) 4308 /* CSR_ACSMSEQ3X3 */ 4309 #define CSR_ACSMSEQ3X3_LSB 0 4310 #define CSR_ACSMSEQ3X3_MASK GENMASK_32(15, 0) 4311 #define CSR_ACSMCMDREPCNT3_LSB 0 4312 #define CSR_ACSMCMDREPCNT3_MASK GENMASK_32(7, 0) 4313 #define CSR_ACSMADRADV3_LSB 8 4314 #define CSR_ACSMADRADV3_MASK GENMASK_32(9, 8) 4315 #define CSR_ACSMBNKADV3_LSB 10 4316 #define CSR_ACSMBNKADV3_MASK GENMASK_32(11, 10) 4317 #define CSR_ACSMADRSELLOAD3_LSB 12 4318 #define CSR_ACSMADRSELLOAD3_MASK GENMASK_32(13, 12) 4319 #define CSR_ACSMBNKSELLOAD3_LSB 14 4320 #define CSR_ACSMBNKSELLOAD3_MASK BIT(14) 4321 #define CSR_ACSMLONGBUBBLE3_LSB 15 4322 #define CSR_ACSMLONGBUBBLE3_MASK BIT(15) 4323 /* CSR_ACSMSEQ3X4 */ 4324 #define CSR_ACSMSEQ3X4_LSB 0 4325 #define CSR_ACSMSEQ3X4_MASK GENMASK_32(15, 0) 4326 #define CSR_ACSMCMDREPCNT4_LSB 0 4327 #define CSR_ACSMCMDREPCNT4_MASK GENMASK_32(7, 0) 4328 #define CSR_ACSMADRADV4_LSB 8 4329 #define CSR_ACSMADRADV4_MASK GENMASK_32(9, 8) 4330 #define CSR_ACSMBNKADV4_LSB 10 4331 #define CSR_ACSMBNKADV4_MASK GENMASK_32(11, 10) 4332 #define CSR_ACSMADRSELLOAD4_LSB 12 4333 #define CSR_ACSMADRSELLOAD4_MASK GENMASK_32(13, 12) 4334 #define CSR_ACSMBNKSELLOAD4_LSB 14 4335 #define CSR_ACSMBNKSELLOAD4_MASK BIT(14) 4336 #define CSR_ACSMLONGBUBBLE4_LSB 15 4337 #define CSR_ACSMLONGBUBBLE4_MASK BIT(15) 4338 /* CSR_ACSMSEQ3X5 */ 4339 #define CSR_ACSMSEQ3X5_LSB 0 4340 #define CSR_ACSMSEQ3X5_MASK GENMASK_32(15, 0) 4341 #define CSR_ACSMCMDREPCNT5_LSB 0 4342 #define CSR_ACSMCMDREPCNT5_MASK GENMASK_32(7, 0) 4343 #define CSR_ACSMADRADV5_LSB 8 4344 #define CSR_ACSMADRADV5_MASK GENMASK_32(9, 8) 4345 #define CSR_ACSMBNKADV5_LSB 10 4346 #define CSR_ACSMBNKADV5_MASK GENMASK_32(11, 10) 4347 #define CSR_ACSMADRSELLOAD5_LSB 12 4348 #define CSR_ACSMADRSELLOAD5_MASK GENMASK_32(13, 12) 4349 #define CSR_ACSMBNKSELLOAD5_LSB 14 4350 #define CSR_ACSMBNKSELLOAD5_MASK BIT(14) 4351 #define CSR_ACSMLONGBUBBLE5_LSB 15 4352 #define CSR_ACSMLONGBUBBLE5_MASK BIT(15) 4353 /* CSR_ACSMSEQ3X6 */ 4354 #define CSR_ACSMSEQ3X6_LSB 0 4355 #define CSR_ACSMSEQ3X6_MASK GENMASK_32(15, 0) 4356 #define CSR_ACSMCMDREPCNT6_LSB 0 4357 #define CSR_ACSMCMDREPCNT6_MASK GENMASK_32(7, 0) 4358 #define CSR_ACSMADRADV6_LSB 8 4359 #define CSR_ACSMADRADV6_MASK GENMASK_32(9, 8) 4360 #define CSR_ACSMBNKADV6_LSB 10 4361 #define CSR_ACSMBNKADV6_MASK GENMASK_32(11, 10) 4362 #define CSR_ACSMADRSELLOAD6_LSB 12 4363 #define CSR_ACSMADRSELLOAD6_MASK GENMASK_32(13, 12) 4364 #define CSR_ACSMBNKSELLOAD6_LSB 14 4365 #define CSR_ACSMBNKSELLOAD6_MASK BIT(14) 4366 #define CSR_ACSMLONGBUBBLE6_LSB 15 4367 #define CSR_ACSMLONGBUBBLE6_MASK BIT(15) 4368 /* CSR_ACSMSEQ3X7 */ 4369 #define CSR_ACSMSEQ3X7_LSB 0 4370 #define CSR_ACSMSEQ3X7_MASK GENMASK_32(15, 0) 4371 #define CSR_ACSMCMDREPCNT7_LSB 0 4372 #define CSR_ACSMCMDREPCNT7_MASK GENMASK_32(7, 0) 4373 #define CSR_ACSMADRADV7_LSB 8 4374 #define CSR_ACSMADRADV7_MASK GENMASK_32(9, 8) 4375 #define CSR_ACSMBNKADV7_LSB 10 4376 #define CSR_ACSMBNKADV7_MASK GENMASK_32(11, 10) 4377 #define CSR_ACSMADRSELLOAD7_LSB 12 4378 #define CSR_ACSMADRSELLOAD7_MASK GENMASK_32(13, 12) 4379 #define CSR_ACSMBNKSELLOAD7_LSB 14 4380 #define CSR_ACSMBNKSELLOAD7_MASK BIT(14) 4381 #define CSR_ACSMLONGBUBBLE7_LSB 15 4382 #define CSR_ACSMLONGBUBBLE7_MASK BIT(15) 4383 /* CSR_ACSMSEQ3X8 */ 4384 #define CSR_ACSMSEQ3X8_LSB 0 4385 #define CSR_ACSMSEQ3X8_MASK GENMASK_32(15, 0) 4386 #define CSR_ACSMCMDREPCNT8_LSB 0 4387 #define CSR_ACSMCMDREPCNT8_MASK GENMASK_32(7, 0) 4388 #define CSR_ACSMADRADV8_LSB 8 4389 #define CSR_ACSMADRADV8_MASK GENMASK_32(9, 8) 4390 #define CSR_ACSMBNKADV8_LSB 10 4391 #define CSR_ACSMBNKADV8_MASK GENMASK_32(11, 10) 4392 #define CSR_ACSMADRSELLOAD8_LSB 12 4393 #define CSR_ACSMADRSELLOAD8_MASK GENMASK_32(13, 12) 4394 #define CSR_ACSMBNKSELLOAD8_LSB 14 4395 #define CSR_ACSMBNKSELLOAD8_MASK BIT(14) 4396 #define CSR_ACSMLONGBUBBLE8_LSB 15 4397 #define CSR_ACSMLONGBUBBLE8_MASK BIT(15) 4398 /* CSR_ACSMSEQ3X9 */ 4399 #define CSR_ACSMSEQ3X9_LSB 0 4400 #define CSR_ACSMSEQ3X9_MASK GENMASK_32(15, 0) 4401 #define CSR_ACSMCMDREPCNT9_LSB 0 4402 #define CSR_ACSMCMDREPCNT9_MASK GENMASK_32(7, 0) 4403 #define CSR_ACSMADRADV9_LSB 8 4404 #define CSR_ACSMADRADV9_MASK GENMASK_32(9, 8) 4405 #define CSR_ACSMBNKADV9_LSB 10 4406 #define CSR_ACSMBNKADV9_MASK GENMASK_32(11, 10) 4407 #define CSR_ACSMADRSELLOAD9_LSB 12 4408 #define CSR_ACSMADRSELLOAD9_MASK GENMASK_32(13, 12) 4409 #define CSR_ACSMBNKSELLOAD9_LSB 14 4410 #define CSR_ACSMBNKSELLOAD9_MASK BIT(14) 4411 #define CSR_ACSMLONGBUBBLE9_LSB 15 4412 #define CSR_ACSMLONGBUBBLE9_MASK BIT(15) 4413 /* CSR_ACSMSEQ3X10 */ 4414 #define CSR_ACSMSEQ3X10_LSB 0 4415 #define CSR_ACSMSEQ3X10_MASK GENMASK_32(15, 0) 4416 #define CSR_ACSMCMDREPCNT10_LSB 0 4417 #define CSR_ACSMCMDREPCNT10_MASK GENMASK_32(7, 0) 4418 #define CSR_ACSMADRADV10_LSB 8 4419 #define CSR_ACSMADRADV10_MASK GENMASK_32(9, 8) 4420 #define CSR_ACSMBNKADV10_LSB 10 4421 #define CSR_ACSMBNKADV10_MASK GENMASK_32(11, 10) 4422 #define CSR_ACSMADRSELLOAD10_LSB 12 4423 #define CSR_ACSMADRSELLOAD10_MASK GENMASK_32(13, 12) 4424 #define CSR_ACSMBNKSELLOAD10_LSB 14 4425 #define CSR_ACSMBNKSELLOAD10_MASK BIT(14) 4426 #define CSR_ACSMLONGBUBBLE10_LSB 15 4427 #define CSR_ACSMLONGBUBBLE10_MASK BIT(15) 4428 /* CSR_ACSMSEQ3X11 */ 4429 #define CSR_ACSMSEQ3X11_LSB 0 4430 #define CSR_ACSMSEQ3X11_MASK GENMASK_32(15, 0) 4431 #define CSR_ACSMCMDREPCNT11_LSB 0 4432 #define CSR_ACSMCMDREPCNT11_MASK GENMASK_32(7, 0) 4433 #define CSR_ACSMADRADV11_LSB 8 4434 #define CSR_ACSMADRADV11_MASK GENMASK_32(9, 8) 4435 #define CSR_ACSMBNKADV11_LSB 10 4436 #define CSR_ACSMBNKADV11_MASK GENMASK_32(11, 10) 4437 #define CSR_ACSMADRSELLOAD11_LSB 12 4438 #define CSR_ACSMADRSELLOAD11_MASK GENMASK_32(13, 12) 4439 #define CSR_ACSMBNKSELLOAD11_LSB 14 4440 #define CSR_ACSMBNKSELLOAD11_MASK BIT(14) 4441 #define CSR_ACSMLONGBUBBLE11_LSB 15 4442 #define CSR_ACSMLONGBUBBLE11_MASK BIT(15) 4443 /* CSR_ACSMSEQ3X12 */ 4444 #define CSR_ACSMSEQ3X12_LSB 0 4445 #define CSR_ACSMSEQ3X12_MASK GENMASK_32(15, 0) 4446 #define CSR_ACSMCMDREPCNT12_LSB 0 4447 #define CSR_ACSMCMDREPCNT12_MASK GENMASK_32(7, 0) 4448 #define CSR_ACSMADRADV12_LSB 8 4449 #define CSR_ACSMADRADV12_MASK GENMASK_32(9, 8) 4450 #define CSR_ACSMBNKADV12_LSB 10 4451 #define CSR_ACSMBNKADV12_MASK GENMASK_32(11, 10) 4452 #define CSR_ACSMADRSELLOAD12_LSB 12 4453 #define CSR_ACSMADRSELLOAD12_MASK GENMASK_32(13, 12) 4454 #define CSR_ACSMBNKSELLOAD12_LSB 14 4455 #define CSR_ACSMBNKSELLOAD12_MASK BIT(14) 4456 #define CSR_ACSMLONGBUBBLE12_LSB 15 4457 #define CSR_ACSMLONGBUBBLE12_MASK BIT(15) 4458 /* CSR_ACSMSEQ3X13 */ 4459 #define CSR_ACSMSEQ3X13_LSB 0 4460 #define CSR_ACSMSEQ3X13_MASK GENMASK_32(15, 0) 4461 #define CSR_ACSMCMDREPCNT13_LSB 0 4462 #define CSR_ACSMCMDREPCNT13_MASK GENMASK_32(7, 0) 4463 #define CSR_ACSMADRADV13_LSB 8 4464 #define CSR_ACSMADRADV13_MASK GENMASK_32(9, 8) 4465 #define CSR_ACSMBNKADV13_LSB 10 4466 #define CSR_ACSMBNKADV13_MASK GENMASK_32(11, 10) 4467 #define CSR_ACSMADRSELLOAD13_LSB 12 4468 #define CSR_ACSMADRSELLOAD13_MASK GENMASK_32(13, 12) 4469 #define CSR_ACSMBNKSELLOAD13_LSB 14 4470 #define CSR_ACSMBNKSELLOAD13_MASK BIT(14) 4471 #define CSR_ACSMLONGBUBBLE13_LSB 15 4472 #define CSR_ACSMLONGBUBBLE13_MASK BIT(15) 4473 /* CSR_ACSMSEQ3X14 */ 4474 #define CSR_ACSMSEQ3X14_LSB 0 4475 #define CSR_ACSMSEQ3X14_MASK GENMASK_32(15, 0) 4476 #define CSR_ACSMCMDREPCNT14_LSB 0 4477 #define CSR_ACSMCMDREPCNT14_MASK GENMASK_32(7, 0) 4478 #define CSR_ACSMADRADV14_LSB 8 4479 #define CSR_ACSMADRADV14_MASK GENMASK_32(9, 8) 4480 #define CSR_ACSMBNKADV14_LSB 10 4481 #define CSR_ACSMBNKADV14_MASK GENMASK_32(11, 10) 4482 #define CSR_ACSMADRSELLOAD14_LSB 12 4483 #define CSR_ACSMADRSELLOAD14_MASK GENMASK_32(13, 12) 4484 #define CSR_ACSMBNKSELLOAD14_LSB 14 4485 #define CSR_ACSMBNKSELLOAD14_MASK BIT(14) 4486 #define CSR_ACSMLONGBUBBLE14_LSB 15 4487 #define CSR_ACSMLONGBUBBLE14_MASK BIT(15) 4488 /* CSR_ACSMSEQ3X15 */ 4489 #define CSR_ACSMSEQ3X15_LSB 0 4490 #define CSR_ACSMSEQ3X15_MASK GENMASK_32(15, 0) 4491 #define CSR_ACSMCMDREPCNT15_LSB 0 4492 #define CSR_ACSMCMDREPCNT15_MASK GENMASK_32(7, 0) 4493 #define CSR_ACSMADRADV15_LSB 8 4494 #define CSR_ACSMADRADV15_MASK GENMASK_32(9, 8) 4495 #define CSR_ACSMBNKADV15_LSB 10 4496 #define CSR_ACSMBNKADV15_MASK GENMASK_32(11, 10) 4497 #define CSR_ACSMADRSELLOAD15_LSB 12 4498 #define CSR_ACSMADRSELLOAD15_MASK GENMASK_32(13, 12) 4499 #define CSR_ACSMBNKSELLOAD15_LSB 14 4500 #define CSR_ACSMBNKSELLOAD15_MASK BIT(14) 4501 #define CSR_ACSMLONGBUBBLE15_LSB 15 4502 #define CSR_ACSMLONGBUBBLE15_MASK BIT(15) 4503 /* CSR_ACSMSEQ3X16 */ 4504 #define CSR_ACSMSEQ3X16_LSB 0 4505 #define CSR_ACSMSEQ3X16_MASK GENMASK_32(15, 0) 4506 #define CSR_ACSMCMDREPCNT16_LSB 0 4507 #define CSR_ACSMCMDREPCNT16_MASK GENMASK_32(7, 0) 4508 #define CSR_ACSMADRADV16_LSB 8 4509 #define CSR_ACSMADRADV16_MASK GENMASK_32(9, 8) 4510 #define CSR_ACSMBNKADV16_LSB 10 4511 #define CSR_ACSMBNKADV16_MASK GENMASK_32(11, 10) 4512 #define CSR_ACSMADRSELLOAD16_LSB 12 4513 #define CSR_ACSMADRSELLOAD16_MASK GENMASK_32(13, 12) 4514 #define CSR_ACSMBNKSELLOAD16_LSB 14 4515 #define CSR_ACSMBNKSELLOAD16_MASK BIT(14) 4516 #define CSR_ACSMLONGBUBBLE16_LSB 15 4517 #define CSR_ACSMLONGBUBBLE16_MASK BIT(15) 4518 /* CSR_ACSMSEQ3X17 */ 4519 #define CSR_ACSMSEQ3X17_LSB 0 4520 #define CSR_ACSMSEQ3X17_MASK GENMASK_32(15, 0) 4521 #define CSR_ACSMCMDREPCNT17_LSB 0 4522 #define CSR_ACSMCMDREPCNT17_MASK GENMASK_32(7, 0) 4523 #define CSR_ACSMADRADV17_LSB 8 4524 #define CSR_ACSMADRADV17_MASK GENMASK_32(9, 8) 4525 #define CSR_ACSMBNKADV17_LSB 10 4526 #define CSR_ACSMBNKADV17_MASK GENMASK_32(11, 10) 4527 #define CSR_ACSMADRSELLOAD17_LSB 12 4528 #define CSR_ACSMADRSELLOAD17_MASK GENMASK_32(13, 12) 4529 #define CSR_ACSMBNKSELLOAD17_LSB 14 4530 #define CSR_ACSMBNKSELLOAD17_MASK BIT(14) 4531 #define CSR_ACSMLONGBUBBLE17_LSB 15 4532 #define CSR_ACSMLONGBUBBLE17_MASK BIT(15) 4533 /* CSR_ACSMSEQ3X18 */ 4534 #define CSR_ACSMSEQ3X18_LSB 0 4535 #define CSR_ACSMSEQ3X18_MASK GENMASK_32(15, 0) 4536 #define CSR_ACSMCMDREPCNT18_LSB 0 4537 #define CSR_ACSMCMDREPCNT18_MASK GENMASK_32(7, 0) 4538 #define CSR_ACSMADRADV18_LSB 8 4539 #define CSR_ACSMADRADV18_MASK GENMASK_32(9, 8) 4540 #define CSR_ACSMBNKADV18_LSB 10 4541 #define CSR_ACSMBNKADV18_MASK GENMASK_32(11, 10) 4542 #define CSR_ACSMADRSELLOAD18_LSB 12 4543 #define CSR_ACSMADRSELLOAD18_MASK GENMASK_32(13, 12) 4544 #define CSR_ACSMBNKSELLOAD18_LSB 14 4545 #define CSR_ACSMBNKSELLOAD18_MASK BIT(14) 4546 #define CSR_ACSMLONGBUBBLE18_LSB 15 4547 #define CSR_ACSMLONGBUBBLE18_MASK BIT(15) 4548 /* CSR_ACSMSEQ3X19 */ 4549 #define CSR_ACSMSEQ3X19_LSB 0 4550 #define CSR_ACSMSEQ3X19_MASK GENMASK_32(15, 0) 4551 #define CSR_ACSMCMDREPCNT19_LSB 0 4552 #define CSR_ACSMCMDREPCNT19_MASK GENMASK_32(7, 0) 4553 #define CSR_ACSMADRADV19_LSB 8 4554 #define CSR_ACSMADRADV19_MASK GENMASK_32(9, 8) 4555 #define CSR_ACSMBNKADV19_LSB 10 4556 #define CSR_ACSMBNKADV19_MASK GENMASK_32(11, 10) 4557 #define CSR_ACSMADRSELLOAD19_LSB 12 4558 #define CSR_ACSMADRSELLOAD19_MASK GENMASK_32(13, 12) 4559 #define CSR_ACSMBNKSELLOAD19_LSB 14 4560 #define CSR_ACSMBNKSELLOAD19_MASK BIT(14) 4561 #define CSR_ACSMLONGBUBBLE19_LSB 15 4562 #define CSR_ACSMLONGBUBBLE19_MASK BIT(15) 4563 /* CSR_ACSMSEQ3X20 */ 4564 #define CSR_ACSMSEQ3X20_LSB 0 4565 #define CSR_ACSMSEQ3X20_MASK GENMASK_32(15, 0) 4566 #define CSR_ACSMCMDREPCNT20_LSB 0 4567 #define CSR_ACSMCMDREPCNT20_MASK GENMASK_32(7, 0) 4568 #define CSR_ACSMADRADV20_LSB 8 4569 #define CSR_ACSMADRADV20_MASK GENMASK_32(9, 8) 4570 #define CSR_ACSMBNKADV20_LSB 10 4571 #define CSR_ACSMBNKADV20_MASK GENMASK_32(11, 10) 4572 #define CSR_ACSMADRSELLOAD20_LSB 12 4573 #define CSR_ACSMADRSELLOAD20_MASK GENMASK_32(13, 12) 4574 #define CSR_ACSMBNKSELLOAD20_LSB 14 4575 #define CSR_ACSMBNKSELLOAD20_MASK BIT(14) 4576 #define CSR_ACSMLONGBUBBLE20_LSB 15 4577 #define CSR_ACSMLONGBUBBLE20_MASK BIT(15) 4578 /* CSR_ACSMSEQ3X21 */ 4579 #define CSR_ACSMSEQ3X21_LSB 0 4580 #define CSR_ACSMSEQ3X21_MASK GENMASK_32(15, 0) 4581 #define CSR_ACSMCMDREPCNT21_LSB 0 4582 #define CSR_ACSMCMDREPCNT21_MASK GENMASK_32(7, 0) 4583 #define CSR_ACSMADRADV21_LSB 8 4584 #define CSR_ACSMADRADV21_MASK GENMASK_32(9, 8) 4585 #define CSR_ACSMBNKADV21_LSB 10 4586 #define CSR_ACSMBNKADV21_MASK GENMASK_32(11, 10) 4587 #define CSR_ACSMADRSELLOAD21_LSB 12 4588 #define CSR_ACSMADRSELLOAD21_MASK GENMASK_32(13, 12) 4589 #define CSR_ACSMBNKSELLOAD21_LSB 14 4590 #define CSR_ACSMBNKSELLOAD21_MASK BIT(14) 4591 #define CSR_ACSMLONGBUBBLE21_LSB 15 4592 #define CSR_ACSMLONGBUBBLE21_MASK BIT(15) 4593 /* CSR_ACSMSEQ3X22 */ 4594 #define CSR_ACSMSEQ3X22_LSB 0 4595 #define CSR_ACSMSEQ3X22_MASK GENMASK_32(15, 0) 4596 #define CSR_ACSMCMDREPCNT22_LSB 0 4597 #define CSR_ACSMCMDREPCNT22_MASK GENMASK_32(7, 0) 4598 #define CSR_ACSMADRADV22_LSB 8 4599 #define CSR_ACSMADRADV22_MASK GENMASK_32(9, 8) 4600 #define CSR_ACSMBNKADV22_LSB 10 4601 #define CSR_ACSMBNKADV22_MASK GENMASK_32(11, 10) 4602 #define CSR_ACSMADRSELLOAD22_LSB 12 4603 #define CSR_ACSMADRSELLOAD22_MASK GENMASK_32(13, 12) 4604 #define CSR_ACSMBNKSELLOAD22_LSB 14 4605 #define CSR_ACSMBNKSELLOAD22_MASK BIT(14) 4606 #define CSR_ACSMLONGBUBBLE22_LSB 15 4607 #define CSR_ACSMLONGBUBBLE22_MASK BIT(15) 4608 /* CSR_ACSMSEQ3X23 */ 4609 #define CSR_ACSMSEQ3X23_LSB 0 4610 #define CSR_ACSMSEQ3X23_MASK GENMASK_32(15, 0) 4611 #define CSR_ACSMCMDREPCNT23_LSB 0 4612 #define CSR_ACSMCMDREPCNT23_MASK GENMASK_32(7, 0) 4613 #define CSR_ACSMADRADV23_LSB 8 4614 #define CSR_ACSMADRADV23_MASK GENMASK_32(9, 8) 4615 #define CSR_ACSMBNKADV23_LSB 10 4616 #define CSR_ACSMBNKADV23_MASK GENMASK_32(11, 10) 4617 #define CSR_ACSMADRSELLOAD23_LSB 12 4618 #define CSR_ACSMADRSELLOAD23_MASK GENMASK_32(13, 12) 4619 #define CSR_ACSMBNKSELLOAD23_LSB 14 4620 #define CSR_ACSMBNKSELLOAD23_MASK BIT(14) 4621 #define CSR_ACSMLONGBUBBLE23_LSB 15 4622 #define CSR_ACSMLONGBUBBLE23_MASK BIT(15) 4623 /* CSR_ACSMSEQ3X24 */ 4624 #define CSR_ACSMSEQ3X24_LSB 0 4625 #define CSR_ACSMSEQ3X24_MASK GENMASK_32(15, 0) 4626 #define CSR_ACSMCMDREPCNT24_LSB 0 4627 #define CSR_ACSMCMDREPCNT24_MASK GENMASK_32(7, 0) 4628 #define CSR_ACSMADRADV24_LSB 8 4629 #define CSR_ACSMADRADV24_MASK GENMASK_32(9, 8) 4630 #define CSR_ACSMBNKADV24_LSB 10 4631 #define CSR_ACSMBNKADV24_MASK GENMASK_32(11, 10) 4632 #define CSR_ACSMADRSELLOAD24_LSB 12 4633 #define CSR_ACSMADRSELLOAD24_MASK GENMASK_32(13, 12) 4634 #define CSR_ACSMBNKSELLOAD24_LSB 14 4635 #define CSR_ACSMBNKSELLOAD24_MASK BIT(14) 4636 #define CSR_ACSMLONGBUBBLE24_LSB 15 4637 #define CSR_ACSMLONGBUBBLE24_MASK BIT(15) 4638 /* CSR_ACSMSEQ3X25 */ 4639 #define CSR_ACSMSEQ3X25_LSB 0 4640 #define CSR_ACSMSEQ3X25_MASK GENMASK_32(15, 0) 4641 #define CSR_ACSMCMDREPCNT25_LSB 0 4642 #define CSR_ACSMCMDREPCNT25_MASK GENMASK_32(7, 0) 4643 #define CSR_ACSMADRADV25_LSB 8 4644 #define CSR_ACSMADRADV25_MASK GENMASK_32(9, 8) 4645 #define CSR_ACSMBNKADV25_LSB 10 4646 #define CSR_ACSMBNKADV25_MASK GENMASK_32(11, 10) 4647 #define CSR_ACSMADRSELLOAD25_LSB 12 4648 #define CSR_ACSMADRSELLOAD25_MASK GENMASK_32(13, 12) 4649 #define CSR_ACSMBNKSELLOAD25_LSB 14 4650 #define CSR_ACSMBNKSELLOAD25_MASK BIT(14) 4651 #define CSR_ACSMLONGBUBBLE25_LSB 15 4652 #define CSR_ACSMLONGBUBBLE25_MASK BIT(15) 4653 /* CSR_ACSMSEQ3X26 */ 4654 #define CSR_ACSMSEQ3X26_LSB 0 4655 #define CSR_ACSMSEQ3X26_MASK GENMASK_32(15, 0) 4656 #define CSR_ACSMCMDREPCNT26_LSB 0 4657 #define CSR_ACSMCMDREPCNT26_MASK GENMASK_32(7, 0) 4658 #define CSR_ACSMADRADV26_LSB 8 4659 #define CSR_ACSMADRADV26_MASK GENMASK_32(9, 8) 4660 #define CSR_ACSMBNKADV26_LSB 10 4661 #define CSR_ACSMBNKADV26_MASK GENMASK_32(11, 10) 4662 #define CSR_ACSMADRSELLOAD26_LSB 12 4663 #define CSR_ACSMADRSELLOAD26_MASK GENMASK_32(13, 12) 4664 #define CSR_ACSMBNKSELLOAD26_LSB 14 4665 #define CSR_ACSMBNKSELLOAD26_MASK BIT(14) 4666 #define CSR_ACSMLONGBUBBLE26_LSB 15 4667 #define CSR_ACSMLONGBUBBLE26_MASK BIT(15) 4668 /* CSR_ACSMSEQ3X27 */ 4669 #define CSR_ACSMSEQ3X27_LSB 0 4670 #define CSR_ACSMSEQ3X27_MASK GENMASK_32(15, 0) 4671 #define CSR_ACSMCMDREPCNT27_LSB 0 4672 #define CSR_ACSMCMDREPCNT27_MASK GENMASK_32(7, 0) 4673 #define CSR_ACSMADRADV27_LSB 8 4674 #define CSR_ACSMADRADV27_MASK GENMASK_32(9, 8) 4675 #define CSR_ACSMBNKADV27_LSB 10 4676 #define CSR_ACSMBNKADV27_MASK GENMASK_32(11, 10) 4677 #define CSR_ACSMADRSELLOAD27_LSB 12 4678 #define CSR_ACSMADRSELLOAD27_MASK GENMASK_32(13, 12) 4679 #define CSR_ACSMBNKSELLOAD27_LSB 14 4680 #define CSR_ACSMBNKSELLOAD27_MASK BIT(14) 4681 #define CSR_ACSMLONGBUBBLE27_LSB 15 4682 #define CSR_ACSMLONGBUBBLE27_MASK BIT(15) 4683 /* CSR_ACSMSEQ3X28 */ 4684 #define CSR_ACSMSEQ3X28_LSB 0 4685 #define CSR_ACSMSEQ3X28_MASK GENMASK_32(15, 0) 4686 #define CSR_ACSMCMDREPCNT28_LSB 0 4687 #define CSR_ACSMCMDREPCNT28_MASK GENMASK_32(7, 0) 4688 #define CSR_ACSMADRADV28_LSB 8 4689 #define CSR_ACSMADRADV28_MASK GENMASK_32(9, 8) 4690 #define CSR_ACSMBNKADV28_LSB 10 4691 #define CSR_ACSMBNKADV28_MASK GENMASK_32(11, 10) 4692 #define CSR_ACSMADRSELLOAD28_LSB 12 4693 #define CSR_ACSMADRSELLOAD28_MASK GENMASK_32(13, 12) 4694 #define CSR_ACSMBNKSELLOAD28_LSB 14 4695 #define CSR_ACSMBNKSELLOAD28_MASK BIT(14) 4696 #define CSR_ACSMLONGBUBBLE28_LSB 15 4697 #define CSR_ACSMLONGBUBBLE28_MASK BIT(15) 4698 /* CSR_ACSMSEQ3X29 */ 4699 #define CSR_ACSMSEQ3X29_LSB 0 4700 #define CSR_ACSMSEQ3X29_MASK GENMASK_32(15, 0) 4701 #define CSR_ACSMCMDREPCNT29_LSB 0 4702 #define CSR_ACSMCMDREPCNT29_MASK GENMASK_32(7, 0) 4703 #define CSR_ACSMADRADV29_LSB 8 4704 #define CSR_ACSMADRADV29_MASK GENMASK_32(9, 8) 4705 #define CSR_ACSMBNKADV29_LSB 10 4706 #define CSR_ACSMBNKADV29_MASK GENMASK_32(11, 10) 4707 #define CSR_ACSMADRSELLOAD29_LSB 12 4708 #define CSR_ACSMADRSELLOAD29_MASK GENMASK_32(13, 12) 4709 #define CSR_ACSMBNKSELLOAD29_LSB 14 4710 #define CSR_ACSMBNKSELLOAD29_MASK BIT(14) 4711 #define CSR_ACSMLONGBUBBLE29_LSB 15 4712 #define CSR_ACSMLONGBUBBLE29_MASK BIT(15) 4713 /* CSR_ACSMSEQ3X30 */ 4714 #define CSR_ACSMSEQ3X30_LSB 0 4715 #define CSR_ACSMSEQ3X30_MASK GENMASK_32(15, 0) 4716 #define CSR_ACSMCMDREPCNT30_LSB 0 4717 #define CSR_ACSMCMDREPCNT30_MASK GENMASK_32(7, 0) 4718 #define CSR_ACSMADRADV30_LSB 8 4719 #define CSR_ACSMADRADV30_MASK GENMASK_32(9, 8) 4720 #define CSR_ACSMBNKADV30_LSB 10 4721 #define CSR_ACSMBNKADV30_MASK GENMASK_32(11, 10) 4722 #define CSR_ACSMADRSELLOAD30_LSB 12 4723 #define CSR_ACSMADRSELLOAD30_MASK GENMASK_32(13, 12) 4724 #define CSR_ACSMBNKSELLOAD30_LSB 14 4725 #define CSR_ACSMBNKSELLOAD30_MASK BIT(14) 4726 #define CSR_ACSMLONGBUBBLE30_LSB 15 4727 #define CSR_ACSMLONGBUBBLE30_MASK BIT(15) 4728 /* CSR_ACSMSEQ3X31 */ 4729 #define CSR_ACSMSEQ3X31_LSB 0 4730 #define CSR_ACSMSEQ3X31_MASK GENMASK_32(15, 0) 4731 #define CSR_ACSMCMDREPCNT31_LSB 0 4732 #define CSR_ACSMCMDREPCNT31_MASK GENMASK_32(7, 0) 4733 #define CSR_ACSMADRADV31_LSB 8 4734 #define CSR_ACSMADRADV31_MASK GENMASK_32(9, 8) 4735 #define CSR_ACSMBNKADV31_LSB 10 4736 #define CSR_ACSMBNKADV31_MASK GENMASK_32(11, 10) 4737 #define CSR_ACSMADRSELLOAD31_LSB 12 4738 #define CSR_ACSMADRSELLOAD31_MASK GENMASK_32(13, 12) 4739 #define CSR_ACSMBNKSELLOAD31_LSB 14 4740 #define CSR_ACSMBNKSELLOAD31_MASK BIT(14) 4741 #define CSR_ACSMLONGBUBBLE31_LSB 15 4742 #define CSR_ACSMLONGBUBBLE31_MASK BIT(15) 4743 /* CSR_ACSMPLAYBACK0X0 */ 4744 #define CSR_ACSMPLAYBACK0X0_LSB 0 4745 #define CSR_ACSMPLAYBACK0X0_MASK GENMASK_32(11, 0) 4746 /* CSR_ACSMPLAYBACK1X0 */ 4747 #define CSR_ACSMPLAYBACK1X0_LSB 0 4748 #define CSR_ACSMPLAYBACK1X0_MASK GENMASK_32(11, 0) 4749 /* CSR_ACSMPLAYBACK0X1 */ 4750 #define CSR_ACSMPLAYBACK0X1_LSB 0 4751 #define CSR_ACSMPLAYBACK0X1_MASK GENMASK_32(11, 0) 4752 /* CSR_ACSMPLAYBACK1X1 */ 4753 #define CSR_ACSMPLAYBACK1X1_LSB 0 4754 #define CSR_ACSMPLAYBACK1X1_MASK GENMASK_32(11, 0) 4755 /* CSR_ACSMPLAYBACK0X2 */ 4756 #define CSR_ACSMPLAYBACK0X2_LSB 0 4757 #define CSR_ACSMPLAYBACK0X2_MASK GENMASK_32(11, 0) 4758 /* CSR_ACSMPLAYBACK1X2 */ 4759 #define CSR_ACSMPLAYBACK1X2_LSB 0 4760 #define CSR_ACSMPLAYBACK1X2_MASK GENMASK_32(11, 0) 4761 /* CSR_ACSMPLAYBACK0X3 */ 4762 #define CSR_ACSMPLAYBACK0X3_LSB 0 4763 #define CSR_ACSMPLAYBACK0X3_MASK GENMASK_32(11, 0) 4764 /* CSR_ACSMPLAYBACK1X3 */ 4765 #define CSR_ACSMPLAYBACK1X3_LSB 0 4766 #define CSR_ACSMPLAYBACK1X3_MASK GENMASK_32(11, 0) 4767 /* CSR_ACSMPLAYBACK0X4 */ 4768 #define CSR_ACSMPLAYBACK0X4_LSB 0 4769 #define CSR_ACSMPLAYBACK0X4_MASK GENMASK_32(11, 0) 4770 /* CSR_ACSMPLAYBACK1X4 */ 4771 #define CSR_ACSMPLAYBACK1X4_LSB 0 4772 #define CSR_ACSMPLAYBACK1X4_MASK GENMASK_32(11, 0) 4773 /* CSR_ACSMPLAYBACK0X5 */ 4774 #define CSR_ACSMPLAYBACK0X5_LSB 0 4775 #define CSR_ACSMPLAYBACK0X5_MASK GENMASK_32(11, 0) 4776 /* CSR_ACSMPLAYBACK1X5 */ 4777 #define CSR_ACSMPLAYBACK1X5_LSB 0 4778 #define CSR_ACSMPLAYBACK1X5_MASK GENMASK_32(11, 0) 4779 /* CSR_ACSMPLAYBACK0X6 */ 4780 #define CSR_ACSMPLAYBACK0X6_LSB 0 4781 #define CSR_ACSMPLAYBACK0X6_MASK GENMASK_32(11, 0) 4782 /* CSR_ACSMPLAYBACK1X6 */ 4783 #define CSR_ACSMPLAYBACK1X6_LSB 0 4784 #define CSR_ACSMPLAYBACK1X6_MASK GENMASK_32(11, 0) 4785 /* CSR_ACSMPLAYBACK0X7 */ 4786 #define CSR_ACSMPLAYBACK0X7_LSB 0 4787 #define CSR_ACSMPLAYBACK0X7_MASK GENMASK_32(11, 0) 4788 /* CSR_ACSMPLAYBACK1X7 */ 4789 #define CSR_ACSMPLAYBACK1X7_LSB 0 4790 #define CSR_ACSMPLAYBACK1X7_MASK GENMASK_32(11, 0) 4791 /* CSR_ACSMPSTATEOVREN */ 4792 #define CSR_ACSMPSTATEOVREN_LSB 0 4793 #define CSR_ACSMPSTATEOVREN_MASK BIT(0) 4794 /* CSR_ACSMPSTATEOVRVAL */ 4795 #define CSR_ACSMPSTATEOVRVAL_LSB 0 4796 #define CSR_ACSMPSTATEOVRVAL_MASK GENMASK_32(3, 0) 4797 /* CSR_ACSMCTRL23 */ 4798 #define CSR_ACSMCTRL23_LSB 0 4799 #define CSR_ACSMCTRL23_MASK GENMASK_32(12, 0) 4800 #define CSR_ACSMCSMASK_LSB 0 4801 #define CSR_ACSMCSMASK_MASK GENMASK_32(7, 0) 4802 #define CSR_ACSMCSMODE_LSB 8 4803 #define CSR_ACSMCSMODE_MASK BIT(8) 4804 #define CSR_ACSMPARMASK_LSB 9 4805 #define CSR_ACSMPARMASK_MASK GENMASK_32(12, 9) 4806 /* CSR_ACSMCKEVAL */ 4807 #define CSR_ACSMCKEVAL_LSB 0 4808 #define CSR_ACSMCKEVAL_MASK GENMASK_32(3, 0) 4809 /* CSR_LOWSPEEDCLOCKDIVIDER */ 4810 #define CSR_LOWSPEEDCLOCKDIVIDER_LSB 0 4811 #define CSR_LOWSPEEDCLOCKDIVIDER_MASK GENMASK_32(5, 0) 4812 /* CSR_ACSMCSMAPCTRL0 */ 4813 #define CSR_ACSMCSMAPCTRL0_LSB 0 4814 #define CSR_ACSMCSMAPCTRL0_MASK GENMASK_32(14, 0) 4815 #define CSR_ACSMCSMAP0_LSB 0 4816 #define CSR_ACSMCSMAP0_MASK GENMASK_32(7, 0) 4817 #define CSR_ACSMDESTMAP0_LSB 8 4818 #define CSR_ACSMDESTMAP0_MASK GENMASK_32(11, 8) 4819 #define CSR_ACSMODTMAP0_LSB 12 4820 #define CSR_ACSMODTMAP0_MASK GENMASK_32(14, 12) 4821 /* CSR_ACSMCSMAPCTRL1 */ 4822 #define CSR_ACSMCSMAPCTRL1_LSB 0 4823 #define CSR_ACSMCSMAPCTRL1_MASK GENMASK_32(14, 0) 4824 #define CSR_ACSMCSMAP1_LSB 0 4825 #define CSR_ACSMCSMAP1_MASK GENMASK_32(7, 0) 4826 #define CSR_ACSMDESTMAP1_LSB 8 4827 #define CSR_ACSMDESTMAP1_MASK GENMASK_32(11, 8) 4828 #define CSR_ACSMODTMAP1_LSB 12 4829 #define CSR_ACSMODTMAP1_MASK GENMASK_32(14, 12) 4830 /* CSR_ACSMCSMAPCTRL2 */ 4831 #define CSR_ACSMCSMAPCTRL2_LSB 0 4832 #define CSR_ACSMCSMAPCTRL2_MASK GENMASK_32(14, 0) 4833 #define CSR_ACSMCSMAP2_LSB 0 4834 #define CSR_ACSMCSMAP2_MASK GENMASK_32(7, 0) 4835 #define CSR_ACSMDESTMAP2_LSB 8 4836 #define CSR_ACSMDESTMAP2_MASK GENMASK_32(11, 8) 4837 #define CSR_ACSMODTMAP2_LSB 12 4838 #define CSR_ACSMODTMAP2_MASK GENMASK_32(14, 12) 4839 /* CSR_ACSMCSMAPCTRL3 */ 4840 #define CSR_ACSMCSMAPCTRL3_LSB 0 4841 #define CSR_ACSMCSMAPCTRL3_MASK GENMASK_32(14, 0) 4842 #define CSR_ACSMCSMAP3_LSB 0 4843 #define CSR_ACSMCSMAP3_MASK GENMASK_32(7, 0) 4844 #define CSR_ACSMDESTMAP3_LSB 8 4845 #define CSR_ACSMDESTMAP3_MASK GENMASK_32(11, 8) 4846 #define CSR_ACSMODTMAP3_LSB 12 4847 #define CSR_ACSMODTMAP3_MASK GENMASK_32(14, 12) 4848 /* CSR_ACSMCSMAPCTRL4 */ 4849 #define CSR_ACSMCSMAPCTRL4_LSB 0 4850 #define CSR_ACSMCSMAPCTRL4_MASK GENMASK_32(14, 0) 4851 #define CSR_ACSMCSMAP4_LSB 0 4852 #define CSR_ACSMCSMAP4_MASK GENMASK_32(7, 0) 4853 #define CSR_ACSMDESTMAP4_LSB 8 4854 #define CSR_ACSMDESTMAP4_MASK GENMASK_32(11, 8) 4855 #define CSR_ACSMODTMAP4_LSB 12 4856 #define CSR_ACSMODTMAP4_MASK GENMASK_32(14, 12) 4857 /* CSR_ACSMCSMAPCTRL5 */ 4858 #define CSR_ACSMCSMAPCTRL5_LSB 0 4859 #define CSR_ACSMCSMAPCTRL5_MASK GENMASK_32(14, 0) 4860 #define CSR_ACSMCSMAP5_LSB 0 4861 #define CSR_ACSMCSMAP5_MASK GENMASK_32(7, 0) 4862 #define CSR_ACSMDESTMAP5_LSB 8 4863 #define CSR_ACSMDESTMAP5_MASK GENMASK_32(11, 8) 4864 #define CSR_ACSMODTMAP5_LSB 12 4865 #define CSR_ACSMODTMAP5_MASK GENMASK_32(14, 12) 4866 /* CSR_ACSMCSMAPCTRL6 */ 4867 #define CSR_ACSMCSMAPCTRL6_LSB 0 4868 #define CSR_ACSMCSMAPCTRL6_MASK GENMASK_32(14, 0) 4869 #define CSR_ACSMCSMAP6_LSB 0 4870 #define CSR_ACSMCSMAP6_MASK GENMASK_32(7, 0) 4871 #define CSR_ACSMDESTMAP6_LSB 8 4872 #define CSR_ACSMDESTMAP6_MASK GENMASK_32(11, 8) 4873 #define CSR_ACSMODTMAP6_LSB 12 4874 #define CSR_ACSMODTMAP6_MASK GENMASK_32(14, 12) 4875 /* CSR_ACSMCSMAPCTRL7 */ 4876 #define CSR_ACSMCSMAPCTRL7_LSB 0 4877 #define CSR_ACSMCSMAPCTRL7_MASK GENMASK_32(14, 0) 4878 #define CSR_ACSMCSMAP7_LSB 0 4879 #define CSR_ACSMCSMAP7_MASK GENMASK_32(7, 0) 4880 #define CSR_ACSMDESTMAP7_LSB 8 4881 #define CSR_ACSMDESTMAP7_MASK GENMASK_32(11, 8) 4882 #define CSR_ACSMODTMAP7_LSB 12 4883 #define CSR_ACSMODTMAP7_MASK GENMASK_32(14, 12) 4884 /* CSR_ACSMCSMAPCTRL8 */ 4885 #define CSR_ACSMCSMAPCTRL8_LSB 0 4886 #define CSR_ACSMCSMAPCTRL8_MASK GENMASK_32(14, 0) 4887 #define CSR_ACSMCSMAP8_LSB 0 4888 #define CSR_ACSMCSMAP8_MASK GENMASK_32(7, 0) 4889 #define CSR_ACSMDESTMAP8_LSB 8 4890 #define CSR_ACSMDESTMAP8_MASK GENMASK_32(11, 8) 4891 #define CSR_ACSMODTMAP8_LSB 12 4892 #define CSR_ACSMODTMAP8_MASK GENMASK_32(14, 12) 4893 /* CSR_ACSMCSMAPCTRL9 */ 4894 #define CSR_ACSMCSMAPCTRL9_LSB 0 4895 #define CSR_ACSMCSMAPCTRL9_MASK GENMASK_32(14, 0) 4896 #define CSR_ACSMCSMAP9_LSB 0 4897 #define CSR_ACSMCSMAP9_MASK GENMASK_32(7, 0) 4898 #define CSR_ACSMDESTMAP9_LSB 8 4899 #define CSR_ACSMDESTMAP9_MASK GENMASK_32(11, 8) 4900 #define CSR_ACSMODTMAP9_LSB 12 4901 #define CSR_ACSMODTMAP9_MASK GENMASK_32(14, 12) 4902 /* CSR_ACSMCSMAPCTRL10 */ 4903 #define CSR_ACSMCSMAPCTRL10_LSB 0 4904 #define CSR_ACSMCSMAPCTRL10_MASK GENMASK_32(14, 0) 4905 #define CSR_ACSMCSMAP10_LSB 0 4906 #define CSR_ACSMCSMAP10_MASK GENMASK_32(7, 0) 4907 #define CSR_ACSMDESTMAP10_LSB 8 4908 #define CSR_ACSMDESTMAP10_MASK GENMASK_32(11, 8) 4909 #define CSR_ACSMODTMAP10_LSB 12 4910 #define CSR_ACSMODTMAP10_MASK GENMASK_32(14, 12) 4911 /* CSR_ACSMCSMAPCTRL11 */ 4912 #define CSR_ACSMCSMAPCTRL11_LSB 0 4913 #define CSR_ACSMCSMAPCTRL11_MASK GENMASK_32(14, 0) 4914 #define CSR_ACSMCSMAP11_LSB 0 4915 #define CSR_ACSMCSMAP11_MASK GENMASK_32(7, 0) 4916 #define CSR_ACSMDESTMAP11_LSB 8 4917 #define CSR_ACSMDESTMAP11_MASK GENMASK_32(11, 8) 4918 #define CSR_ACSMODTMAP11_LSB 12 4919 #define CSR_ACSMODTMAP11_MASK GENMASK_32(14, 12) 4920 /* CSR_ACSMCSMAPCTRL12 */ 4921 #define CSR_ACSMCSMAPCTRL12_LSB 0 4922 #define CSR_ACSMCSMAPCTRL12_MASK GENMASK_32(14, 0) 4923 #define CSR_ACSMCSMAP12_LSB 0 4924 #define CSR_ACSMCSMAP12_MASK GENMASK_32(7, 0) 4925 #define CSR_ACSMDESTMAP12_LSB 8 4926 #define CSR_ACSMDESTMAP12_MASK GENMASK_32(11, 8) 4927 #define CSR_ACSMODTMAP12_LSB 12 4928 #define CSR_ACSMODTMAP12_MASK GENMASK_32(14, 12) 4929 /* CSR_ACSMCSMAPCTRL13 */ 4930 #define CSR_ACSMCSMAPCTRL13_LSB 0 4931 #define CSR_ACSMCSMAPCTRL13_MASK GENMASK_32(14, 0) 4932 #define CSR_ACSMCSMAP13_LSB 0 4933 #define CSR_ACSMCSMAP13_MASK GENMASK_32(7, 0) 4934 #define CSR_ACSMDESTMAP13_LSB 8 4935 #define CSR_ACSMDESTMAP13_MASK GENMASK_32(11, 8) 4936 #define CSR_ACSMODTMAP13_LSB 12 4937 #define CSR_ACSMODTMAP13_MASK GENMASK_32(14, 12) 4938 /* CSR_ACSMCSMAPCTRL14 */ 4939 #define CSR_ACSMCSMAPCTRL14_LSB 0 4940 #define CSR_ACSMCSMAPCTRL14_MASK GENMASK_32(14, 0) 4941 #define CSR_ACSMCSMAP14_LSB 0 4942 #define CSR_ACSMCSMAP14_MASK GENMASK_32(7, 0) 4943 #define CSR_ACSMDESTMAP14_LSB 8 4944 #define CSR_ACSMDESTMAP14_MASK GENMASK_32(11, 8) 4945 #define CSR_ACSMODTMAP14_LSB 12 4946 #define CSR_ACSMODTMAP14_MASK GENMASK_32(14, 12) 4947 /* CSR_ACSMCSMAPCTRL15 */ 4948 #define CSR_ACSMCSMAPCTRL15_LSB 0 4949 #define CSR_ACSMCSMAPCTRL15_MASK GENMASK_32(14, 0) 4950 #define CSR_ACSMCSMAP15_LSB 0 4951 #define CSR_ACSMCSMAP15_MASK GENMASK_32(7, 0) 4952 #define CSR_ACSMDESTMAP15_LSB 8 4953 #define CSR_ACSMDESTMAP15_MASK GENMASK_32(11, 8) 4954 #define CSR_ACSMODTMAP15_LSB 12 4955 #define CSR_ACSMODTMAP15_MASK GENMASK_32(14, 12) 4956 /* CSR_ACSMODTCTRL0 */ 4957 #define CSR_ACSMODTCTRL0_LSB 0 4958 #define CSR_ACSMODTCTRL0_MASK GENMASK_32(7, 0) 4959 #define CSR_ACSMODTWRPATCS0_LSB 0 4960 #define CSR_ACSMODTWRPATCS0_MASK GENMASK_32(3, 0) 4961 #define CSR_ACSMODTRDPATCS0_LSB 4 4962 #define CSR_ACSMODTRDPATCS0_MASK GENMASK_32(7, 4) 4963 /* CSR_ACSMODTCTRL1 */ 4964 #define CSR_ACSMODTCTRL1_LSB 0 4965 #define CSR_ACSMODTCTRL1_MASK GENMASK_32(7, 0) 4966 #define CSR_ACSMODTWRPATCS1_LSB 0 4967 #define CSR_ACSMODTWRPATCS1_MASK GENMASK_32(3, 0) 4968 #define CSR_ACSMODTRDPATCS1_LSB 4 4969 #define CSR_ACSMODTRDPATCS1_MASK GENMASK_32(7, 4) 4970 /* CSR_ACSMODTCTRL2 */ 4971 #define CSR_ACSMODTCTRL2_LSB 0 4972 #define CSR_ACSMODTCTRL2_MASK GENMASK_32(7, 0) 4973 #define CSR_ACSMODTWRPATCS2_LSB 0 4974 #define CSR_ACSMODTWRPATCS2_MASK GENMASK_32(3, 0) 4975 #define CSR_ACSMODTRDPATCS2_LSB 4 4976 #define CSR_ACSMODTRDPATCS2_MASK GENMASK_32(7, 4) 4977 /* CSR_ACSMODTCTRL3 */ 4978 #define CSR_ACSMODTCTRL3_LSB 0 4979 #define CSR_ACSMODTCTRL3_MASK GENMASK_32(7, 0) 4980 #define CSR_ACSMODTWRPATCS3_LSB 0 4981 #define CSR_ACSMODTWRPATCS3_MASK GENMASK_32(3, 0) 4982 #define CSR_ACSMODTRDPATCS3_LSB 4 4983 #define CSR_ACSMODTRDPATCS3_MASK GENMASK_32(7, 4) 4984 /* CSR_ACSMODTCTRL4 */ 4985 #define CSR_ACSMODTCTRL4_LSB 0 4986 #define CSR_ACSMODTCTRL4_MASK GENMASK_32(7, 0) 4987 #define CSR_ACSMODTWRPATCS4_LSB 0 4988 #define CSR_ACSMODTWRPATCS4_MASK GENMASK_32(3, 0) 4989 #define CSR_ACSMODTRDPATCS4_LSB 4 4990 #define CSR_ACSMODTRDPATCS4_MASK GENMASK_32(7, 4) 4991 /* CSR_ACSMODTCTRL5 */ 4992 #define CSR_ACSMODTCTRL5_LSB 0 4993 #define CSR_ACSMODTCTRL5_MASK GENMASK_32(7, 0) 4994 #define CSR_ACSMODTWRPATCS5_LSB 0 4995 #define CSR_ACSMODTWRPATCS5_MASK GENMASK_32(3, 0) 4996 #define CSR_ACSMODTRDPATCS5_LSB 4 4997 #define CSR_ACSMODTRDPATCS5_MASK GENMASK_32(7, 4) 4998 /* CSR_ACSMODTCTRL6 */ 4999 #define CSR_ACSMODTCTRL6_LSB 0 5000 #define CSR_ACSMODTCTRL6_MASK GENMASK_32(7, 0) 5001 #define CSR_ACSMODTWRPATCS6_LSB 0 5002 #define CSR_ACSMODTWRPATCS6_MASK GENMASK_32(3, 0) 5003 #define CSR_ACSMODTRDPATCS6_LSB 4 5004 #define CSR_ACSMODTRDPATCS6_MASK GENMASK_32(7, 4) 5005 /* CSR_ACSMODTCTRL7 */ 5006 #define CSR_ACSMODTCTRL7_LSB 0 5007 #define CSR_ACSMODTCTRL7_MASK GENMASK_32(7, 0) 5008 #define CSR_ACSMODTWRPATCS7_LSB 0 5009 #define CSR_ACSMODTWRPATCS7_MASK GENMASK_32(3, 0) 5010 #define CSR_ACSMODTRDPATCS7_LSB 4 5011 #define CSR_ACSMODTRDPATCS7_MASK GENMASK_32(7, 4) 5012 /* CSR_ACSMODTCTRL8 */ 5013 #define CSR_ACSMODTCTRL8_LSB 0 5014 #define CSR_ACSMODTCTRL8_MASK GENMASK_32(15, 0) 5015 #define CSR_ACSMODTWRDURCTRL_LSB 0 5016 #define CSR_ACSMODTWRDURCTRL_MASK GENMASK_32(3, 0) 5017 #define CSR_ACSMODTRDDURCTRL_LSB 4 5018 #define CSR_ACSMODTRDDURCTRL_MASK GENMASK_32(7, 4) 5019 #define CSR_ACSMODTWRSTRTCTRL_LSB 8 5020 #define CSR_ACSMODTWRSTRTCTRL_MASK GENMASK_32(11, 8) 5021 #define CSR_ACSMODTRDSTRTCTRL_LSB 12 5022 #define CSR_ACSMODTRDSTRTCTRL_MASK GENMASK_32(15, 12) 5023 /* CSR_ACSMCTRL16 */ 5024 #define CSR_ACSMCTRL16_LSB 0 5025 #define CSR_ACSMCTRL16_MASK GENMASK_32(15, 0) 5026 #define CSR_ACSMDDRADRUP_LSB 0 5027 #define CSR_ACSMDDRADRUP_MASK GENMASK_32(3, 0) 5028 #define CSR_ACSMHIGHADDR_LSB 4 5029 #define CSR_ACSMHIGHADDR_MASK BIT(4) 5030 #define CSR_ACSMADR13PLUGHOLE_LSB 5 5031 #define CSR_ACSMADR13PLUGHOLE_MASK BIT(5) 5032 #define CSR_ACSMCTRL16RSVD_LSB 6 5033 #define CSR_ACSMCTRL16RSVD_MASK BIT(6) 5034 #define CSR_ACSMWRTLVLODTCTRL_LSB 7 5035 #define CSR_ACSMWRTLVLODTCTRL_MASK BIT(7) 5036 #define CSR_ACSMWRTLVLODT_LSB 8 5037 #define CSR_ACSMWRTLVLODT_MASK GENMASK_32(11, 8) 5038 #define CSR_ACSM2TGRPINHIBIT_LSB 12 5039 #define CSR_ACSM2TGRPINHIBIT_MASK GENMASK_32(15, 12) 5040 /* CSR_LOWSPEEDCLOCKSTOPVAL */ 5041 #define CSR_LOWSPEEDCLOCKSTOPVAL_LSB 0 5042 #define CSR_LOWSPEEDCLOCKSTOPVAL_MASK BIT(0) 5043 /* CSR_ACSMCTRL18 */ 5044 #define CSR_ACSMCTRL18_LSB 0 5045 #define CSR_ACSMCTRL18_MASK GENMASK_32(1, 0) 5046 #define CSR_ACSMLOCALDONE_LSB 0 5047 #define CSR_ACSMLOCALDONE_MASK BIT(0) 5048 #define CSR_ACSMSTOPONERRASRTD_LSB 1 5049 #define CSR_ACSMSTOPONERRASRTD_MASK BIT(1) 5050 /* CSR_ACSMCTRL19 */ 5051 #define CSR_ACSMCTRL19_LSB 0 5052 #define CSR_ACSMCTRL19_MASK GENMASK_32(2, 0) 5053 #define CSR_ACSMVISSEL_LSB 0 5054 #define CSR_ACSMVISSEL_MASK GENMASK_32(2, 0) 5055 /* CSR_ACSMCTRL20 */ 5056 #define CSR_ACSMCTRL20_LSB 0 5057 #define CSR_ACSMCTRL20_MASK GENMASK_32(15, 0) 5058 #define CSR_ACSMVISVAL_LSB 0 5059 #define CSR_ACSMVISVAL_MASK GENMASK_32(15, 0) 5060 /* CSR_ACSMCTRL21 */ 5061 #define CSR_ACSMCTRL21_LSB 0 5062 #define CSR_ACSMCTRL21_MASK GENMASK_32(11, 0) 5063 #define CSR_ACSMMAPDIMMCS0_LSB 0 5064 #define CSR_ACSMMAPDIMMCS0_MASK GENMASK_32(2, 0) 5065 #define CSR_ACSMMAPDIMMCS1_LSB 3 5066 #define CSR_ACSMMAPDIMMCS1_MASK GENMASK_32(5, 3) 5067 #define CSR_ACSMMAPDIMMCS2_LSB 6 5068 #define CSR_ACSMMAPDIMMCS2_MASK GENMASK_32(8, 6) 5069 #define CSR_ACSMMAPDIMMCS3_LSB 9 5070 #define CSR_ACSMMAPDIMMCS3_MASK GENMASK_32(11, 9) 5071 /* CSR_ACSMCTRL22 */ 5072 #define CSR_ACSMCTRL22_LSB 0 5073 #define CSR_ACSMCTRL22_MASK GENMASK_32(11, 0) 5074 #define CSR_ACSMMAPDIMMCS4_LSB 0 5075 #define CSR_ACSMMAPDIMMCS4_MASK GENMASK_32(2, 0) 5076 #define CSR_ACSMMAPDIMMCS5_LSB 3 5077 #define CSR_ACSMMAPDIMMCS5_MASK GENMASK_32(5, 3) 5078 #define CSR_ACSMMAPDIMMCS6_LSB 6 5079 #define CSR_ACSMMAPDIMMCS6_MASK GENMASK_32(8, 6) 5080 #define CSR_ACSMMAPDIMMCS7_LSB 9 5081 #define CSR_ACSMMAPDIMMCS7_MASK GENMASK_32(11, 9) 5082 /* CSR_ACSMCTRL0 */ 5083 #define CSR_ACSMCTRL0_LSB 0 5084 #define CSR_ACSMCTRL0_MASK GENMASK_32(15, 0) 5085 #define CSR_ACSMRSVDCTRL00_LSB 0 5086 #define CSR_ACSMRSVDCTRL00_MASK BIT(0) 5087 #define CSR_ACSMDYNBLMODE_LSB 1 5088 #define CSR_ACSMDYNBLMODE_MASK BIT(1) 5089 #define CSR_ACSMBURSTLEN_LSB 2 5090 #define CSR_ACSMBURSTLEN_MASK BIT(2) 5091 #define CSR_ACSMINFLOOP_LSB 3 5092 #define CSR_ACSMINFLOOP_MASK BIT(3) 5093 #define CSR_ACSMRXVALMODE_LSB 4 5094 #define CSR_ACSMRXVALMODE_MASK BIT(4) 5095 #define CSR_ACSMSTPONERRMODE_LSB 5 5096 #define CSR_ACSMSTPONERRMODE_MASK BIT(5) 5097 #define CSR_ACSM2TMODE_LSB 6 5098 #define CSR_ACSM2TMODE_MASK BIT(6) 5099 #define CSR_ACSMTRAINSOEMODE_LSB 7 5100 #define CSR_ACSMTRAINSOEMODE_MASK BIT(7) 5101 #define CSR_ACSMGATEDDRCMD_LSB 8 5102 #define CSR_ACSMGATEDDRCMD_MASK BIT(8) 5103 #define CSR_ACSMGEARDOWNMODE_LSB 9 5104 #define CSR_ACSMGEARDOWNMODE_MASK BIT(9) 5105 #define CSR_ACSMGEARDOWNPHASE_LSB 10 5106 #define CSR_ACSMGEARDOWNPHASE_MASK BIT(10) 5107 #define CSR_ACSMGEARDOWNSYNC_LSB 11 5108 #define CSR_ACSMGEARDOWNSYNC_MASK BIT(11) 5109 #define CSR_ACSMCAPRBSMODE_LSB 12 5110 #define CSR_ACSMCAPRBSMODE_MASK BIT(12) 5111 #define CSR_ACSMGATERXFIFOWRITE_LSB 13 5112 #define CSR_ACSMGATERXFIFOWRITE_MASK BIT(13) 5113 #define CSR_ACSMPARMODE_LSB 14 5114 #define CSR_ACSMPARMODE_MASK BIT(14) 5115 #define CSR_ACSMTDSMODE_LSB 15 5116 #define CSR_ACSMTDSMODE_MASK BIT(15) 5117 /* CSR_ACSMCTRL1 */ 5118 #define CSR_ACSMCTRL1_LSB 0 5119 #define CSR_ACSMCTRL1_MASK GENMASK_32(15, 0) 5120 #define CSR_ACSMREPCNT_LSB 0 5121 #define CSR_ACSMREPCNT_MASK GENMASK_32(15, 0) 5122 /* CSR_ACSMCTRL2 */ 5123 #define CSR_ACSMCTRL2_LSB 0 5124 #define CSR_ACSMCTRL2_MASK GENMASK_32(4, 0) 5125 #define CSR_ACSMSTARTPTR_LSB 0 5126 #define CSR_ACSMSTARTPTR_MASK GENMASK_32(4, 0) 5127 /* CSR_ACSMCTRL3 */ 5128 #define CSR_ACSMCTRL3_LSB 0 5129 #define CSR_ACSMCTRL3_MASK GENMASK_32(4, 0) 5130 #define CSR_ACSMLOOPPTR_LSB 0 5131 #define CSR_ACSMLOOPPTR_MASK GENMASK_32(4, 0) 5132 /* CSR_ACSMCTRL4 */ 5133 #define CSR_ACSMCTRL4_LSB 0 5134 #define CSR_ACSMCTRL4_MASK GENMASK_32(4, 0) 5135 #define CSR_ACSMENDPTR_LSB 0 5136 #define CSR_ACSMENDPTR_MASK GENMASK_32(4, 0) 5137 /* CSR_ACSMCTRL5 */ 5138 #define CSR_ACSMCTRL5_LSB 0 5139 #define CSR_ACSMCTRL5_MASK GENMASK_32(13, 0) 5140 #define CSR_ACSMMXRDLAT_LSB 0 5141 #define CSR_ACSMMXRDLAT_MASK GENMASK_32(7, 0) 5142 #define CSR_ACSMRCASLAT_LSB 8 5143 #define CSR_ACSMRCASLAT_MASK GENMASK_32(13, 8) 5144 /* CSR_ACSMCTRL6 */ 5145 #define CSR_ACSMCTRL6_LSB 0 5146 #define CSR_ACSMCTRL6_MASK GENMASK_32(10, 0) 5147 #define CSR_ACSMWCASLAT_LSB 0 5148 #define CSR_ACSMWCASLAT_MASK GENMASK_32(5, 0) 5149 #define CSR_ACSMWRRSVD_LSB 6 5150 #define CSR_ACSMWRRSVD_MASK GENMASK_32(7, 6) 5151 #define CSR_ACSMWRDATLAT_LSB 8 5152 #define CSR_ACSMWRDATLAT_MASK GENMASK_32(10, 8) 5153 /* CSR_ACSMCTRL7 */ 5154 #define CSR_ACSMCTRL7_LSB 0 5155 #define CSR_ACSMCTRL7_MASK GENMASK_32(15, 0) 5156 #define CSR_ACSMRASPCFG_LSB 0 5157 #define CSR_ACSMRASPCFG_MASK GENMASK_32(15, 0) 5158 /* CSR_ACSMCTRL8 */ 5159 #define CSR_ACSMCTRL8_LSB 0 5160 #define CSR_ACSMCTRL8_MASK GENMASK_32(15, 0) 5161 #define CSR_ACSMRASPSEED_LSB 0 5162 #define CSR_ACSMRASPSEED_MASK GENMASK_32(15, 0) 5163 /* CSR_ACSMCTRL9 */ 5164 #define CSR_ACSMCTRL9_LSB 0 5165 #define CSR_ACSMCTRL9_MASK GENMASK_32(15, 0) 5166 #define CSR_ACSMCASPCFG_LSB 0 5167 #define CSR_ACSMCASPCFG_MASK GENMASK_32(15, 0) 5168 /* CSR_ACSMCTRL10 */ 5169 #define CSR_ACSMCTRL10_LSB 0 5170 #define CSR_ACSMCTRL10_MASK GENMASK_32(15, 0) 5171 #define CSR_ACSMCASPSEED_LSB 0 5172 #define CSR_ACSMCASPSEED_MASK GENMASK_32(15, 0) 5173 /* CSR_ACSMCTRL11 */ 5174 #define CSR_ACSMCTRL11_LSB 0 5175 #define CSR_ACSMCTRL11_MASK GENMASK_32(15, 0) 5176 #define CSR_ACSMRASADRINC_LSB 0 5177 #define CSR_ACSMRASADRINC_MASK GENMASK_32(7, 0) 5178 #define CSR_ACSMCASADRINC_LSB 8 5179 #define CSR_ACSMCASADRINC_MASK GENMASK_32(15, 8) 5180 /* CSR_ACSMCTRL12 */ 5181 #define CSR_ACSMCTRL12_LSB 0 5182 #define CSR_ACSMCTRL12_MASK GENMASK_32(11, 0) 5183 #define CSR_ACSMBNKPCFG_LSB 0 5184 #define CSR_ACSMBNKPCFG_MASK GENMASK_32(3, 0) 5185 #define CSR_ACSMBNKPSEED_LSB 4 5186 #define CSR_ACSMBNKPSEED_MASK GENMASK_32(7, 4) 5187 #define CSR_ACSMBNKADRINC_LSB 8 5188 #define CSR_ACSMBNKADRINC_MASK GENMASK_32(11, 8) 5189 /* CSR_ACSMCTRL13 */ 5190 #define CSR_ACSMCTRL13_LSB 0 5191 #define CSR_ACSMCTRL13_MASK GENMASK_32(3, 0) 5192 #define CSR_ACSMCKEENB_LSB 0 5193 #define CSR_ACSMCKEENB_MASK GENMASK_32(3, 0) 5194 /* CSR_ACSMCTRL14 */ 5195 #define CSR_ACSMCTRL14_LSB 0 5196 #define CSR_ACSMCTRL14_MASK GENMASK_32(3, 0) 5197 #define CSR_ACSMRASPCFGUP_LSB 0 5198 #define CSR_ACSMRASPCFGUP_MASK GENMASK_32(3, 0) 5199 /* CSR_ACSMCTRL15 */ 5200 #define CSR_ACSMCTRL15_LSB 0 5201 #define CSR_ACSMCTRL15_MASK GENMASK_32(3, 0) 5202 #define CSR_ACSMRASPSEEDUP_LSB 0 5203 #define CSR_ACSMRASPSEEDUP_MASK GENMASK_32(3, 0) 5204 5205 /* PPGC0 register offsets */ 5206 /* CSR_PPGCCTRL1 */ 5207 #define CSR_PPGCCTRL1_LSB 1 5208 #define CSR_PPGCCTRL1_MASK GENMASK_32(4, 1) 5209 #define CSR_HWTTXDBIEN_LSB 1 5210 #define CSR_HWTTXDBIEN_MASK BIT(1) 5211 #define CSR_HWTRXDBIEN_LSB 2 5212 #define CSR_HWTRXDBIEN_MASK BIT(2) 5213 #define CSR_HWTTXDMDBIVAL_LSB 3 5214 #define CSR_HWTTXDMDBIVAL_MASK BIT(3) 5215 #define CSR_HWTTXDMDBISEL_LSB 4 5216 #define CSR_HWTTXDMDBISEL_MASK BIT(4) 5217 /* CSR_PPGCLANE2CRCINMAP0 */ 5218 #define CSR_PPGCLANE2CRCINMAP0_LSB 0 5219 #define CSR_PPGCLANE2CRCINMAP0_MASK GENMASK_32(11, 0) 5220 #define CSR_PPGCCRCLANEMAP0_LSB 0 5221 #define CSR_PPGCCRCLANEMAP0_MASK GENMASK_32(2, 0) 5222 #define CSR_PPGCCRCLANEMAP1_LSB 3 5223 #define CSR_PPGCCRCLANEMAP1_MASK GENMASK_32(5, 3) 5224 #define CSR_PPGCCRCLANEMAP2_LSB 6 5225 #define CSR_PPGCCRCLANEMAP2_MASK GENMASK_32(8, 6) 5226 #define CSR_PPGCCRCLANEMAP3_LSB 9 5227 #define CSR_PPGCCRCLANEMAP3_MASK GENMASK_32(11, 9) 5228 /* CSR_PPGCLANE2CRCINMAP1 */ 5229 #define CSR_PPGCLANE2CRCINMAP1_LSB 0 5230 #define CSR_PPGCLANE2CRCINMAP1_MASK GENMASK_32(11, 0) 5231 #define CSR_PPGCCRCLANEMAP4_LSB 0 5232 #define CSR_PPGCCRCLANEMAP4_MASK GENMASK_32(2, 0) 5233 #define CSR_PPGCCRCLANEMAP5_LSB 3 5234 #define CSR_PPGCCRCLANEMAP5_MASK GENMASK_32(5, 3) 5235 #define CSR_PPGCCRCLANEMAP6_LSB 6 5236 #define CSR_PPGCCRCLANEMAP6_MASK GENMASK_32(8, 6) 5237 #define CSR_PPGCCRCLANEMAP7_LSB 9 5238 #define CSR_PPGCCRCLANEMAP7_MASK GENMASK_32(11, 9) 5239 /* CSR_PRBSTAPDLY0 */ 5240 #define CSR_PRBSTAPDLY0_LSB 0 5241 #define CSR_PRBSTAPDLY0_MASK GENMASK_32(15, 0) 5242 /* CSR_PRBSTAPDLY1 */ 5243 #define CSR_PRBSTAPDLY1_LSB 0 5244 #define CSR_PRBSTAPDLY1_MASK GENMASK_32(15, 0) 5245 /* CSR_PRBSTAPDLY2 */ 5246 #define CSR_PRBSTAPDLY2_LSB 0 5247 #define CSR_PRBSTAPDLY2_MASK GENMASK_32(15, 0) 5248 /* CSR_PRBSTAPDLY3 */ 5249 #define CSR_PRBSTAPDLY3_LSB 0 5250 #define CSR_PRBSTAPDLY3_MASK GENMASK_32(15, 0) 5251 /* CSR_GENPRBSBYTE0 */ 5252 #define CSR_GENPRBSBYTE0_LSB 0 5253 #define CSR_GENPRBSBYTE0_MASK GENMASK_32(15, 0) 5254 /* CSR_GENPRBSBYTE1² */ 5255 #define CSR_GENPRBSBYTE1_LSB 0 5256 #define CSR_GENPRBSBYTE1_MASK GENMASK_32(15, 0) 5257 /* CSR_GENPRBSBYTE2 */ 5258 #define CSR_GENPRBSBYTE2_LSB 0 5259 #define CSR_GENPRBSBYTE2_MASK GENMASK_32(15, 0) 5260 /* CSR_GENPRBSBYTE3 */ 5261 #define CSR_GENPRBSBYTE3_LSB 0 5262 #define CSR_GENPRBSBYTE3_MASK GENMASK_32(15, 0) 5263 /* CSR_GENPRBSBYTE4 */ 5264 #define CSR_GENPRBSBYTE4_LSB 0 5265 #define CSR_GENPRBSBYTE4_MASK GENMASK_32(15, 0) 5266 /* CSR_GENPRBSBYTE5 */ 5267 #define CSR_GENPRBSBYTE5_LSB 0 5268 #define CSR_GENPRBSBYTE5_MASK GENMASK_32(15, 0) 5269 /* CSR_GENPRBSBYTE6 */ 5270 #define CSR_GENPRBSBYTE6_LSB 0 5271 #define CSR_GENPRBSBYTE6_MASK GENMASK_32(15, 0) 5272 /* CSR_GENPRBSBYTE7 */ 5273 #define CSR_GENPRBSBYTE7_LSB 0 5274 #define CSR_GENPRBSBYTE7_MASK GENMASK_32(15, 0) 5275 /* CSR_GENPRBSBYTE8 */ 5276 #define CSR_GENPRBSBYTE8_LSB 0 5277 #define CSR_GENPRBSBYTE8_MASK GENMASK_32(15, 0) 5278 /* CSR_GENPRBSBYTE9 */ 5279 #define CSR_GENPRBSBYTE9_LSB 0 5280 #define CSR_GENPRBSBYTE9_MASK GENMASK_32(15, 0) 5281 /* CSR_GENPRBSBYTE10 */ 5282 #define CSR_GENPRBSBYTE10_LSB 0 5283 #define CSR_GENPRBSBYTE10_MASK GENMASK_32(15, 0) 5284 /* CSR_GENPRBSBYTE11 */ 5285 #define CSR_GENPRBSBYTE11_LSB 0 5286 #define CSR_GENPRBSBYTE11_MASK GENMASK_32(15, 0) 5287 /* CSR_GENPRBSBYTE12 */ 5288 #define CSR_GENPRBSBYTE12_LSB 0 5289 #define CSR_GENPRBSBYTE12_MASK GENMASK_32(15, 0) 5290 /* CSR_GENPRBSBYTE13 */ 5291 #define CSR_GENPRBSBYTE13_LSB 0 5292 #define CSR_GENPRBSBYTE13_MASK GENMASK_32(15, 0) 5293 /* CSR_GENPRBSBYTE14 */ 5294 #define CSR_GENPRBSBYTE14_LSB 0 5295 #define CSR_GENPRBSBYTE14_MASK GENMASK_32(15, 0) 5296 /* CSR_GENPRBSBYTE15 */ 5297 #define CSR_GENPRBSBYTE15_LSB 0 5298 #define CSR_GENPRBSBYTE15_MASK GENMASK_32(15, 0) 5299 /* CSR_PRBSGENCTL */ 5300 #define CSR_PRBSGENCTL_LSB 0 5301 #define CSR_PRBSGENCTL_MASK GENMASK_32(6, 0) 5302 #define CSR_PPGCMODE_LSB 0 5303 #define CSR_PPGCMODE_MASK BIT(0) 5304 #define CSR_PPGCDMMODE_LSB 1 5305 #define CSR_PPGCDMMODE_MASK BIT(1) 5306 #define CSR_PPGCLDFFMODE_LSB 2 5307 #define CSR_PPGCLDFFMODE_MASK BIT(2) 5308 #define CSR_PPGCSEL23BPRBS_LSB 3 5309 #define CSR_PPGCSEL23BPRBS_MASK BIT(3) 5310 #define CSR_PPGCPATADV_LSB 4 5311 #define CSR_PPGCPATADV_MASK GENMASK_32(5, 4) 5312 #define CSR_PPGCENBPATSTRESSMODE_LSB 6 5313 #define CSR_PPGCENBPATSTRESSMODE_MASK BIT(6) 5314 /* CSR_PRBSGENSTATELO */ 5315 #define CSR_PRBSGENSTATELO_LSB 0 5316 #define CSR_PRBSGENSTATELO_MASK GENMASK_32(15, 0) 5317 /* CSR_PRBSGENSTATEHI */ 5318 #define CSR_PRBSGENSTATEHI_LSB 0 5319 #define CSR_PRBSGENSTATEHI_MASK GENMASK_32(6, 0) 5320 /* CSR_PRBSCHKSTATELO */ 5321 #define CSR_PRBSCHKSTATELO_LSB 0 5322 #define CSR_PRBSCHKSTATELO_MASK GENMASK_32(15, 0) 5323 /* CSR_PRBSCHKSTATEHI */ 5324 #define CSR_PRBSCHKSTATEHI_LSB 0 5325 #define CSR_PRBSCHKSTATEHI_MASK GENMASK_32(6, 0) 5326 /* CSR_PRBSGENCTL1 */ 5327 #define CSR_PRBSGENCTL1_LSB 0 5328 #define CSR_PRBSGENCTL1_MASK GENMASK_32(8, 0) 5329 #define CSR_PPGCMODELANE_LSB 0 5330 #define CSR_PPGCMODELANE_MASK GENMASK_32(8, 0) 5331 /* CSR_PRBSGENCTL2 */ 5332 #define CSR_PRBSGENCTL2_LSB 0 5333 #define CSR_PRBSGENCTL2_MASK GENMASK_32(15, 0) 5334 #define CSR_PPGCMSKPERIODLIM_LSB 0 5335 #define CSR_PPGCMSKPERIODLIM_MASK GENMASK_32(15, 0) 5336 5337 /* INITENG0 register offsets */ 5338 /* CSR_PRESEQUENCEREG0B0S0 */ 5339 #define CSR_PRESEQUENCEREG0B0S0_LSB 0 5340 #define CSR_PRESEQUENCEREG0B0S0_MASK GENMASK_32(15, 0) 5341 /* CSR_PRESEQUENCEREG0B0S1 */ 5342 #define CSR_PRESEQUENCEREG0B0S1_LSB 0 5343 #define CSR_PRESEQUENCEREG0B0S1_MASK GENMASK_32(15, 0) 5344 /* CSR_PRESEQUENCEREG0B0S2 */ 5345 #define CSR_PRESEQUENCEREG0B0S2_LSB 0 5346 #define CSR_PRESEQUENCEREG0B0S2_MASK GENMASK_32(8, 0) 5347 /* CSR_PRESEQUENCEREG0B1S0 */ 5348 #define CSR_PRESEQUENCEREG0B1S0_LSB 0 5349 #define CSR_PRESEQUENCEREG0B1S0_MASK GENMASK_32(15, 0) 5350 /* CSR_PRESEQUENCEREG0B1S1 */ 5351 #define CSR_PRESEQUENCEREG0B1S1_LSB 0 5352 #define CSR_PRESEQUENCEREG0B1S1_MASK GENMASK_32(15, 0) 5353 /* CSR_PRESEQUENCEREG0B1S2 */ 5354 #define CSR_PRESEQUENCEREG0B1S2_LSB 0 5355 #define CSR_PRESEQUENCEREG0B1S2_MASK GENMASK_32(8, 0) 5356 /* CSR_POSTSEQUENCEREG0B0S0 */ 5357 #define CSR_POSTSEQUENCEREG0B0S0_LSB 0 5358 #define CSR_POSTSEQUENCEREG0B0S0_MASK GENMASK_32(15, 0) 5359 /* CSR_POSTSEQUENCEREG0B0S1 */ 5360 #define CSR_POSTSEQUENCEREG0B0S1_LSB 0 5361 #define CSR_POSTSEQUENCEREG0B0S1_MASK GENMASK_32(15, 0) 5362 /* CSR_POSTSEQUENCEREG0B0S2 */ 5363 #define CSR_POSTSEQUENCEREG0B0S2_LSB 0 5364 #define CSR_POSTSEQUENCEREG0B0S2_MASK GENMASK_32(8, 0) 5365 /* CSR_POSTSEQUENCEREG0B1S0 */ 5366 #define CSR_POSTSEQUENCEREG0B1S0_LSB 0 5367 #define CSR_POSTSEQUENCEREG0B1S0_MASK GENMASK_32(15, 0) 5368 /* CSR_POSTSEQUENCEREG0B1S1 */ 5369 #define CSR_POSTSEQUENCEREG0B1S1_LSB 0 5370 #define CSR_POSTSEQUENCEREG0B1S1_MASK GENMASK_32(15, 0) 5371 /* CSR_POSTSEQUENCEREG0B1S2 */ 5372 #define CSR_POSTSEQUENCEREG0B1S2_LSB 0 5373 #define CSR_POSTSEQUENCEREG0B1S2_MASK GENMASK_32(8, 0) 5374 /* CSR_SEQ0BDISABLEFLAG0 */ 5375 #define CSR_SEQ0BDISABLEFLAG0_LSB 0 5376 #define CSR_SEQ0BDISABLEFLAG0_MASK GENMASK_32(15, 0) 5377 /* CSR_SEQ0BDISABLEFLAG1 */ 5378 #define CSR_SEQ0BDISABLEFLAG1_LSB 0 5379 #define CSR_SEQ0BDISABLEFLAG1_MASK GENMASK_32(15, 0) 5380 /* CSR_SEQ0BDISABLEFLAG2 */ 5381 #define CSR_SEQ0BDISABLEFLAG2_LSB 0 5382 #define CSR_SEQ0BDISABLEFLAG2_MASK GENMASK_32(15, 0) 5383 /* CSR_SEQ0BDISABLEFLAG3 */ 5384 #define CSR_SEQ0BDISABLEFLAG3_LSB 0 5385 #define CSR_SEQ0BDISABLEFLAG3_MASK GENMASK_32(15, 0) 5386 /* CSR_SEQ0BDISABLEFLAG4 */ 5387 #define CSR_SEQ0BDISABLEFLAG4_LSB 0 5388 #define CSR_SEQ0BDISABLEFLAG4_MASK GENMASK_32(15, 0) 5389 /* CSR_SEQ0BDISABLEFLAG5 */ 5390 #define CSR_SEQ0BDISABLEFLAG5_LSB 0 5391 #define CSR_SEQ0BDISABLEFLAG5_MASK GENMASK_32(15, 0) 5392 /* CSR_SEQ0BDISABLEFLAG6 */ 5393 #define CSR_SEQ0BDISABLEFLAG6_LSB 0 5394 #define CSR_SEQ0BDISABLEFLAG6_MASK GENMASK_32(15, 0) 5395 /* CSR_SEQ0BDISABLEFLAG7 */ 5396 #define CSR_SEQ0BDISABLEFLAG7_LSB 0 5397 #define CSR_SEQ0BDISABLEFLAG7_MASK GENMASK_32(15, 0) 5398 /* CSR_STARTVECTOR0B0 */ 5399 #define CSR_STARTVECTOR0B0_LSB 0 5400 #define CSR_STARTVECTOR0B0_MASK GENMASK_32(6, 0) 5401 #define CSR_SEQ0BSTARTVEC0_LSB 0 5402 #define CSR_SEQ0BSTARTVEC0_MASK GENMASK_32(6, 0) 5403 /* CSR_STARTVECTOR0B1 */ 5404 #define CSR_STARTVECTOR0B1_LSB 0 5405 #define CSR_STARTVECTOR0B1_MASK GENMASK_32(6, 0) 5406 #define CSR_SEQ0BSTARTVEC1_LSB 0 5407 #define CSR_SEQ0BSTARTVEC1_MASK GENMASK_32(6, 0) 5408 /* CSR_STARTVECTOR0B2 */ 5409 #define CSR_STARTVECTOR0B2_LSB 0 5410 #define CSR_STARTVECTOR0B2_MASK GENMASK_32(6, 0) 5411 #define CSR_SEQ0BSTARTVEC2_LSB 0 5412 #define CSR_SEQ0BSTARTVEC2_MASK GENMASK_32(6, 0) 5413 /* CSR_STARTVECTOR0B3 */ 5414 #define CSR_STARTVECTOR0B3_LSB 0 5415 #define CSR_STARTVECTOR0B3_MASK GENMASK_32(6, 0) 5416 #define CSR_SEQ0BSTARTVEC3_LSB 0 5417 #define CSR_SEQ0BSTARTVEC3_MASK GENMASK_32(6, 0) 5418 /* CSR_STARTVECTOR0B4 */ 5419 #define CSR_STARTVECTOR0B4_LSB 0 5420 #define CSR_STARTVECTOR0B4_MASK GENMASK_32(6, 0) 5421 #define CSR_SEQ0BSTARTVEC4_LSB 0 5422 #define CSR_SEQ0BSTARTVEC4_MASK GENMASK_32(6, 0) 5423 /* CSR_STARTVECTOR0B5 */ 5424 #define CSR_STARTVECTOR0B5_LSB 0 5425 #define CSR_STARTVECTOR0B5_MASK GENMASK_32(6, 0) 5426 #define CSR_SEQ0BSTARTVEC5_LSB 0 5427 #define CSR_SEQ0BSTARTVEC5_MASK GENMASK_32(6, 0) 5428 /* CSR_STARTVECTOR0B6 */ 5429 #define CSR_STARTVECTOR0B6_LSB 0 5430 #define CSR_STARTVECTOR0B6_MASK GENMASK_32(6, 0) 5431 #define CSR_SEQ0BSTARTVEC6_LSB 0 5432 #define CSR_SEQ0BSTARTVEC6_MASK GENMASK_32(6, 0) 5433 /* CSR_STARTVECTOR0B7 */ 5434 #define CSR_STARTVECTOR0B7_LSB 0 5435 #define CSR_STARTVECTOR0B7_MASK GENMASK_32(6, 0) 5436 #define CSR_SEQ0BSTARTVEC7_LSB 0 5437 #define CSR_SEQ0BSTARTVEC7_MASK GENMASK_32(6, 0) 5438 /* CSR_STARTVECTOR0B8 */ 5439 #define CSR_STARTVECTOR0B8_LSB 0 5440 #define CSR_STARTVECTOR0B8_MASK GENMASK_32(6, 0) 5441 #define CSR_SEQ0BSTARTVEC8_LSB 0 5442 #define CSR_SEQ0BSTARTVEC8_MASK GENMASK_32(6, 0) 5443 /* CSR_STARTVECTOR0B9 */ 5444 #define CSR_STARTVECTOR0B9_LSB 0 5445 #define CSR_STARTVECTOR0B9_MASK GENMASK_32(6, 0) 5446 #define CSR_SEQ0BSTARTVEC9_LSB 0 5447 #define CSR_SEQ0BSTARTVEC9_MASK GENMASK_32(6, 0) 5448 /* CSR_STARTVECTOR0B10 */ 5449 #define CSR_STARTVECTOR0B10_LSB 0 5450 #define CSR_STARTVECTOR0B10_MASK GENMASK_32(6, 0) 5451 #define CSR_SEQ0BSTARTVEC10_LSB 0 5452 #define CSR_SEQ0BSTARTVEC10_MASK GENMASK_32(6, 0) 5453 /* CSR_STARTVECTOR0B11 */ 5454 #define CSR_STARTVECTOR0B11_LSB 0 5455 #define CSR_STARTVECTOR0B11_MASK GENMASK_32(6, 0) 5456 #define CSR_SEQ0BSTARTVEC11_LSB 0 5457 #define CSR_SEQ0BSTARTVEC11_MASK GENMASK_32(6, 0) 5458 /* CSR_STARTVECTOR0B12 */ 5459 #define CSR_STARTVECTOR0B12_LSB 0 5460 #define CSR_STARTVECTOR0B12_MASK GENMASK_32(6, 0) 5461 #define CSR_SEQ0BSTARTVEC12_LSB 0 5462 #define CSR_SEQ0BSTARTVEC12_MASK GENMASK_32(6, 0) 5463 /* CSR_STARTVECTOR0B13 */ 5464 #define CSR_STARTVECTOR0B13_LSB 0 5465 #define CSR_STARTVECTOR0B13_MASK GENMASK_32(6, 0) 5466 #define CSR_SEQ0BSTARTVEC13_LSB 0 5467 #define CSR_SEQ0BSTARTVEC13_MASK GENMASK_32(6, 0) 5468 /* CSR_STARTVECTOR0B14 */ 5469 #define CSR_STARTVECTOR0B14_LSB 0 5470 #define CSR_STARTVECTOR0B14_MASK GENMASK_32(6, 0) 5471 #define CSR_SEQ0BSTARTVEC14_LSB 0 5472 #define CSR_SEQ0BSTARTVEC14_MASK GENMASK_32(6, 0) 5473 /* CSR_STARTVECTOR0B15 */ 5474 #define CSR_STARTVECTOR0B15_LSB 0 5475 #define CSR_STARTVECTOR0B15_MASK GENMASK_32(6, 0) 5476 #define CSR_SEQ0BSTARTVEC15_LSB 0 5477 #define CSR_SEQ0BSTARTVEC15_MASK GENMASK_32(6, 0) 5478 /* CSR_SEQ0BWAITCONDSEL */ 5479 #define CSR_SEQ0BWAITCONDSEL_LSB 0 5480 #define CSR_SEQ0BWAITCONDSEL_MASK GENMASK_32(2, 0) 5481 /* CSR_PHYINLP3 */ 5482 #define CSR_PHYINLP3_LSB 0 5483 #define CSR_PHYINLP3_MASK BIT(0) 5484 /* CSR_SEQUENCEREG0B0S0 */ 5485 #define CSR_SEQUENCEREG0B0S0_LSB 0 5486 #define CSR_SEQUENCEREG0B0S0_MASK GENMASK_32(15, 0) 5487 /* CSR_SEQUENCEREG0B0S1 */ 5488 #define CSR_SEQUENCEREG0B0S1_LSB 0 5489 #define CSR_SEQUENCEREG0B0S1_MASK GENMASK_32(15, 0) 5490 /* CSR_SEQUENCEREG0B0S2 */ 5491 #define CSR_SEQUENCEREG0B0S2_LSB 0 5492 #define CSR_SEQUENCEREG0B0S2_MASK GENMASK_32(8, 0) 5493 /* CSR_SEQUENCEREG0B1S0 */ 5494 #define CSR_SEQUENCEREG0B1S0_LSB 0 5495 #define CSR_SEQUENCEREG0B1S0_MASK GENMASK_32(15, 0) 5496 /* CSR_SEQUENCEREG0B1S1 */ 5497 #define CSR_SEQUENCEREG0B1S1_LSB 0 5498 #define CSR_SEQUENCEREG0B1S1_MASK GENMASK_32(15, 0) 5499 /* CSR_SEQUENCEREG0B1S2 */ 5500 #define CSR_SEQUENCEREG0B1S2_LSB 0 5501 #define CSR_SEQUENCEREG0B1S2_MASK GENMASK_32(8, 0) 5502 /* CSR_SEQUENCEREG0B2S0 */ 5503 #define CSR_SEQUENCEREG0B2S0_LSB 0 5504 #define CSR_SEQUENCEREG0B2S0_MASK GENMASK_32(15, 0) 5505 /* CSR_SEQUENCEREG0B2S1 */ 5506 #define CSR_SEQUENCEREG0B2S1_LSB 0 5507 #define CSR_SEQUENCEREG0B2S1_MASK GENMASK_32(15, 0) 5508 /* CSR_SEQUENCEREG0B2S2 */ 5509 #define CSR_SEQUENCEREG0B2S2_LSB 0 5510 #define CSR_SEQUENCEREG0B2S2_MASK GENMASK_32(8, 0) 5511 /* CSR_SEQUENCEREG0B3S0 */ 5512 #define CSR_SEQUENCEREG0B3S0_LSB 0 5513 #define CSR_SEQUENCEREG0B3S0_MASK GENMASK_32(15, 0) 5514 /* CSR_SEQUENCEREG0B3S1 */ 5515 #define CSR_SEQUENCEREG0B3S1_LSB 0 5516 #define CSR_SEQUENCEREG0B3S1_MASK GENMASK_32(15, 0) 5517 /* CSR_SEQUENCEREG0B3S2 */ 5518 #define CSR_SEQUENCEREG0B3S2_LSB 0 5519 #define CSR_SEQUENCEREG0B3S2_MASK GENMASK_32(8, 0) 5520 /* CSR_SEQUENCEREG0B4S0 */ 5521 #define CSR_SEQUENCEREG0B4S0_LSB 0 5522 #define CSR_SEQUENCEREG0B4S0_MASK GENMASK_32(15, 0) 5523 /* CSR_SEQUENCEREG0B4S1 */ 5524 #define CSR_SEQUENCEREG0B4S1_LSB 0 5525 #define CSR_SEQUENCEREG0B4S1_MASK GENMASK_32(15, 0) 5526 /* CSR_SEQUENCEREG0B4S2 */ 5527 #define CSR_SEQUENCEREG0B4S2_LSB 0 5528 #define CSR_SEQUENCEREG0B4S2_MASK GENMASK_32(8, 0) 5529 /* CSR_SEQUENCEREG0B5S0 */ 5530 #define CSR_SEQUENCEREG0B5S0_LSB 0 5531 #define CSR_SEQUENCEREG0B5S0_MASK GENMASK_32(15, 0) 5532 /* CSR_SEQUENCEREG0B5S1 */ 5533 #define CSR_SEQUENCEREG0B5S1_LSB 0 5534 #define CSR_SEQUENCEREG0B5S1_MASK GENMASK_32(15, 0) 5535 /* CSR_SEQUENCEREG0B5S2 */ 5536 #define CSR_SEQUENCEREG0B5S2_LSB 0 5537 #define CSR_SEQUENCEREG0B5S2_MASK GENMASK_32(8, 0) 5538 /* CSR_SEQUENCEREG0B6S0 */ 5539 #define CSR_SEQUENCEREG0B6S0_LSB 0 5540 #define CSR_SEQUENCEREG0B6S0_MASK GENMASK_32(15, 0) 5541 /* CSR_SEQUENCEREG0B6S1 */ 5542 #define CSR_SEQUENCEREG0B6S1_LSB 0 5543 #define CSR_SEQUENCEREG0B6S1_MASK GENMASK_32(15, 0) 5544 /* CSR_SEQUENCEREG0B6S2 */ 5545 #define CSR_SEQUENCEREG0B6S2_LSB 0 5546 #define CSR_SEQUENCEREG0B6S2_MASK GENMASK_32(8, 0) 5547 /* CSR_SEQUENCEREG0B7S0 */ 5548 #define CSR_SEQUENCEREG0B7S0_LSB 0 5549 #define CSR_SEQUENCEREG0B7S0_MASK GENMASK_32(15, 0) 5550 /* CSR_SEQUENCEREG0B7S1 */ 5551 #define CSR_SEQUENCEREG0B7S1_LSB 0 5552 #define CSR_SEQUENCEREG0B7S1_MASK GENMASK_32(15, 0) 5553 /* CSR_SEQUENCEREG0B7S2 */ 5554 #define CSR_SEQUENCEREG0B7S2_LSB 0 5555 #define CSR_SEQUENCEREG0B7S2_MASK GENMASK_32(8, 0) 5556 /* CSR_SEQUENCEREG0B8S0 */ 5557 #define CSR_SEQUENCEREG0B8S0_LSB 0 5558 #define CSR_SEQUENCEREG0B8S0_MASK GENMASK_32(15, 0) 5559 /* CSR_SEQUENCEREG0B8S1 */ 5560 #define CSR_SEQUENCEREG0B8S1_LSB 0 5561 #define CSR_SEQUENCEREG0B8S1_MASK GENMASK_32(15, 0) 5562 /* CSR_SEQUENCEREG0B8S2 */ 5563 #define CSR_SEQUENCEREG0B8S2_LSB 0 5564 #define CSR_SEQUENCEREG0B8S2_MASK GENMASK_32(8, 0) 5565 /* CSR_SEQUENCEREG0B9S0 */ 5566 #define CSR_SEQUENCEREG0B9S0_LSB 0 5567 #define CSR_SEQUENCEREG0B9S0_MASK GENMASK_32(15, 0) 5568 /* CSR_SEQUENCEREG0B9S1 */ 5569 #define CSR_SEQUENCEREG0B9S1_LSB 0 5570 #define CSR_SEQUENCEREG0B9S1_MASK GENMASK_32(15, 0) 5571 /* CSR_SEQUENCEREG0B9S2 */ 5572 #define CSR_SEQUENCEREG0B9S2_LSB 0 5573 #define CSR_SEQUENCEREG0B9S2_MASK GENMASK_32(8, 0) 5574 /* CSR_SEQUENCEREG0B10S0 */ 5575 #define CSR_SEQUENCEREG0B10S0_LSB 0 5576 #define CSR_SEQUENCEREG0B10S0_MASK GENMASK_32(15, 0) 5577 /* CSR_SEQUENCEREG0B10S1 */ 5578 #define CSR_SEQUENCEREG0B10S1_LSB 0 5579 #define CSR_SEQUENCEREG0B10S1_MASK GENMASK_32(15, 0) 5580 /* CSR_SEQUENCEREG0B10S2 */ 5581 #define CSR_SEQUENCEREG0B10S2_LSB 0 5582 #define CSR_SEQUENCEREG0B10S2_MASK GENMASK_32(8, 0) 5583 /* CSR_SEQUENCEREG0B11S0 */ 5584 #define CSR_SEQUENCEREG0B11S0_LSB 0 5585 #define CSR_SEQUENCEREG0B11S0_MASK GENMASK_32(15, 0) 5586 /* CSR_SEQUENCEREG0B11S1 */ 5587 #define CSR_SEQUENCEREG0B11S1_LSB 0 5588 #define CSR_SEQUENCEREG0B11S1_MASK GENMASK_32(15, 0) 5589 /* CSR_SEQUENCEREG0B11S2 */ 5590 #define CSR_SEQUENCEREG0B11S2_LSB 0 5591 #define CSR_SEQUENCEREG0B11S2_MASK GENMASK_32(8, 0) 5592 /* CSR_SEQUENCEREG0B12S0 */ 5593 #define CSR_SEQUENCEREG0B12S0_LSB 0 5594 #define CSR_SEQUENCEREG0B12S0_MASK GENMASK_32(15, 0) 5595 /* CSR_SEQUENCEREG0B12S1 */ 5596 #define CSR_SEQUENCEREG0B12S1_LSB 0 5597 #define CSR_SEQUENCEREG0B12S1_MASK GENMASK_32(15, 0) 5598 /* CSR_SEQUENCEREG0B12S2 */ 5599 #define CSR_SEQUENCEREG0B12S2_LSB 0 5600 #define CSR_SEQUENCEREG0B12S2_MASK GENMASK_32(8, 0) 5601 /* CSR_SEQUENCEREG0B13S0 */ 5602 #define CSR_SEQUENCEREG0B13S0_LSB 0 5603 #define CSR_SEQUENCEREG0B13S0_MASK GENMASK_32(15, 0) 5604 /* CSR_SEQUENCEREG0B13S1 */ 5605 #define CSR_SEQUENCEREG0B13S1_LSB 0 5606 #define CSR_SEQUENCEREG0B13S1_MASK GENMASK_32(15, 0) 5607 /* CSR_SEQUENCEREG0B13S2 */ 5608 #define CSR_SEQUENCEREG0B13S2_LSB 0 5609 #define CSR_SEQUENCEREG0B13S2_MASK GENMASK_32(8, 0) 5610 /* CSR_SEQUENCEREG0B14S0 */ 5611 #define CSR_SEQUENCEREG0B14S0_LSB 0 5612 #define CSR_SEQUENCEREG0B14S0_MASK GENMASK_32(15, 0) 5613 /* CSR_SEQUENCEREG0B14S1 */ 5614 #define CSR_SEQUENCEREG0B14S1_LSB 0 5615 #define CSR_SEQUENCEREG0B14S1_MASK GENMASK_32(15, 0) 5616 /* CSR_SEQUENCEREG0B14S2 */ 5617 #define CSR_SEQUENCEREG0B14S2_LSB 0 5618 #define CSR_SEQUENCEREG0B14S2_MASK GENMASK_32(8, 0) 5619 /* CSR_SEQUENCEREG0B15S0 */ 5620 #define CSR_SEQUENCEREG0B15S0_LSB 0 5621 #define CSR_SEQUENCEREG0B15S0_MASK GENMASK_32(15, 0) 5622 /* CSR_SEQUENCEREG0B15S1 */ 5623 #define CSR_SEQUENCEREG0B15S1_LSB 0 5624 #define CSR_SEQUENCEREG0B15S1_MASK GENMASK_32(15, 0) 5625 /* CSR_SEQUENCEREG0B15S2 */ 5626 #define CSR_SEQUENCEREG0B15S2_LSB 0 5627 #define CSR_SEQUENCEREG0B15S2_MASK GENMASK_32(8, 0) 5628 /* CSR_SEQUENCEREG0B16S0 */ 5629 #define CSR_SEQUENCEREG0B16S0_LSB 0 5630 #define CSR_SEQUENCEREG0B16S0_MASK GENMASK_32(15, 0) 5631 /* CSR_SEQUENCEREG0B16S1 */ 5632 #define CSR_SEQUENCEREG0B16S1_LSB 0 5633 #define CSR_SEQUENCEREG0B16S1_MASK GENMASK_32(15, 0) 5634 /* CSR_SEQUENCEREG0B16S2 */ 5635 #define CSR_SEQUENCEREG0B16S2_LSB 0 5636 #define CSR_SEQUENCEREG0B16S2_MASK GENMASK_32(8, 0) 5637 /* CSR_SEQUENCEREG0B17S0 */ 5638 #define CSR_SEQUENCEREG0B17S0_LSB 0 5639 #define CSR_SEQUENCEREG0B17S0_MASK GENMASK_32(15, 0) 5640 /* CSR_SEQUENCEREG0B17S1 */ 5641 #define CSR_SEQUENCEREG0B17S1_LSB 0 5642 #define CSR_SEQUENCEREG0B17S1_MASK GENMASK_32(15, 0) 5643 /* CSR_SEQUENCEREG0B17S2 */ 5644 #define CSR_SEQUENCEREG0B17S2_LSB 0 5645 #define CSR_SEQUENCEREG0B17S2_MASK GENMASK_32(8, 0) 5646 /* CSR_SEQUENCEREG0B18S0 */ 5647 #define CSR_SEQUENCEREG0B18S0_LSB 0 5648 #define CSR_SEQUENCEREG0B18S0_MASK GENMASK_32(15, 0) 5649 /* CSR_SEQUENCEREG0B18S1 */ 5650 #define CSR_SEQUENCEREG0B18S1_LSB 0 5651 #define CSR_SEQUENCEREG0B18S1_MASK GENMASK_32(15, 0) 5652 /* CSR_SEQUENCEREG0B18S2 */ 5653 #define CSR_SEQUENCEREG0B18S2_LSB 0 5654 #define CSR_SEQUENCEREG0B18S2_MASK GENMASK_32(8, 0) 5655 /* CSR_SEQUENCEREG0B19S0 */ 5656 #define CSR_SEQUENCEREG0B19S0_LSB 0 5657 #define CSR_SEQUENCEREG0B19S0_MASK GENMASK_32(15, 0) 5658 /* CSR_SEQUENCEREG0B19S1 */ 5659 #define CSR_SEQUENCEREG0B19S1_LSB 0 5660 #define CSR_SEQUENCEREG0B19S1_MASK GENMASK_32(15, 0) 5661 /* CSR_SEQUENCEREG0B19S2 */ 5662 #define CSR_SEQUENCEREG0B19S2_LSB 0 5663 #define CSR_SEQUENCEREG0B19S2_MASK GENMASK_32(8, 0) 5664 /* CSR_SEQUENCEREG0B20S0 */ 5665 #define CSR_SEQUENCEREG0B20S0_LSB 0 5666 #define CSR_SEQUENCEREG0B20S0_MASK GENMASK_32(15, 0) 5667 /* CSR_SEQUENCEREG0B20S1 */ 5668 #define CSR_SEQUENCEREG0B20S1_LSB 0 5669 #define CSR_SEQUENCEREG0B20S1_MASK GENMASK_32(15, 0) 5670 /* CSR_SEQUENCEREG0B20S2 */ 5671 #define CSR_SEQUENCEREG0B20S2_LSB 0 5672 #define CSR_SEQUENCEREG0B20S2_MASK GENMASK_32(8, 0) 5673 /* CSR_SEQUENCEREG0B21S0 */ 5674 #define CSR_SEQUENCEREG0B21S0_LSB 0 5675 #define CSR_SEQUENCEREG0B21S0_MASK GENMASK_32(15, 0) 5676 /* CSR_SEQUENCEREG0B21S1 */ 5677 #define CSR_SEQUENCEREG0B21S1_LSB 0 5678 #define CSR_SEQUENCEREG0B21S1_MASK GENMASK_32(15, 0) 5679 /* CSR_SEQUENCEREG0B21S2 */ 5680 #define CSR_SEQUENCEREG0B21S2_LSB 0 5681 #define CSR_SEQUENCEREG0B21S2_MASK GENMASK_32(8, 0) 5682 /* CSR_SEQUENCEREG0B22S0 */ 5683 #define CSR_SEQUENCEREG0B22S0_LSB 0 5684 #define CSR_SEQUENCEREG0B22S0_MASK GENMASK_32(15, 0) 5685 /* CSR_SEQUENCEREG0B22S1 */ 5686 #define CSR_SEQUENCEREG0B22S1_LSB 0 5687 #define CSR_SEQUENCEREG0B22S1_MASK GENMASK_32(15, 0) 5688 /* CSR_SEQUENCEREG0B22S2 */ 5689 #define CSR_SEQUENCEREG0B22S2_LSB 0 5690 #define CSR_SEQUENCEREG0B22S2_MASK GENMASK_32(8, 0) 5691 /* CSR_SEQUENCEREG0B23S0 */ 5692 #define CSR_SEQUENCEREG0B23S0_LSB 0 5693 #define CSR_SEQUENCEREG0B23S0_MASK GENMASK_32(15, 0) 5694 /* CSR_SEQUENCEREG0B23S1 */ 5695 #define CSR_SEQUENCEREG0B23S1_LSB 0 5696 #define CSR_SEQUENCEREG0B23S1_MASK GENMASK_32(15, 0) 5697 /* CSR_SEQUENCEREG0B23S2 */ 5698 #define CSR_SEQUENCEREG0B23S2_LSB 0 5699 #define CSR_SEQUENCEREG0B23S2_MASK GENMASK_32(8, 0) 5700 /* CSR_SEQUENCEREG0B24S0 */ 5701 #define CSR_SEQUENCEREG0B24S0_LSB 0 5702 #define CSR_SEQUENCEREG0B24S0_MASK GENMASK_32(15, 0) 5703 /* CSR_SEQUENCEREG0B24S1 */ 5704 #define CSR_SEQUENCEREG0B24S1_LSB 0 5705 #define CSR_SEQUENCEREG0B24S1_MASK GENMASK_32(15, 0) 5706 /* CSR_SEQUENCEREG0B24S2 */ 5707 #define CSR_SEQUENCEREG0B24S2_LSB 0 5708 #define CSR_SEQUENCEREG0B24S2_MASK GENMASK_32(8, 0) 5709 /* CSR_SEQUENCEREG0B25S0 */ 5710 #define CSR_SEQUENCEREG0B25S0_LSB 0 5711 #define CSR_SEQUENCEREG0B25S0_MASK GENMASK_32(15, 0) 5712 /* CSR_SEQUENCEREG0B25S1 */ 5713 #define CSR_SEQUENCEREG0B25S1_LSB 0 5714 #define CSR_SEQUENCEREG0B25S1_MASK GENMASK_32(15, 0) 5715 /* CSR_SEQUENCEREG0B25S2 */ 5716 #define CSR_SEQUENCEREG0B25S2_LSB 0 5717 #define CSR_SEQUENCEREG0B25S2_MASK GENMASK_32(8, 0) 5718 /* CSR_SEQUENCEREG0B26S0 */ 5719 #define CSR_SEQUENCEREG0B26S0_LSB 0 5720 #define CSR_SEQUENCEREG0B26S0_MASK GENMASK_32(15, 0) 5721 /* CSR_SEQUENCEREG0B26S1 */ 5722 #define CSR_SEQUENCEREG0B26S1_LSB 0 5723 #define CSR_SEQUENCEREG0B26S1_MASK GENMASK_32(15, 0) 5724 /* CSR_SEQUENCEREG0B26S2 */ 5725 #define CSR_SEQUENCEREG0B26S2_LSB 0 5726 #define CSR_SEQUENCEREG0B26S2_MASK GENMASK_32(8, 0) 5727 /* CSR_SEQUENCEREG0B27S0 */ 5728 #define CSR_SEQUENCEREG0B27S0_LSB 0 5729 #define CSR_SEQUENCEREG0B27S0_MASK GENMASK_32(15, 0) 5730 /* CSR_SEQUENCEREG0B27S1 */ 5731 #define CSR_SEQUENCEREG0B27S1_LSB 0 5732 #define CSR_SEQUENCEREG0B27S1_MASK GENMASK_32(15, 0) 5733 /* CSR_SEQUENCEREG0B27S2 */ 5734 #define CSR_SEQUENCEREG0B27S2_LSB 0 5735 #define CSR_SEQUENCEREG0B27S2_MASK GENMASK_32(8, 0) 5736 /* CSR_SEQUENCEREG0B28S0 */ 5737 #define CSR_SEQUENCEREG0B28S0_LSB 0 5738 #define CSR_SEQUENCEREG0B28S0_MASK GENMASK_32(15, 0) 5739 /* CSR_SEQUENCEREG0B28S1 */ 5740 #define CSR_SEQUENCEREG0B28S1_LSB 0 5741 #define CSR_SEQUENCEREG0B28S1_MASK GENMASK_32(15, 0) 5742 /* CSR_SEQUENCEREG0B28S2 */ 5743 #define CSR_SEQUENCEREG0B28S2_LSB 0 5744 #define CSR_SEQUENCEREG0B28S2_MASK GENMASK_32(8, 0) 5745 /* CSR_SEQUENCEREG0B29S0 */ 5746 #define CSR_SEQUENCEREG0B29S0_LSB 0 5747 #define CSR_SEQUENCEREG0B29S0_MASK GENMASK_32(15, 0) 5748 /* CSR_SEQUENCEREG0B29S1 */ 5749 #define CSR_SEQUENCEREG0B29S1_LSB 0 5750 #define CSR_SEQUENCEREG0B29S1_MASK GENMASK_32(15, 0) 5751 /* CSR_SEQUENCEREG0B29S2 */ 5752 #define CSR_SEQUENCEREG0B29S2_LSB 0 5753 #define CSR_SEQUENCEREG0B29S2_MASK GENMASK_32(8, 0) 5754 /* CSR_SEQUENCEREG0B30S0 */ 5755 #define CSR_SEQUENCEREG0B30S0_LSB 0 5756 #define CSR_SEQUENCEREG0B30S0_MASK GENMASK_32(15, 0) 5757 /* CSR_SEQUENCEREG0B30S1 */ 5758 #define CSR_SEQUENCEREG0B30S1_LSB 0 5759 #define CSR_SEQUENCEREG0B30S1_MASK GENMASK_32(15, 0) 5760 /* CSR_SEQUENCEREG0B30S2 */ 5761 #define CSR_SEQUENCEREG0B30S2_LSB 0 5762 #define CSR_SEQUENCEREG0B30S2_MASK GENMASK_32(8, 0) 5763 /* CSR_SEQUENCEREG0B31S0 */ 5764 #define CSR_SEQUENCEREG0B31S0_LSB 0 5765 #define CSR_SEQUENCEREG0B31S0_MASK GENMASK_32(15, 0) 5766 /* CSR_SEQUENCEREG0B31S1 */ 5767 #define CSR_SEQUENCEREG0B31S1_LSB 0 5768 #define CSR_SEQUENCEREG0B31S1_MASK GENMASK_32(15, 0) 5769 /* CSR_SEQUENCEREG0B31S2 */ 5770 #define CSR_SEQUENCEREG0B31S2_LSB 0 5771 #define CSR_SEQUENCEREG0B31S2_MASK GENMASK_32(8, 0) 5772 /* CSR_SEQUENCEREG0B32S0 */ 5773 #define CSR_SEQUENCEREG0B32S0_LSB 0 5774 #define CSR_SEQUENCEREG0B32S0_MASK GENMASK_32(15, 0) 5775 /* CSR_SEQUENCEREG0B32S1 */ 5776 #define CSR_SEQUENCEREG0B32S1_LSB 0 5777 #define CSR_SEQUENCEREG0B32S1_MASK GENMASK_32(15, 0) 5778 /* CSR_SEQUENCEREG0B32S2 */ 5779 #define CSR_SEQUENCEREG0B32S2_LSB 0 5780 #define CSR_SEQUENCEREG0B32S2_MASK GENMASK_32(8, 0) 5781 /* CSR_SEQUENCEREG0B33S0 */ 5782 #define CSR_SEQUENCEREG0B33S0_LSB 0 5783 #define CSR_SEQUENCEREG0B33S0_MASK GENMASK_32(15, 0) 5784 /* CSR_SEQUENCEREG0B33S1 */ 5785 #define CSR_SEQUENCEREG0B33S1_LSB 0 5786 #define CSR_SEQUENCEREG0B33S1_MASK GENMASK_32(15, 0) 5787 /* CSR_SEQUENCEREG0B33S2 */ 5788 #define CSR_SEQUENCEREG0B33S2_LSB 0 5789 #define CSR_SEQUENCEREG0B33S2_MASK GENMASK_32(8, 0) 5790 /* CSR_SEQUENCEREG0B34S0 */ 5791 #define CSR_SEQUENCEREG0B34S0_LSB 0 5792 #define CSR_SEQUENCEREG0B34S0_MASK GENMASK_32(15, 0) 5793 /* CSR_SEQUENCEREG0B34S1 */ 5794 #define CSR_SEQUENCEREG0B34S1_LSB 0 5795 #define CSR_SEQUENCEREG0B34S1_MASK GENMASK_32(15, 0) 5796 /* CSR_SEQUENCEREG0B34S2 */ 5797 #define CSR_SEQUENCEREG0B34S2_LSB 0 5798 #define CSR_SEQUENCEREG0B34S2_MASK GENMASK_32(8, 0) 5799 /* CSR_SEQUENCEREG0B35S0 */ 5800 #define CSR_SEQUENCEREG0B35S0_LSB 0 5801 #define CSR_SEQUENCEREG0B35S0_MASK GENMASK_32(15, 0) 5802 /* CSR_SEQUENCEREG0B35S1 */ 5803 #define CSR_SEQUENCEREG0B35S1_LSB 0 5804 #define CSR_SEQUENCEREG0B35S1_MASK GENMASK_32(15, 0) 5805 /* CSR_SEQUENCEREG0B35S2 */ 5806 #define CSR_SEQUENCEREG0B35S2_LSB 0 5807 #define CSR_SEQUENCEREG0B35S2_MASK GENMASK_32(8, 0) 5808 /* CSR_SEQUENCEREG0B36S0 */ 5809 #define CSR_SEQUENCEREG0B36S0_LSB 0 5810 #define CSR_SEQUENCEREG0B36S0_MASK GENMASK_32(15, 0) 5811 /* CSR_SEQUENCEREG0B36S1 */ 5812 #define CSR_SEQUENCEREG0B36S1_LSB 0 5813 #define CSR_SEQUENCEREG0B36S1_MASK GENMASK_32(15, 0) 5814 /* CSR_SEQUENCEREG0B36S2 */ 5815 #define CSR_SEQUENCEREG0B36S2_LSB 0 5816 #define CSR_SEQUENCEREG0B36S2_MASK GENMASK_32(8, 0) 5817 /* CSR_SEQUENCEREG0B37S0 */ 5818 #define CSR_SEQUENCEREG0B37S0_LSB 0 5819 #define CSR_SEQUENCEREG0B37S0_MASK GENMASK_32(15, 0) 5820 /* CSR_SEQUENCEREG0B37S1 */ 5821 #define CSR_SEQUENCEREG0B37S1_LSB 0 5822 #define CSR_SEQUENCEREG0B37S1_MASK GENMASK_32(15, 0) 5823 /* CSR_SEQUENCEREG0B37S2 */ 5824 #define CSR_SEQUENCEREG0B37S2_LSB 0 5825 #define CSR_SEQUENCEREG0B37S2_MASK GENMASK_32(8, 0) 5826 /* CSR_SEQUENCEREG0B38S0 */ 5827 #define CSR_SEQUENCEREG0B38S0_LSB 0 5828 #define CSR_SEQUENCEREG0B38S0_MASK GENMASK_32(15, 0) 5829 /* CSR_SEQUENCEREG0B38S1 */ 5830 #define CSR_SEQUENCEREG0B38S1_LSB 0 5831 #define CSR_SEQUENCEREG0B38S1_MASK GENMASK_32(15, 0) 5832 /* CSR_SEQUENCEREG0B38S2 */ 5833 #define CSR_SEQUENCEREG0B38S2_LSB 0 5834 #define CSR_SEQUENCEREG0B38S2_MASK GENMASK_32(8, 0) 5835 /* CSR_SEQUENCEREG0B39S0 */ 5836 #define CSR_SEQUENCEREG0B39S0_LSB 0 5837 #define CSR_SEQUENCEREG0B39S0_MASK GENMASK_32(15, 0) 5838 /* CSR_SEQUENCEREG0B39S1 */ 5839 #define CSR_SEQUENCEREG0B39S1_LSB 0 5840 #define CSR_SEQUENCEREG0B39S1_MASK GENMASK_32(15, 0) 5841 /* CSR_SEQUENCEREG0B39S2 */ 5842 #define CSR_SEQUENCEREG0B39S2_LSB 0 5843 #define CSR_SEQUENCEREG0B39S2_MASK GENMASK_32(8, 0) 5844 /* CSR_SEQUENCEREG0B40S0 */ 5845 #define CSR_SEQUENCEREG0B40S0_LSB 0 5846 #define CSR_SEQUENCEREG0B40S0_MASK GENMASK_32(15, 0) 5847 /* CSR_SEQUENCEREG0B40S1 */ 5848 #define CSR_SEQUENCEREG0B40S1_LSB 0 5849 #define CSR_SEQUENCEREG0B40S1_MASK GENMASK_32(15, 0) 5850 /* CSR_SEQUENCEREG0B40S2 */ 5851 #define CSR_SEQUENCEREG0B40S2_LSB 0 5852 #define CSR_SEQUENCEREG0B40S2_MASK GENMASK_32(8, 0) 5853 /* CSR_SEQUENCEREG0B41S0 */ 5854 #define CSR_SEQUENCEREG0B41S0_LSB 0 5855 #define CSR_SEQUENCEREG0B41S0_MASK GENMASK_32(15, 0) 5856 /* CSR_SEQUENCEREG0B41S1 */ 5857 #define CSR_SEQUENCEREG0B41S1_LSB 0 5858 #define CSR_SEQUENCEREG0B41S1_MASK GENMASK_32(15, 0) 5859 /* CSR_SEQUENCEREG0B41S2 */ 5860 #define CSR_SEQUENCEREG0B41S2_LSB 0 5861 #define CSR_SEQUENCEREG0B41S2_MASK GENMASK_32(8, 0) 5862 /* CSR_SEQUENCEREG0B42S0 */ 5863 #define CSR_SEQUENCEREG0B42S0_LSB 0 5864 #define CSR_SEQUENCEREG0B42S0_MASK GENMASK_32(15, 0) 5865 /* CSR_SEQUENCEREG0B42S1 */ 5866 #define CSR_SEQUENCEREG0B42S1_LSB 0 5867 #define CSR_SEQUENCEREG0B42S1_MASK GENMASK_32(15, 0) 5868 /* CSR_SEQUENCEREG0B42S2 */ 5869 #define CSR_SEQUENCEREG0B42S2_LSB 0 5870 #define CSR_SEQUENCEREG0B42S2_MASK GENMASK_32(8, 0) 5871 /* CSR_SEQUENCEREG0B43S0 */ 5872 #define CSR_SEQUENCEREG0B43S0_LSB 0 5873 #define CSR_SEQUENCEREG0B43S0_MASK GENMASK_32(15, 0) 5874 /* CSR_SEQUENCEREG0B43S1 */ 5875 #define CSR_SEQUENCEREG0B43S1_LSB 0 5876 #define CSR_SEQUENCEREG0B43S1_MASK GENMASK_32(15, 0) 5877 /* CSR_SEQUENCEREG0B43S2 */ 5878 #define CSR_SEQUENCEREG0B43S2_LSB 0 5879 #define CSR_SEQUENCEREG0B43S2_MASK GENMASK_32(8, 0) 5880 /* CSR_SEQUENCEREG0B44S0 */ 5881 #define CSR_SEQUENCEREG0B44S0_LSB 0 5882 #define CSR_SEQUENCEREG0B44S0_MASK GENMASK_32(15, 0) 5883 /* CSR_SEQUENCEREG0B44S1 */ 5884 #define CSR_SEQUENCEREG0B44S1_LSB 0 5885 #define CSR_SEQUENCEREG0B44S1_MASK GENMASK_32(15, 0) 5886 /* CSR_SEQUENCEREG0B44S2 */ 5887 #define CSR_SEQUENCEREG0B44S2_LSB 0 5888 #define CSR_SEQUENCEREG0B44S2_MASK GENMASK_32(8, 0) 5889 /* CSR_SEQUENCEREG0B45S0 */ 5890 #define CSR_SEQUENCEREG0B45S0_LSB 0 5891 #define CSR_SEQUENCEREG0B45S0_MASK GENMASK_32(15, 0) 5892 /* CSR_SEQUENCEREG0B45S1 */ 5893 #define CSR_SEQUENCEREG0B45S1_LSB 0 5894 #define CSR_SEQUENCEREG0B45S1_MASK GENMASK_32(15, 0) 5895 /* CSR_SEQUENCEREG0B45S2 */ 5896 #define CSR_SEQUENCEREG0B45S2_LSB 0 5897 #define CSR_SEQUENCEREG0B45S2_MASK GENMASK_32(8, 0) 5898 /* CSR_SEQUENCEREG0B46S0 */ 5899 #define CSR_SEQUENCEREG0B46S0_LSB 0 5900 #define CSR_SEQUENCEREG0B46S0_MASK GENMASK_32(15, 0) 5901 /* CSR_SEQUENCEREG0B46S1 */ 5902 #define CSR_SEQUENCEREG0B46S1_LSB 0 5903 #define CSR_SEQUENCEREG0B46S1_MASK GENMASK_32(15, 0) 5904 /* CSR_SEQUENCEREG0B46S2 */ 5905 #define CSR_SEQUENCEREG0B46S2_LSB 0 5906 #define CSR_SEQUENCEREG0B46S2_MASK GENMASK_32(8, 0) 5907 /* CSR_SEQUENCEREG0B47S0 */ 5908 #define CSR_SEQUENCEREG0B47S0_LSB 0 5909 #define CSR_SEQUENCEREG0B47S0_MASK GENMASK_32(15, 0) 5910 /* CSR_SEQUENCEREG0B47S1 */ 5911 #define CSR_SEQUENCEREG0B47S1_LSB 0 5912 #define CSR_SEQUENCEREG0B47S1_MASK GENMASK_32(15, 0) 5913 /* CSR_SEQUENCEREG0B47S2 */ 5914 #define CSR_SEQUENCEREG0B47S2_LSB 0 5915 #define CSR_SEQUENCEREG0B47S2_MASK GENMASK_32(8, 0) 5916 /* CSR_SEQUENCEREG0B48S0 */ 5917 #define CSR_SEQUENCEREG0B48S0_LSB 0 5918 #define CSR_SEQUENCEREG0B48S0_MASK GENMASK_32(15, 0) 5919 /* CSR_SEQUENCEREG0B48S1 */ 5920 #define CSR_SEQUENCEREG0B48S1_LSB 0 5921 #define CSR_SEQUENCEREG0B48S1_MASK GENMASK_32(15, 0) 5922 /* CSR_SEQUENCEREG0B48S2 */ 5923 #define CSR_SEQUENCEREG0B48S2_LSB 0 5924 #define CSR_SEQUENCEREG0B48S2_MASK GENMASK_32(8, 0) 5925 /* CSR_SEQUENCEREG0B49S0 */ 5926 #define CSR_SEQUENCEREG0B49S0_LSB 0 5927 #define CSR_SEQUENCEREG0B49S0_MASK GENMASK_32(15, 0) 5928 /* CSR_SEQUENCEREG0B49S1 */ 5929 #define CSR_SEQUENCEREG0B49S1_LSB 0 5930 #define CSR_SEQUENCEREG0B49S1_MASK GENMASK_32(15, 0) 5931 /* CSR_SEQUENCEREG0B49S2 */ 5932 #define CSR_SEQUENCEREG0B49S2_LSB 0 5933 #define CSR_SEQUENCEREG0B49S2_MASK GENMASK_32(8, 0) 5934 /* CSR_SEQUENCEREG0B50S0 */ 5935 #define CSR_SEQUENCEREG0B50S0_LSB 0 5936 #define CSR_SEQUENCEREG0B50S0_MASK GENMASK_32(15, 0) 5937 /* CSR_SEQUENCEREG0B50S1 */ 5938 #define CSR_SEQUENCEREG0B50S1_LSB 0 5939 #define CSR_SEQUENCEREG0B50S1_MASK GENMASK_32(15, 0) 5940 /* CSR_SEQUENCEREG0B50S2 */ 5941 #define CSR_SEQUENCEREG0B50S2_LSB 0 5942 #define CSR_SEQUENCEREG0B50S2_MASK GENMASK_32(8, 0) 5943 /* CSR_SEQUENCEREG0B51S0 */ 5944 #define CSR_SEQUENCEREG0B51S0_LSB 0 5945 #define CSR_SEQUENCEREG0B51S0_MASK GENMASK_32(15, 0) 5946 /* CSR_SEQUENCEREG0B51S1 */ 5947 #define CSR_SEQUENCEREG0B51S1_LSB 0 5948 #define CSR_SEQUENCEREG0B51S1_MASK GENMASK_32(15, 0) 5949 /* CSR_SEQUENCEREG0B51S2 */ 5950 #define CSR_SEQUENCEREG0B51S2_LSB 0 5951 #define CSR_SEQUENCEREG0B51S2_MASK GENMASK_32(8, 0) 5952 /* CSR_SEQUENCEREG0B52S0 */ 5953 #define CSR_SEQUENCEREG0B52S0_LSB 0 5954 #define CSR_SEQUENCEREG0B52S0_MASK GENMASK_32(15, 0) 5955 /* CSR_SEQUENCEREG0B52S1 */ 5956 #define CSR_SEQUENCEREG0B52S1_LSB 0 5957 #define CSR_SEQUENCEREG0B52S1_MASK GENMASK_32(15, 0) 5958 /* CSR_SEQUENCEREG0B52S2 */ 5959 #define CSR_SEQUENCEREG0B52S2_LSB 0 5960 #define CSR_SEQUENCEREG0B52S2_MASK GENMASK_32(8, 0) 5961 /* CSR_SEQUENCEREG0B53S0 */ 5962 #define CSR_SEQUENCEREG0B53S0_LSB 0 5963 #define CSR_SEQUENCEREG0B53S0_MASK GENMASK_32(15, 0) 5964 /* CSR_SEQUENCEREG0B53S1 */ 5965 #define CSR_SEQUENCEREG0B53S1_LSB 0 5966 #define CSR_SEQUENCEREG0B53S1_MASK GENMASK_32(15, 0) 5967 /* CSR_SEQUENCEREG0B53S2 */ 5968 #define CSR_SEQUENCEREG0B53S2_LSB 0 5969 #define CSR_SEQUENCEREG0B53S2_MASK GENMASK_32(8, 0) 5970 /* CSR_SEQUENCEREG0B54S0 */ 5971 #define CSR_SEQUENCEREG0B54S0_LSB 0 5972 #define CSR_SEQUENCEREG0B54S0_MASK GENMASK_32(15, 0) 5973 /* CSR_SEQUENCEREG0B54S1 */ 5974 #define CSR_SEQUENCEREG0B54S1_LSB 0 5975 #define CSR_SEQUENCEREG0B54S1_MASK GENMASK_32(15, 0) 5976 /* CSR_SEQUENCEREG0B54S2 */ 5977 #define CSR_SEQUENCEREG0B54S2_LSB 0 5978 #define CSR_SEQUENCEREG0B54S2_MASK GENMASK_32(8, 0) 5979 /* CSR_SEQUENCEREG0B55S0 */ 5980 #define CSR_SEQUENCEREG0B55S0_LSB 0 5981 #define CSR_SEQUENCEREG0B55S0_MASK GENMASK_32(15, 0) 5982 /* CSR_SEQUENCEREG0B55S1 */ 5983 #define CSR_SEQUENCEREG0B55S1_LSB 0 5984 #define CSR_SEQUENCEREG0B55S1_MASK GENMASK_32(15, 0) 5985 /* CSR_SEQUENCEREG0B55S2 */ 5986 #define CSR_SEQUENCEREG0B55S2_LSB 0 5987 #define CSR_SEQUENCEREG0B55S2_MASK GENMASK_32(8, 0) 5988 /* CSR_SEQUENCEREG0B56S0 */ 5989 #define CSR_SEQUENCEREG0B56S0_LSB 0 5990 #define CSR_SEQUENCEREG0B56S0_MASK GENMASK_32(15, 0) 5991 /* CSR_SEQUENCEREG0B56S1 */ 5992 #define CSR_SEQUENCEREG0B56S1_LSB 0 5993 #define CSR_SEQUENCEREG0B56S1_MASK GENMASK_32(15, 0) 5994 /* CSR_SEQUENCEREG0B56S2 */ 5995 #define CSR_SEQUENCEREG0B56S2_LSB 0 5996 #define CSR_SEQUENCEREG0B56S2_MASK GENMASK_32(8, 0) 5997 /* CSR_SEQUENCEREG0B57S0 */ 5998 #define CSR_SEQUENCEREG0B57S0_LSB 0 5999 #define CSR_SEQUENCEREG0B57S0_MASK GENMASK_32(15, 0) 6000 /* CSR_SEQUENCEREG0B57S1 */ 6001 #define CSR_SEQUENCEREG0B57S1_LSB 0 6002 #define CSR_SEQUENCEREG0B57S1_MASK GENMASK_32(15, 0) 6003 /* CSR_SEQUENCEREG0B57S2 */ 6004 #define CSR_SEQUENCEREG0B57S2_LSB 0 6005 #define CSR_SEQUENCEREG0B57S2_MASK GENMASK_32(8, 0) 6006 /* CSR_SEQUENCEREG0B58S0 */ 6007 #define CSR_SEQUENCEREG0B58S0_LSB 0 6008 #define CSR_SEQUENCEREG0B58S0_MASK GENMASK_32(15, 0) 6009 /* CSR_SEQUENCEREG0B58S1 */ 6010 #define CSR_SEQUENCEREG0B58S1_LSB 0 6011 #define CSR_SEQUENCEREG0B58S1_MASK GENMASK_32(15, 0) 6012 /* CSR_SEQUENCEREG0B58S2 */ 6013 #define CSR_SEQUENCEREG0B58S2_LSB 0 6014 #define CSR_SEQUENCEREG0B58S2_MASK GENMASK_32(8, 0) 6015 /* CSR_SEQUENCEREG0B59S0 */ 6016 #define CSR_SEQUENCEREG0B59S0_LSB 0 6017 #define CSR_SEQUENCEREG0B59S0_MASK GENMASK_32(15, 0) 6018 /* CSR_SEQUENCEREG0B59S1 */ 6019 #define CSR_SEQUENCEREG0B59S1_LSB 0 6020 #define CSR_SEQUENCEREG0B59S1_MASK GENMASK_32(15, 0) 6021 /* CSR_SEQUENCEREG0B59S2 */ 6022 #define CSR_SEQUENCEREG0B59S2_LSB 0 6023 #define CSR_SEQUENCEREG0B59S2_MASK GENMASK_32(8, 0) 6024 /* CSR_SEQUENCEREG0B60S0 */ 6025 #define CSR_SEQUENCEREG0B60S0_LSB 0 6026 #define CSR_SEQUENCEREG0B60S0_MASK GENMASK_32(15, 0) 6027 /* CSR_SEQUENCEREG0B60S1 */ 6028 #define CSR_SEQUENCEREG0B60S1_LSB 0 6029 #define CSR_SEQUENCEREG0B60S1_MASK GENMASK_32(15, 0) 6030 /* CSR_SEQUENCEREG0B60S2 */ 6031 #define CSR_SEQUENCEREG0B60S2_LSB 0 6032 #define CSR_SEQUENCEREG0B60S2_MASK GENMASK_32(8, 0) 6033 /* CSR_SEQUENCEREG0B61S0 */ 6034 #define CSR_SEQUENCEREG0B61S0_LSB 0 6035 #define CSR_SEQUENCEREG0B61S0_MASK GENMASK_32(15, 0) 6036 /* CSR_SEQUENCEREG0B61S1 */ 6037 #define CSR_SEQUENCEREG0B61S1_LSB 0 6038 #define CSR_SEQUENCEREG0B61S1_MASK GENMASK_32(15, 0) 6039 /* CSR_SEQUENCEREG0B61S2 */ 6040 #define CSR_SEQUENCEREG0B61S2_LSB 0 6041 #define CSR_SEQUENCEREG0B61S2_MASK GENMASK_32(8, 0) 6042 /* CSR_SEQUENCEREG0B62S0 */ 6043 #define CSR_SEQUENCEREG0B62S0_LSB 0 6044 #define CSR_SEQUENCEREG0B62S0_MASK GENMASK_32(15, 0) 6045 /* CSR_SEQUENCEREG0B62S1 */ 6046 #define CSR_SEQUENCEREG0B62S1_LSB 0 6047 #define CSR_SEQUENCEREG0B62S1_MASK GENMASK_32(15, 0) 6048 /* CSR_SEQUENCEREG0B62S2 */ 6049 #define CSR_SEQUENCEREG0B62S2_LSB 0 6050 #define CSR_SEQUENCEREG0B62S2_MASK GENMASK_32(8, 0) 6051 /* CSR_SEQUENCEREG0B63S0 */ 6052 #define CSR_SEQUENCEREG0B63S0_LSB 0 6053 #define CSR_SEQUENCEREG0B63S0_MASK GENMASK_32(15, 0) 6054 /* CSR_SEQUENCEREG0B63S1 */ 6055 #define CSR_SEQUENCEREG0B63S1_LSB 0 6056 #define CSR_SEQUENCEREG0B63S1_MASK GENMASK_32(15, 0) 6057 /* CSR_SEQUENCEREG0B63S2 */ 6058 #define CSR_SEQUENCEREG0B63S2_LSB 0 6059 #define CSR_SEQUENCEREG0B63S2_MASK GENMASK_32(8, 0) 6060 /* CSR_SEQUENCEREG0B64S0 */ 6061 #define CSR_SEQUENCEREG0B64S0_LSB 0 6062 #define CSR_SEQUENCEREG0B64S0_MASK GENMASK_32(15, 0) 6063 /* CSR_SEQUENCEREG0B64S1 */ 6064 #define CSR_SEQUENCEREG0B64S1_LSB 0 6065 #define CSR_SEQUENCEREG0B64S1_MASK GENMASK_32(15, 0) 6066 /* CSR_SEQUENCEREG0B64S2 */ 6067 #define CSR_SEQUENCEREG0B64S2_LSB 0 6068 #define CSR_SEQUENCEREG0B64S2_MASK GENMASK_32(8, 0) 6069 /* CSR_SEQUENCEREG0B65S0 */ 6070 #define CSR_SEQUENCEREG0B65S0_LSB 0 6071 #define CSR_SEQUENCEREG0B65S0_MASK GENMASK_32(15, 0) 6072 /* CSR_SEQUENCEREG0B65S1 */ 6073 #define CSR_SEQUENCEREG0B65S1_LSB 0 6074 #define CSR_SEQUENCEREG0B65S1_MASK GENMASK_32(15, 0) 6075 /* CSR_SEQUENCEREG0B65S2 */ 6076 #define CSR_SEQUENCEREG0B65S2_LSB 0 6077 #define CSR_SEQUENCEREG0B65S2_MASK GENMASK_32(8, 0) 6078 /* CSR_SEQUENCEREG0B66S0 */ 6079 #define CSR_SEQUENCEREG0B66S0_LSB 0 6080 #define CSR_SEQUENCEREG0B66S0_MASK GENMASK_32(15, 0) 6081 /* CSR_SEQUENCEREG0B66S1 */ 6082 #define CSR_SEQUENCEREG0B66S1_LSB 0 6083 #define CSR_SEQUENCEREG0B66S1_MASK GENMASK_32(15, 0) 6084 /* CSR_SEQUENCEREG0B66S2 */ 6085 #define CSR_SEQUENCEREG0B66S2_LSB 0 6086 #define CSR_SEQUENCEREG0B66S2_MASK GENMASK_32(8, 0) 6087 /* CSR_SEQUENCEREG0B67S0 */ 6088 #define CSR_SEQUENCEREG0B67S0_LSB 0 6089 #define CSR_SEQUENCEREG0B67S0_MASK GENMASK_32(15, 0) 6090 /* CSR_SEQUENCEREG0B67S1 */ 6091 #define CSR_SEQUENCEREG0B67S1_LSB 0 6092 #define CSR_SEQUENCEREG0B67S1_MASK GENMASK_32(15, 0) 6093 /* CSR_SEQUENCEREG0B67S2 */ 6094 #define CSR_SEQUENCEREG0B67S2_LSB 0 6095 #define CSR_SEQUENCEREG0B67S2_MASK GENMASK_32(8, 0) 6096 /* CSR_SEQUENCEREG0B68S0 */ 6097 #define CSR_SEQUENCEREG0B68S0_LSB 0 6098 #define CSR_SEQUENCEREG0B68S0_MASK GENMASK_32(15, 0) 6099 /* CSR_SEQUENCEREG0B68S1 */ 6100 #define CSR_SEQUENCEREG0B68S1_LSB 0 6101 #define CSR_SEQUENCEREG0B68S1_MASK GENMASK_32(15, 0) 6102 /* CSR_SEQUENCEREG0B68S2 */ 6103 #define CSR_SEQUENCEREG0B68S2_LSB 0 6104 #define CSR_SEQUENCEREG0B68S2_MASK GENMASK_32(8, 0) 6105 /* CSR_SEQUENCEREG0B69S0 */ 6106 #define CSR_SEQUENCEREG0B69S0_LSB 0 6107 #define CSR_SEQUENCEREG0B69S0_MASK GENMASK_32(15, 0) 6108 /* CSR_SEQUENCEREG0B69S1 */ 6109 #define CSR_SEQUENCEREG0B69S1_LSB 0 6110 #define CSR_SEQUENCEREG0B69S1_MASK GENMASK_32(15, 0) 6111 /* CSR_SEQUENCEREG0B69S2 */ 6112 #define CSR_SEQUENCEREG0B69S2_LSB 0 6113 #define CSR_SEQUENCEREG0B69S2_MASK GENMASK_32(8, 0) 6114 /* CSR_SEQUENCEREG0B70S0 */ 6115 #define CSR_SEQUENCEREG0B70S0_LSB 0 6116 #define CSR_SEQUENCEREG0B70S0_MASK GENMASK_32(15, 0) 6117 /* CSR_SEQUENCEREG0B70S1 */ 6118 #define CSR_SEQUENCEREG0B70S1_LSB 0 6119 #define CSR_SEQUENCEREG0B70S1_MASK GENMASK_32(15, 0) 6120 /* CSR_SEQUENCEREG0B70S2 */ 6121 #define CSR_SEQUENCEREG0B70S2_LSB 0 6122 #define CSR_SEQUENCEREG0B70S2_MASK GENMASK_32(8, 0) 6123 /* CSR_SEQUENCEREG0B71S0 */ 6124 #define CSR_SEQUENCEREG0B71S0_LSB 0 6125 #define CSR_SEQUENCEREG0B71S0_MASK GENMASK_32(15, 0) 6126 /* CSR_SEQUENCEREG0B71S1 */ 6127 #define CSR_SEQUENCEREG0B71S1_LSB 0 6128 #define CSR_SEQUENCEREG0B71S1_MASK GENMASK_32(15, 0) 6129 /* CSR_SEQUENCEREG0B71S2 */ 6130 #define CSR_SEQUENCEREG0B71S2_LSB 0 6131 #define CSR_SEQUENCEREG0B71S2_MASK GENMASK_32(8, 0) 6132 /* CSR_SEQUENCEREG0B72S0 */ 6133 #define CSR_SEQUENCEREG0B72S0_LSB 0 6134 #define CSR_SEQUENCEREG0B72S0_MASK GENMASK_32(15, 0) 6135 /* CSR_SEQUENCEREG0B72S1 */ 6136 #define CSR_SEQUENCEREG0B72S1_LSB 0 6137 #define CSR_SEQUENCEREG0B72S1_MASK GENMASK_32(15, 0) 6138 /* CSR_SEQUENCEREG0B72S2 */ 6139 #define CSR_SEQUENCEREG0B72S2_LSB 0 6140 #define CSR_SEQUENCEREG0B72S2_MASK GENMASK_32(8, 0) 6141 /* CSR_SEQUENCEREG0B73S0 */ 6142 #define CSR_SEQUENCEREG0B73S0_LSB 0 6143 #define CSR_SEQUENCEREG0B73S0_MASK GENMASK_32(15, 0) 6144 /* CSR_SEQUENCEREG0B73S1 */ 6145 #define CSR_SEQUENCEREG0B73S1_LSB 0 6146 #define CSR_SEQUENCEREG0B73S1_MASK GENMASK_32(15, 0) 6147 /* CSR_SEQUENCEREG0B73S2 */ 6148 #define CSR_SEQUENCEREG0B73S2_LSB 0 6149 #define CSR_SEQUENCEREG0B73S2_MASK GENMASK_32(8, 0) 6150 /* CSR_SEQUENCEREG0B74S0 */ 6151 #define CSR_SEQUENCEREG0B74S0_LSB 0 6152 #define CSR_SEQUENCEREG0B74S0_MASK GENMASK_32(15, 0) 6153 /* CSR_SEQUENCEREG0B74S1 */ 6154 #define CSR_SEQUENCEREG0B74S1_LSB 0 6155 #define CSR_SEQUENCEREG0B74S1_MASK GENMASK_32(15, 0) 6156 /* CSR_SEQUENCEREG0B74S2 */ 6157 #define CSR_SEQUENCEREG0B74S2_LSB 0 6158 #define CSR_SEQUENCEREG0B74S2_MASK GENMASK_32(8, 0) 6159 /* CSR_SEQUENCEREG0B75S0 */ 6160 #define CSR_SEQUENCEREG0B75S0_LSB 0 6161 #define CSR_SEQUENCEREG0B75S0_MASK GENMASK_32(15, 0) 6162 /* CSR_SEQUENCEREG0B75S1 */ 6163 #define CSR_SEQUENCEREG0B75S1_LSB 0 6164 #define CSR_SEQUENCEREG0B75S1_MASK GENMASK_32(15, 0) 6165 /* CSR_SEQUENCEREG0B75S2 */ 6166 #define CSR_SEQUENCEREG0B75S2_LSB 0 6167 #define CSR_SEQUENCEREG0B75S2_MASK GENMASK_32(8, 0) 6168 /* CSR_SEQUENCEREG0B76S0 */ 6169 #define CSR_SEQUENCEREG0B76S0_LSB 0 6170 #define CSR_SEQUENCEREG0B76S0_MASK GENMASK_32(15, 0) 6171 /* CSR_SEQUENCEREG0B76S1 */ 6172 #define CSR_SEQUENCEREG0B76S1_LSB 0 6173 #define CSR_SEQUENCEREG0B76S1_MASK GENMASK_32(15, 0) 6174 /* CSR_SEQUENCEREG0B76S2 */ 6175 #define CSR_SEQUENCEREG0B76S2_LSB 0 6176 #define CSR_SEQUENCEREG0B76S2_MASK GENMASK_32(8, 0) 6177 /* CSR_SEQUENCEREG0B77S0 */ 6178 #define CSR_SEQUENCEREG0B77S0_LSB 0 6179 #define CSR_SEQUENCEREG0B77S0_MASK GENMASK_32(15, 0) 6180 /* CSR_SEQUENCEREG0B77S1 */ 6181 #define CSR_SEQUENCEREG0B77S1_LSB 0 6182 #define CSR_SEQUENCEREG0B77S1_MASK GENMASK_32(15, 0) 6183 /* CSR_SEQUENCEREG0B77S2 */ 6184 #define CSR_SEQUENCEREG0B77S2_LSB 0 6185 #define CSR_SEQUENCEREG0B77S2_MASK GENMASK_32(8, 0) 6186 /* CSR_SEQUENCEREG0B78S0 */ 6187 #define CSR_SEQUENCEREG0B78S0_LSB 0 6188 #define CSR_SEQUENCEREG0B78S0_MASK GENMASK_32(15, 0) 6189 /* CSR_SEQUENCEREG0B78S1 */ 6190 #define CSR_SEQUENCEREG0B78S1_LSB 0 6191 #define CSR_SEQUENCEREG0B78S1_MASK GENMASK_32(15, 0) 6192 /* CSR_SEQUENCEREG0B78S2 */ 6193 #define CSR_SEQUENCEREG0B78S2_LSB 0 6194 #define CSR_SEQUENCEREG0B78S2_MASK GENMASK_32(8, 0) 6195 /* CSR_SEQUENCEREG0B79S0 */ 6196 #define CSR_SEQUENCEREG0B79S0_LSB 0 6197 #define CSR_SEQUENCEREG0B79S0_MASK GENMASK_32(15, 0) 6198 /* CSR_SEQUENCEREG0B79S1 */ 6199 #define CSR_SEQUENCEREG0B79S1_LSB 0 6200 #define CSR_SEQUENCEREG0B79S1_MASK GENMASK_32(15, 0) 6201 /* CSR_SEQUENCEREG0B79S2 */ 6202 #define CSR_SEQUENCEREG0B79S2_LSB 0 6203 #define CSR_SEQUENCEREG0B79S2_MASK GENMASK_32(8, 0) 6204 /* CSR_SEQUENCEREG0B80S0 */ 6205 #define CSR_SEQUENCEREG0B80S0_LSB 0 6206 #define CSR_SEQUENCEREG0B80S0_MASK GENMASK_32(15, 0) 6207 /* CSR_SEQUENCEREG0B80S1 */ 6208 #define CSR_SEQUENCEREG0B80S1_LSB 0 6209 #define CSR_SEQUENCEREG0B80S1_MASK GENMASK_32(15, 0) 6210 /* CSR_SEQUENCEREG0B80S2 */ 6211 #define CSR_SEQUENCEREG0B80S2_LSB 0 6212 #define CSR_SEQUENCEREG0B80S2_MASK GENMASK_32(8, 0) 6213 /* CSR_SEQUENCEREG0B81S0 */ 6214 #define CSR_SEQUENCEREG0B81S0_LSB 0 6215 #define CSR_SEQUENCEREG0B81S0_MASK GENMASK_32(15, 0) 6216 /* CSR_SEQUENCEREG0B81S1 */ 6217 #define CSR_SEQUENCEREG0B81S1_LSB 0 6218 #define CSR_SEQUENCEREG0B81S1_MASK GENMASK_32(15, 0) 6219 /* CSR_SEQUENCEREG0B81S2 */ 6220 #define CSR_SEQUENCEREG0B81S2_LSB 0 6221 #define CSR_SEQUENCEREG0B81S2_MASK GENMASK_32(8, 0) 6222 /* CSR_SEQUENCEREG0B82S0 */ 6223 #define CSR_SEQUENCEREG0B82S0_LSB 0 6224 #define CSR_SEQUENCEREG0B82S0_MASK GENMASK_32(15, 0) 6225 /* CSR_SEQUENCEREG0B82S1 */ 6226 #define CSR_SEQUENCEREG0B82S1_LSB 0 6227 #define CSR_SEQUENCEREG0B82S1_MASK GENMASK_32(15, 0) 6228 /* CSR_SEQUENCEREG0B82S2 */ 6229 #define CSR_SEQUENCEREG0B82S2_LSB 0 6230 #define CSR_SEQUENCEREG0B82S2_MASK GENMASK_32(8, 0) 6231 /* CSR_SEQUENCEREG0B83S0 */ 6232 #define CSR_SEQUENCEREG0B83S0_LSB 0 6233 #define CSR_SEQUENCEREG0B83S0_MASK GENMASK_32(15, 0) 6234 /* CSR_SEQUENCEREG0B83S1 */ 6235 #define CSR_SEQUENCEREG0B83S1_LSB 0 6236 #define CSR_SEQUENCEREG0B83S1_MASK GENMASK_32(15, 0) 6237 /* CSR_SEQUENCEREG0B83S2 */ 6238 #define CSR_SEQUENCEREG0B83S2_LSB 0 6239 #define CSR_SEQUENCEREG0B83S2_MASK GENMASK_32(8, 0) 6240 /* CSR_SEQUENCEREG0B84S0 */ 6241 #define CSR_SEQUENCEREG0B84S0_LSB 0 6242 #define CSR_SEQUENCEREG0B84S0_MASK GENMASK_32(15, 0) 6243 /* CSR_SEQUENCEREG0B84S1 */ 6244 #define CSR_SEQUENCEREG0B84S1_LSB 0 6245 #define CSR_SEQUENCEREG0B84S1_MASK GENMASK_32(15, 0) 6246 /* CSR_SEQUENCEREG0B84S2 */ 6247 #define CSR_SEQUENCEREG0B84S2_LSB 0 6248 #define CSR_SEQUENCEREG0B84S2_MASK GENMASK_32(8, 0) 6249 /* CSR_SEQUENCEREG0B85S0 */ 6250 #define CSR_SEQUENCEREG0B85S0_LSB 0 6251 #define CSR_SEQUENCEREG0B85S0_MASK GENMASK_32(15, 0) 6252 /* CSR_SEQUENCEREG0B85S1 */ 6253 #define CSR_SEQUENCEREG0B85S1_LSB 0 6254 #define CSR_SEQUENCEREG0B85S1_MASK GENMASK_32(15, 0) 6255 /* CSR_SEQUENCEREG0B85S2 */ 6256 #define CSR_SEQUENCEREG0B85S2_LSB 0 6257 #define CSR_SEQUENCEREG0B85S2_MASK GENMASK_32(8, 0) 6258 /* CSR_SEQUENCEREG0B86S0 */ 6259 #define CSR_SEQUENCEREG0B86S0_LSB 0 6260 #define CSR_SEQUENCEREG0B86S0_MASK GENMASK_32(15, 0) 6261 /* CSR_SEQUENCEREG0B86S1 */ 6262 #define CSR_SEQUENCEREG0B86S1_LSB 0 6263 #define CSR_SEQUENCEREG0B86S1_MASK GENMASK_32(15, 0) 6264 /* CSR_SEQUENCEREG0B86S2 */ 6265 #define CSR_SEQUENCEREG0B86S2_LSB 0 6266 #define CSR_SEQUENCEREG0B86S2_MASK GENMASK_32(8, 0) 6267 /* CSR_SEQUENCEREG0B87S0 */ 6268 #define CSR_SEQUENCEREG0B87S0_LSB 0 6269 #define CSR_SEQUENCEREG0B87S0_MASK GENMASK_32(15, 0) 6270 /* CSR_SEQUENCEREG0B87S1 */ 6271 #define CSR_SEQUENCEREG0B87S1_LSB 0 6272 #define CSR_SEQUENCEREG0B87S1_MASK GENMASK_32(15, 0) 6273 /* CSR_SEQUENCEREG0B87S2 */ 6274 #define CSR_SEQUENCEREG0B87S2_LSB 0 6275 #define CSR_SEQUENCEREG0B87S2_MASK GENMASK_32(8, 0) 6276 /* CSR_SEQUENCEREG0B88S0 */ 6277 #define CSR_SEQUENCEREG0B88S0_LSB 0 6278 #define CSR_SEQUENCEREG0B88S0_MASK GENMASK_32(15, 0) 6279 /* CSR_SEQUENCEREG0B88S1 */ 6280 #define CSR_SEQUENCEREG0B88S1_LSB 0 6281 #define CSR_SEQUENCEREG0B88S1_MASK GENMASK_32(15, 0) 6282 /* CSR_SEQUENCEREG0B88S2 */ 6283 #define CSR_SEQUENCEREG0B88S2_LSB 0 6284 #define CSR_SEQUENCEREG0B88S2_MASK GENMASK_32(8, 0) 6285 /* CSR_SEQUENCEREG0B89S0 */ 6286 #define CSR_SEQUENCEREG0B89S0_LSB 0 6287 #define CSR_SEQUENCEREG0B89S0_MASK GENMASK_32(15, 0) 6288 /* CSR_SEQUENCEREG0B89S1 */ 6289 #define CSR_SEQUENCEREG0B89S1_LSB 0 6290 #define CSR_SEQUENCEREG0B89S1_MASK GENMASK_32(15, 0) 6291 /* CSR_SEQUENCEREG0B89S2 */ 6292 #define CSR_SEQUENCEREG0B89S2_LSB 0 6293 #define CSR_SEQUENCEREG0B89S2_MASK GENMASK_32(8, 0) 6294 /* CSR_SEQUENCEREG0B90S0 */ 6295 #define CSR_SEQUENCEREG0B90S0_LSB 0 6296 #define CSR_SEQUENCEREG0B90S0_MASK GENMASK_32(15, 0) 6297 /* CSR_SEQUENCEREG0B90S1 */ 6298 #define CSR_SEQUENCEREG0B90S1_LSB 0 6299 #define CSR_SEQUENCEREG0B90S1_MASK GENMASK_32(15, 0) 6300 /* CSR_SEQUENCEREG0B90S2 */ 6301 #define CSR_SEQUENCEREG0B90S2_LSB 0 6302 #define CSR_SEQUENCEREG0B90S2_MASK GENMASK_32(8, 0) 6303 /* CSR_SEQUENCEREG0B91S0 */ 6304 #define CSR_SEQUENCEREG0B91S0_LSB 0 6305 #define CSR_SEQUENCEREG0B91S0_MASK GENMASK_32(15, 0) 6306 /* CSR_SEQUENCEREG0B91S1 */ 6307 #define CSR_SEQUENCEREG0B91S1_LSB 0 6308 #define CSR_SEQUENCEREG0B91S1_MASK GENMASK_32(15, 0) 6309 /* CSR_SEQUENCEREG0B91S2 */ 6310 #define CSR_SEQUENCEREG0B91S2_LSB 0 6311 #define CSR_SEQUENCEREG0B91S2_MASK GENMASK_32(8, 0) 6312 /* CSR_SEQUENCEREG0B92S0 */ 6313 #define CSR_SEQUENCEREG0B92S0_LSB 0 6314 #define CSR_SEQUENCEREG0B92S0_MASK GENMASK_32(15, 0) 6315 /* CSR_SEQUENCEREG0B92S1 */ 6316 #define CSR_SEQUENCEREG0B92S1_LSB 0 6317 #define CSR_SEQUENCEREG0B92S1_MASK GENMASK_32(15, 0) 6318 /* CSR_SEQUENCEREG0B92S2 */ 6319 #define CSR_SEQUENCEREG0B92S2_LSB 0 6320 #define CSR_SEQUENCEREG0B92S2_MASK GENMASK_32(8, 0) 6321 /* CSR_SEQUENCEREG0B93S0 */ 6322 #define CSR_SEQUENCEREG0B93S0_LSB 0 6323 #define CSR_SEQUENCEREG0B93S0_MASK GENMASK_32(15, 0) 6324 /* CSR_SEQUENCEREG0B93S1 */ 6325 #define CSR_SEQUENCEREG0B93S1_LSB 0 6326 #define CSR_SEQUENCEREG0B93S1_MASK GENMASK_32(15, 0) 6327 /* CSR_SEQUENCEREG0B93S2 */ 6328 #define CSR_SEQUENCEREG0B93S2_LSB 0 6329 #define CSR_SEQUENCEREG0B93S2_MASK GENMASK_32(8, 0) 6330 /* CSR_SEQUENCEREG0B94S0 */ 6331 #define CSR_SEQUENCEREG0B94S0_LSB 0 6332 #define CSR_SEQUENCEREG0B94S0_MASK GENMASK_32(15, 0) 6333 /* CSR_SEQUENCEREG0B94S1 */ 6334 #define CSR_SEQUENCEREG0B94S1_LSB 0 6335 #define CSR_SEQUENCEREG0B94S1_MASK GENMASK_32(15, 0) 6336 /* CSR_SEQUENCEREG0B94S2 */ 6337 #define CSR_SEQUENCEREG0B94S2_LSB 0 6338 #define CSR_SEQUENCEREG0B94S2_MASK GENMASK_32(8, 0) 6339 /* CSR_SEQUENCEREG0B95S0 */ 6340 #define CSR_SEQUENCEREG0B95S0_LSB 0 6341 #define CSR_SEQUENCEREG0B95S0_MASK GENMASK_32(15, 0) 6342 /* CSR_SEQUENCEREG0B95S1 */ 6343 #define CSR_SEQUENCEREG0B95S1_LSB 0 6344 #define CSR_SEQUENCEREG0B95S1_MASK GENMASK_32(15, 0) 6345 /* CSR_SEQUENCEREG0B95S2 */ 6346 #define CSR_SEQUENCEREG0B95S2_LSB 0 6347 #define CSR_SEQUENCEREG0B95S2_MASK GENMASK_32(8, 0) 6348 /* CSR_SEQUENCEREG0B96S0 */ 6349 #define CSR_SEQUENCEREG0B96S0_LSB 0 6350 #define CSR_SEQUENCEREG0B96S0_MASK GENMASK_32(15, 0) 6351 /* CSR_SEQUENCEREG0B96S1 */ 6352 #define CSR_SEQUENCEREG0B96S1_LSB 0 6353 #define CSR_SEQUENCEREG0B96S1_MASK GENMASK_32(15, 0) 6354 /* CSR_SEQUENCEREG0B96S2 */ 6355 #define CSR_SEQUENCEREG0B96S2_LSB 0 6356 #define CSR_SEQUENCEREG0B96S2_MASK GENMASK_32(8, 0) 6357 /* CSR_SEQUENCEREG0B97S0 */ 6358 #define CSR_SEQUENCEREG0B97S0_LSB 0 6359 #define CSR_SEQUENCEREG0B97S0_MASK GENMASK_32(15, 0) 6360 /* CSR_SEQUENCEREG0B97S1 */ 6361 #define CSR_SEQUENCEREG0B97S1_LSB 0 6362 #define CSR_SEQUENCEREG0B97S1_MASK GENMASK_32(15, 0) 6363 /* CSR_SEQUENCEREG0B97S2 */ 6364 #define CSR_SEQUENCEREG0B97S2_LSB 0 6365 #define CSR_SEQUENCEREG0B97S2_MASK GENMASK_32(8, 0) 6366 /* CSR_SEQUENCEREG0B98S0 */ 6367 #define CSR_SEQUENCEREG0B98S0_LSB 0 6368 #define CSR_SEQUENCEREG0B98S0_MASK GENMASK_32(15, 0) 6369 /* CSR_SEQUENCEREG0B98S1 */ 6370 #define CSR_SEQUENCEREG0B98S1_LSB 0 6371 #define CSR_SEQUENCEREG0B98S1_MASK GENMASK_32(15, 0) 6372 /* CSR_SEQUENCEREG0B98S2 */ 6373 #define CSR_SEQUENCEREG0B98S2_LSB 0 6374 #define CSR_SEQUENCEREG0B98S2_MASK GENMASK_32(8, 0) 6375 /* CSR_SEQUENCEREG0B99S0 */ 6376 #define CSR_SEQUENCEREG0B99S0_LSB 0 6377 #define CSR_SEQUENCEREG0B99S0_MASK GENMASK_32(15, 0) 6378 /* CSR_SEQUENCEREG0B99S1 */ 6379 #define CSR_SEQUENCEREG0B99S1_LSB 0 6380 #define CSR_SEQUENCEREG0B99S1_MASK GENMASK_32(15, 0) 6381 /* CSR_SEQUENCEREG0B99S2 */ 6382 #define CSR_SEQUENCEREG0B99S2_LSB 0 6383 #define CSR_SEQUENCEREG0B99S2_MASK GENMASK_32(8, 0) 6384 /* CSR_SEQUENCEREG0B100S0 */ 6385 #define CSR_SEQUENCEREG0B100S0_LSB 0 6386 #define CSR_SEQUENCEREG0B100S0_MASK GENMASK_32(15, 0) 6387 /* CSR_SEQUENCEREG0B100S1 */ 6388 #define CSR_SEQUENCEREG0B100S1_LSB 0 6389 #define CSR_SEQUENCEREG0B100S1_MASK GENMASK_32(15, 0) 6390 /* CSR_SEQUENCEREG0B100S2 */ 6391 #define CSR_SEQUENCEREG0B100S2_LSB 0 6392 #define CSR_SEQUENCEREG0B100S2_MASK GENMASK_32(8, 0) 6393 /* CSR_SEQUENCEREG0B101S0 */ 6394 #define CSR_SEQUENCEREG0B101S0_LSB 0 6395 #define CSR_SEQUENCEREG0B101S0_MASK GENMASK_32(15, 0) 6396 /* CSR_SEQUENCEREG0B101S1 */ 6397 #define CSR_SEQUENCEREG0B101S1_LSB 0 6398 #define CSR_SEQUENCEREG0B101S1_MASK GENMASK_32(15, 0) 6399 /* CSR_SEQUENCEREG0B101S2 */ 6400 #define CSR_SEQUENCEREG0B101S2_LSB 0 6401 #define CSR_SEQUENCEREG0B101S2_MASK GENMASK_32(8, 0) 6402 /* CSR_SEQUENCEREG0B102S0 */ 6403 #define CSR_SEQUENCEREG0B102S0_LSB 0 6404 #define CSR_SEQUENCEREG0B102S0_MASK GENMASK_32(15, 0) 6405 /* CSR_SEQUENCEREG0B102S1 */ 6406 #define CSR_SEQUENCEREG0B102S1_LSB 0 6407 #define CSR_SEQUENCEREG0B102S1_MASK GENMASK_32(15, 0) 6408 /* CSR_SEQUENCEREG0B102S2 */ 6409 #define CSR_SEQUENCEREG0B102S2_LSB 0 6410 #define CSR_SEQUENCEREG0B102S2_MASK GENMASK_32(8, 0) 6411 /* CSR_SEQUENCEREG0B103S0 */ 6412 #define CSR_SEQUENCEREG0B103S0_LSB 0 6413 #define CSR_SEQUENCEREG0B103S0_MASK GENMASK_32(15, 0) 6414 /* CSR_SEQUENCEREG0B103S1 */ 6415 #define CSR_SEQUENCEREG0B103S1_LSB 0 6416 #define CSR_SEQUENCEREG0B103S1_MASK GENMASK_32(15, 0) 6417 /* CSR_SEQUENCEREG0B103S2 */ 6418 #define CSR_SEQUENCEREG0B103S2_LSB 0 6419 #define CSR_SEQUENCEREG0B103S2_MASK GENMASK_32(8, 0) 6420 /* CSR_SEQUENCEREG0B104S0 */ 6421 #define CSR_SEQUENCEREG0B104S0_LSB 0 6422 #define CSR_SEQUENCEREG0B104S0_MASK GENMASK_32(15, 0) 6423 /* CSR_SEQUENCEREG0B104S1 */ 6424 #define CSR_SEQUENCEREG0B104S1_LSB 0 6425 #define CSR_SEQUENCEREG0B104S1_MASK GENMASK_32(15, 0) 6426 /* CSR_SEQUENCEREG0B104S2 */ 6427 #define CSR_SEQUENCEREG0B104S2_LSB 0 6428 #define CSR_SEQUENCEREG0B104S2_MASK GENMASK_32(8, 0) 6429 /* CSR_SEQUENCEREG0B105S0 */ 6430 #define CSR_SEQUENCEREG0B105S0_LSB 0 6431 #define CSR_SEQUENCEREG0B105S0_MASK GENMASK_32(15, 0) 6432 /* CSR_SEQUENCEREG0B105S1 */ 6433 #define CSR_SEQUENCEREG0B105S1_LSB 0 6434 #define CSR_SEQUENCEREG0B105S1_MASK GENMASK_32(15, 0) 6435 /* CSR_SEQUENCEREG0B105S2 */ 6436 #define CSR_SEQUENCEREG0B105S2_LSB 0 6437 #define CSR_SEQUENCEREG0B105S2_MASK GENMASK_32(8, 0) 6438 /* CSR_SEQUENCEREG0B106S0 */ 6439 #define CSR_SEQUENCEREG0B106S0_LSB 0 6440 #define CSR_SEQUENCEREG0B106S0_MASK GENMASK_32(15, 0) 6441 /* CSR_SEQUENCEREG0B106S1 */ 6442 #define CSR_SEQUENCEREG0B106S1_LSB 0 6443 #define CSR_SEQUENCEREG0B106S1_MASK GENMASK_32(15, 0) 6444 /* CSR_SEQUENCEREG0B106S2 */ 6445 #define CSR_SEQUENCEREG0B106S2_LSB 0 6446 #define CSR_SEQUENCEREG0B106S2_MASK GENMASK_32(8, 0) 6447 /* CSR_SEQUENCEREG0B107S0 */ 6448 #define CSR_SEQUENCEREG0B107S0_LSB 0 6449 #define CSR_SEQUENCEREG0B107S0_MASK GENMASK_32(15, 0) 6450 /* CSR_SEQUENCEREG0B107S1 */ 6451 #define CSR_SEQUENCEREG0B107S1_LSB 0 6452 #define CSR_SEQUENCEREG0B107S1_MASK GENMASK_32(15, 0) 6453 /* CSR_SEQUENCEREG0B107S2 */ 6454 #define CSR_SEQUENCEREG0B107S2_LSB 0 6455 #define CSR_SEQUENCEREG0B107S2_MASK GENMASK_32(8, 0) 6456 /* CSR_SEQUENCEREG0B108S0 */ 6457 #define CSR_SEQUENCEREG0B108S0_LSB 0 6458 #define CSR_SEQUENCEREG0B108S0_MASK GENMASK_32(15, 0) 6459 /* CSR_SEQUENCEREG0B108S1 */ 6460 #define CSR_SEQUENCEREG0B108S1_LSB 0 6461 #define CSR_SEQUENCEREG0B108S1_MASK GENMASK_32(15, 0) 6462 /* CSR_SEQUENCEREG0B108S2 */ 6463 #define CSR_SEQUENCEREG0B108S2_LSB 0 6464 #define CSR_SEQUENCEREG0B108S2_MASK GENMASK_32(8, 0) 6465 /* CSR_SEQUENCEREG0B109S0 */ 6466 #define CSR_SEQUENCEREG0B109S0_LSB 0 6467 #define CSR_SEQUENCEREG0B109S0_MASK GENMASK_32(15, 0) 6468 /* CSR_SEQUENCEREG0B109S1 */ 6469 #define CSR_SEQUENCEREG0B109S1_LSB 0 6470 #define CSR_SEQUENCEREG0B109S1_MASK GENMASK_32(15, 0) 6471 /* CSR_SEQUENCEREG0B109S2 */ 6472 #define CSR_SEQUENCEREG0B109S2_LSB 0 6473 #define CSR_SEQUENCEREG0B109S2_MASK GENMASK_32(8, 0) 6474 /* CSR_SEQUENCEREG0B110S0 */ 6475 #define CSR_SEQUENCEREG0B110S0_LSB 0 6476 #define CSR_SEQUENCEREG0B110S0_MASK GENMASK_32(15, 0) 6477 /* CSR_SEQUENCEREG0B110S1 */ 6478 #define CSR_SEQUENCEREG0B110S1_LSB 0 6479 #define CSR_SEQUENCEREG0B110S1_MASK GENMASK_32(15, 0) 6480 /* CSR_SEQUENCEREG0B110S2 */ 6481 #define CSR_SEQUENCEREG0B110S2_LSB 0 6482 #define CSR_SEQUENCEREG0B110S2_MASK GENMASK_32(8, 0) 6483 /* CSR_SEQUENCEREG0B111S0 */ 6484 #define CSR_SEQUENCEREG0B111S0_LSB 0 6485 #define CSR_SEQUENCEREG0B111S0_MASK GENMASK_32(15, 0) 6486 /* CSR_SEQUENCEREG0B111S1 */ 6487 #define CSR_SEQUENCEREG0B111S1_LSB 0 6488 #define CSR_SEQUENCEREG0B111S1_MASK GENMASK_32(15, 0) 6489 /* CSR_SEQUENCEREG0B111S2 */ 6490 #define CSR_SEQUENCEREG0B111S2_LSB 0 6491 #define CSR_SEQUENCEREG0B111S2_MASK GENMASK_32(8, 0) 6492 /* CSR_SEQUENCEREG0B112S0 */ 6493 #define CSR_SEQUENCEREG0B112S0_LSB 0 6494 #define CSR_SEQUENCEREG0B112S0_MASK GENMASK_32(15, 0) 6495 /* CSR_SEQUENCEREG0B112S1 */ 6496 #define CSR_SEQUENCEREG0B112S1_LSB 0 6497 #define CSR_SEQUENCEREG0B112S1_MASK GENMASK_32(15, 0) 6498 /* CSR_SEQUENCEREG0B112S2 */ 6499 #define CSR_SEQUENCEREG0B112S2_LSB 0 6500 #define CSR_SEQUENCEREG0B112S2_MASK GENMASK_32(8, 0) 6501 /* CSR_SEQUENCEREG0B113S0 */ 6502 #define CSR_SEQUENCEREG0B113S0_LSB 0 6503 #define CSR_SEQUENCEREG0B113S0_MASK GENMASK_32(15, 0) 6504 /* CSR_SEQUENCEREG0B113S1 */ 6505 #define CSR_SEQUENCEREG0B113S1_LSB 0 6506 #define CSR_SEQUENCEREG0B113S1_MASK GENMASK_32(15, 0) 6507 /* CSR_SEQUENCEREG0B113S2 */ 6508 #define CSR_SEQUENCEREG0B113S2_LSB 0 6509 #define CSR_SEQUENCEREG0B113S2_MASK GENMASK_32(8, 0) 6510 /* CSR_SEQUENCEREG0B114S0 */ 6511 #define CSR_SEQUENCEREG0B114S0_LSB 0 6512 #define CSR_SEQUENCEREG0B114S0_MASK GENMASK_32(15, 0) 6513 /* CSR_SEQUENCEREG0B114S1 */ 6514 #define CSR_SEQUENCEREG0B114S1_LSB 0 6515 #define CSR_SEQUENCEREG0B114S1_MASK GENMASK_32(15, 0) 6516 /* CSR_SEQUENCEREG0B114S2 */ 6517 #define CSR_SEQUENCEREG0B114S2_LSB 0 6518 #define CSR_SEQUENCEREG0B114S2_MASK GENMASK_32(8, 0) 6519 /* CSR_SEQUENCEREG0B115S0 */ 6520 #define CSR_SEQUENCEREG0B115S0_LSB 0 6521 #define CSR_SEQUENCEREG0B115S0_MASK GENMASK_32(15, 0) 6522 /* CSR_SEQUENCEREG0B115S1 */ 6523 #define CSR_SEQUENCEREG0B115S1_LSB 0 6524 #define CSR_SEQUENCEREG0B115S1_MASK GENMASK_32(15, 0) 6525 /* CSR_SEQUENCEREG0B115S2 */ 6526 #define CSR_SEQUENCEREG0B115S2_LSB 0 6527 #define CSR_SEQUENCEREG0B115S2_MASK GENMASK_32(8, 0) 6528 /* CSR_SEQUENCEREG0B116S0 */ 6529 #define CSR_SEQUENCEREG0B116S0_LSB 0 6530 #define CSR_SEQUENCEREG0B116S0_MASK GENMASK_32(15, 0) 6531 /* CSR_SEQUENCEREG0B116S1 */ 6532 #define CSR_SEQUENCEREG0B116S1_LSB 0 6533 #define CSR_SEQUENCEREG0B116S1_MASK GENMASK_32(15, 0) 6534 /* CSR_SEQUENCEREG0B116S2 */ 6535 #define CSR_SEQUENCEREG0B116S2_LSB 0 6536 #define CSR_SEQUENCEREG0B116S2_MASK GENMASK_32(8, 0) 6537 /* CSR_SEQUENCEREG0B117S0 */ 6538 #define CSR_SEQUENCEREG0B117S0_LSB 0 6539 #define CSR_SEQUENCEREG0B117S0_MASK GENMASK_32(15, 0) 6540 /* CSR_SEQUENCEREG0B117S1 */ 6541 #define CSR_SEQUENCEREG0B117S1_LSB 0 6542 #define CSR_SEQUENCEREG0B117S1_MASK GENMASK_32(15, 0) 6543 /* CSR_SEQUENCEREG0B117S2 */ 6544 #define CSR_SEQUENCEREG0B117S2_LSB 0 6545 #define CSR_SEQUENCEREG0B117S2_MASK GENMASK_32(8, 0) 6546 /* CSR_SEQUENCEREG0B118S0 */ 6547 #define CSR_SEQUENCEREG0B118S0_LSB 0 6548 #define CSR_SEQUENCEREG0B118S0_MASK GENMASK_32(15, 0) 6549 /* CSR_SEQUENCEREG0B118S1 */ 6550 #define CSR_SEQUENCEREG0B118S1_LSB 0 6551 #define CSR_SEQUENCEREG0B118S1_MASK GENMASK_32(15, 0) 6552 /* CSR_SEQUENCEREG0B118S2 */ 6553 #define CSR_SEQUENCEREG0B118S2_LSB 0 6554 #define CSR_SEQUENCEREG0B118S2_MASK GENMASK_32(8, 0) 6555 /* CSR_SEQUENCEREG0B119S0 */ 6556 #define CSR_SEQUENCEREG0B119S0_LSB 0 6557 #define CSR_SEQUENCEREG0B119S0_MASK GENMASK_32(15, 0) 6558 /* CSR_SEQUENCEREG0B119S1 */ 6559 #define CSR_SEQUENCEREG0B119S1_LSB 0 6560 #define CSR_SEQUENCEREG0B119S1_MASK GENMASK_32(15, 0) 6561 /* CSR_SEQUENCEREG0B119S2 */ 6562 #define CSR_SEQUENCEREG0B119S2_LSB 0 6563 #define CSR_SEQUENCEREG0B119S2_MASK GENMASK_32(8, 0) 6564 /* CSR_SEQUENCEREG0B120S0 */ 6565 #define CSR_SEQUENCEREG0B120S0_LSB 0 6566 #define CSR_SEQUENCEREG0B120S0_MASK GENMASK_32(15, 0) 6567 /* CSR_SEQUENCEREG0B120S1 */ 6568 #define CSR_SEQUENCEREG0B120S1_LSB 0 6569 #define CSR_SEQUENCEREG0B120S1_MASK GENMASK_32(15, 0) 6570 /* CSR_SEQUENCEREG0B120S2 */ 6571 #define CSR_SEQUENCEREG0B120S2_LSB 0 6572 #define CSR_SEQUENCEREG0B120S2_MASK GENMASK_32(8, 0) 6573 /* CSR_SEQUENCEREG0B121S0 */ 6574 #define CSR_SEQUENCEREG0B121S0_LSB 0 6575 #define CSR_SEQUENCEREG0B121S0_MASK GENMASK_32(15, 0) 6576 /* CSR_SEQUENCEREG0B121S1 */ 6577 #define CSR_SEQUENCEREG0B121S1_LSB 0 6578 #define CSR_SEQUENCEREG0B121S1_MASK GENMASK_32(15, 0) 6579 /* CSR_SEQUENCEREG0B121S2 */ 6580 #define CSR_SEQUENCEREG0B121S2_LSB 0 6581 #define CSR_SEQUENCEREG0B121S2_MASK GENMASK_32(8, 0) 6582 /* CSR_SEQ0BGPR1 */ 6583 #define CSR_SEQ0BGPR1_LSB 0 6584 #define CSR_SEQ0BGPR1_MASK GENMASK_32(15, 0) 6585 /* CSR_SEQ0BGPR2 */ 6586 #define CSR_SEQ0BGPR2_LSB 0 6587 #define CSR_SEQ0BGPR2_MASK GENMASK_32(15, 0) 6588 /* CSR_SEQ0BGPR3 */ 6589 #define CSR_SEQ0BGPR3_LSB 0 6590 #define CSR_SEQ0BGPR3_MASK GENMASK_32(15, 0) 6591 /* CSR_SEQ0BGPR4 */ 6592 #define CSR_SEQ0BGPR4_LSB 0 6593 #define CSR_SEQ0BGPR4_MASK GENMASK_32(15, 0) 6594 /* CSR_SEQ0BGPR5 */ 6595 #define CSR_SEQ0BGPR5_LSB 0 6596 #define CSR_SEQ0BGPR5_MASK GENMASK_32(15, 0) 6597 /* CSR_SEQ0BGPR6 */ 6598 #define CSR_SEQ0BGPR6_LSB 0 6599 #define CSR_SEQ0BGPR6_MASK GENMASK_32(15, 0) 6600 /* CSR_SEQ0BGPR7 */ 6601 #define CSR_SEQ0BGPR7_LSB 0 6602 #define CSR_SEQ0BGPR7_MASK GENMASK_32(15, 0) 6603 /* CSR_SEQ0BGPR8 */ 6604 #define CSR_SEQ0BGPR8_LSB 0 6605 #define CSR_SEQ0BGPR8_MASK GENMASK_32(15, 0) 6606 /* CSR_SEQ0BFIXEDADDRBITS */ 6607 #define CSR_SEQ0BFIXEDADDRBITS_LSB 0 6608 #define CSR_SEQ0BFIXEDADDRBITS_MASK GENMASK_32(6, 0) 6609 #define CSR_SEQ0BCHIPLETBITS_LSB 0 6610 #define CSR_SEQ0BCHIPLETBITS_MASK GENMASK_32(3, 0) 6611 #define CSR_SEQ0BPSTATEBITS_LSB 4 6612 #define CSR_SEQ0BPSTATEBITS_MASK GENMASK_32(6, 4) 6613 6614 /* DRTUB0 register offsets */ 6615 /* CSR_DCTSHADOWREGS */ 6616 #define CSR_DCTSHADOWREGS_LSB 0 6617 #define CSR_DCTSHADOWREGS_MASK BIT(0) 6618 #define CSR_DCTWRITEPROTSHADOW_LSB 0 6619 #define CSR_DCTWRITEPROTSHADOW_MASK BIT(0) 6620 /* CSR_DCTWRITEONLYSHADOW */ 6621 #define CSR_DCTWRITEONLYSHADOW_LSB 0 6622 #define CSR_DCTWRITEONLYSHADOW_MASK GENMASK_32(15, 0) 6623 /* CSR_UCTWRITEONLY */ 6624 #define CSR_UCTWRITEONLY_LSB 0 6625 #define CSR_UCTWRITEONLY_MASK GENMASK_32(15, 0) 6626 /* CSR_UCTWRITEPROT */ 6627 #define CSR_UCTWRITEPROT_LSB 0 6628 #define CSR_UCTWRITEPROT_MASK BIT(0) 6629 /* CSR_UCTDATWRITEONLY */ 6630 #define CSR_UCTDATWRITEONLY_LSB 0 6631 #define CSR_UCTDATWRITEONLY_MASK GENMASK_32(15, 0) 6632 /* CSR_UCTDATWRITEPROT */ 6633 #define CSR_UCTDATWRITEPROT_LSB 0 6634 #define CSR_UCTDATWRITEPROT_MASK BIT(0) 6635 /* CSR_UCTLERR */ 6636 #define CSR_UCTLERR_LSB 0 6637 #define CSR_UCTLERR_MASK BIT(0) 6638 /* CSR_UCCLKHCLKENABLES */ 6639 #define CSR_UCCLKHCLKENABLES_LSB 0 6640 #define CSR_UCCLKHCLKENABLES_MASK GENMASK_32(1, 0) 6641 #define CSR_UCCLKEN_LSB 0 6642 #define CSR_UCCLKEN_MASK BIT(0) 6643 #define CSR_HCLKEN_LSB 1 6644 #define CSR_HCLKEN_MASK BIT(1) 6645 /* CSR_CURPSTATE0B */ 6646 #define CSR_CURPSTATE0B_LSB 0 6647 #define CSR_CURPSTATE0B_MASK GENMASK_32(3, 0) 6648 /* CSR_CLRWAKEUPSTICKY */ 6649 #define CSR_CLRWAKEUPSTICKY_LSB 0 6650 #define CSR_CLRWAKEUPSTICKY_MASK GENMASK_32(3, 0) 6651 /* CSR_WAKEUPMASK */ 6652 #define CSR_WAKEUPMASK_LSB 0 6653 #define CSR_WAKEUPMASK_MASK GENMASK_32(3, 0) 6654 /* CSR_CUSTPUBREV */ 6655 #define CSR_CUSTPUBREV_LSB 0 6656 #define CSR_CUSTPUBREV_MASK GENMASK_32(5, 0) 6657 /* CSR_PUBREV */ 6658 #define CSR_PUBREV_LSB 0 6659 #define CSR_PUBREV_MASK GENMASK_32(15, 0) 6660 #define CSR_RESERVEDPUBREV_LSB 0 6661 #define CSR_RESERVEDPUBREV_MASK GENMASK_32(3, 0) 6662 #define CSR_PUBMNR_LSB 4 6663 #define CSR_PUBMNR_MASK GENMASK_32(7, 4) 6664 #define CSR_PUBMDR_LSB 8 6665 #define CSR_PUBMDR_MASK GENMASK_32(11, 8) 6666 #define CSR_PUBMJR_LSB 12 6667 #define CSR_PUBMJR_MASK GENMASK_32(15, 12) 6668 6669 /* APBONLY0 register offsets */ 6670 /* CSR_MICROCONTMUXSEL */ 6671 #define CSR_MICROCONTMUXSEL_LSB 0 6672 #define CSR_MICROCONTMUXSEL_MASK BIT(0) 6673 /* CSR_UCTSHADOWREGS */ 6674 #define CSR_UCTSHADOWREGS_LSB 0 6675 #define CSR_UCTSHADOWREGS_MASK GENMASK_32(1, 0) 6676 #define CSR_UCTWRITEPROTSHADOW_LSB 0 6677 #define CSR_UCTWRITEPROTSHADOW_MASK BIT(0) 6678 #define CSR_UCTDATWRITEPROTSHADOW_LSB 1 6679 #define CSR_UCTDATWRITEPROTSHADOW_MASK BIT(1) 6680 /* CSR_DCTWRITEONLY */ 6681 #define CSR_DCTWRITEONLY_LSB 0 6682 #define CSR_DCTWRITEONLY_MASK GENMASK_32(15, 0) 6683 /* CSR_DCTWRITEPROT */ 6684 #define CSR_DCTWRITEPROT_LSB 0 6685 #define CSR_DCTWRITEPROT_MASK BIT(0) 6686 /* CSR_UCTWRITEONLYSHADOW */ 6687 #define CSR_UCTWRITEONLYSHADOW_LSB 0 6688 #define CSR_UCTWRITEONLYSHADOW_MASK GENMASK_32(15, 0) 6689 /* CSR_UCTDATWRITEONLYSHADOW */ 6690 #define CSR_UCTDATWRITEONLYSHADOW_LSB 0 6691 #define CSR_UCTDATWRITEONLYSHADOW_MASK GENMASK_32(15, 0) 6692 /* CSR_NEVERGATECSRCLOCK */ 6693 #define CSR_NEVERGATECSRCLOCK_LSB 0 6694 #define CSR_NEVERGATECSRCLOCK_MASK BIT(0) 6695 /* CSR_DFICFGRDDATAVALIDTICKS */ 6696 #define CSR_DFICFGRDDATAVALIDTICKS_LSB 0 6697 #define CSR_DFICFGRDDATAVALIDTICKS_MASK GENMASK_32(5, 0) 6698 /* CSR_MICRORESET */ 6699 #define CSR_MICRORESET_LSB 0 6700 #define CSR_MICRORESET_MASK GENMASK_32(3, 0) 6701 #define CSR_STALLTOMICRO_LSB 0 6702 #define CSR_STALLTOMICRO_MASK BIT(0) 6703 #define CSR_TESTWAKEUP_LSB 1 6704 #define CSR_TESTWAKEUP_MASK BIT(1) 6705 #define CSR_RSVDMICRO_LSB 2 6706 #define CSR_RSVDMICRO_MASK BIT(2) 6707 #define CSR_RESETTOMICRO_LSB 3 6708 #define CSR_RESETTOMICRO_MASK BIT(3) 6709 /* CSR_SEQUENCEROVERRIDE */ 6710 #define CSR_SEQUENCEROVERRIDE_LSB 0 6711 #define CSR_SEQUENCEROVERRIDE_MASK GENMASK_32(10, 0) 6712 #define CSR_FORCESEQ0BDFIFREQ_LSB 0 6713 #define CSR_FORCESEQ0BDFIFREQ_MASK GENMASK_32(4, 0) 6714 #define CSR_FORCESEQ0BSTART_LSB 5 6715 #define CSR_FORCESEQ0BSTART_MASK BIT(5) 6716 #define CSR_FORCESEQ0BSTOP_LSB 6 6717 #define CSR_FORCESEQ0BSTOP_MASK BIT(6) 6718 #define CSR_BLOCKSEQ0BREQUESTS_LSB 7 6719 #define CSR_BLOCKSEQ0BREQUESTS_MASK BIT(7) 6720 #define CSR_BLOCKSEQ0BACK_LSB 8 6721 #define CSR_BLOCKSEQ0BACK_MASK BIT(8) 6722 #define CSR_DISABLETERMINATEFLAG_LSB 9 6723 #define CSR_DISABLETERMINATEFLAG_MASK BIT(9) 6724 #define CSR_SELECTDFIFREQTOGPRMUX_LSB 10 6725 #define CSR_SELECTDFIFREQTOGPRMUX_MASK BIT(10) 6726 /* CSR_DFIINITCOMPLETESHADOW */ 6727 #define CSR_DFIINITCOMPLETESHADOW_LSB 0 6728 #define CSR_DFIINITCOMPLETESHADOW_MASK BIT(0) 6729 6730 /* Fields brought to you by the letter B */ 6731 #define B_MIN 0U 6732 #define B_MAX 1U 6733 #define B0 0x0U 6734 #define B1 0x100U 6735 #define BBRD 0xF00U 6736 #define BB_MIN 0U 6737 #define BB_MAX 15U 6738 #define BB0 0x0U 6739 #define BB1 0x1000U 6740 #define BB2 0x2000U 6741 #define BB3 0x3000U 6742 #define BB4 0x4000U 6743 #define BB5 0x5000U 6744 #define BB6 0x6000U 6745 #define BB7 0x7000U 6746 #define BB8 0x8000U 6747 #define BB9 0x9000U 6748 #define BB10 0xA000U 6749 #define BB11 0xB000U 6750 #define BB12 0xC000U 6751 #define BB13 0xD000U 6752 #define BB14 0xE000U 6753 #define BB15 0xF000U 6754 #define BBBRD 0xF000U 6755 /* Fields brought to you by the letter C */ 6756 #define C_MIN 0U 6757 #define C_MAX 15U 6758 #define C0 0x0U 6759 #define C1 0x1000U 6760 #define C2 0x2000U 6761 #define C3 0x3000U 6762 #define C4 0x4000U 6763 #define C5 0x5000U 6764 #define C6 0x6000U 6765 #define C7 0x7000U 6766 #define C8 0x8000U 6767 #define C9 0x9000U 6768 #define C10 0xA000U 6769 #define C11 0xB000U 6770 #define C12 0xC000U 6771 #define C13 0xD000U 6772 #define C14 0xE000U 6773 #define C15 0xF000U 6774 #define CBRD 0xF000U 6775 /* Fields brought to you by the letter D */ 6776 #define D_MIN 0U 6777 #define D_MAX 3U 6778 #define D0 0x0U 6779 #define D1 0x100U 6780 #define D2 0x200U 6781 #define D3 0x300U 6782 #define DBRD 0xF00U 6783 /* Fields brought to you by the letter I */ 6784 #define I_MIN 0U 6785 #define I_MAX 8U 6786 #define I0 0x0U 6787 #define I1 0x100U 6788 #define I2 0x200U 6789 #define I3 0x300U 6790 #define I4 0x400U 6791 #define I5 0x500U 6792 #define I6 0x600U 6793 #define I7 0x700U 6794 #define I8 0x800U 6795 #define IBRD 0xF00U 6796 /* Fields brought to you by the letter J */ 6797 #define J_MIN 0U 6798 #define J_MAX 0U 6799 #define J0 0x0U 6800 #define JBRD 0xF00U 6801 /* Fields brought to you by the letter L */ 6802 #define L_MIN 0U 6803 #define L_MAX 13U 6804 #define L0 0x0U 6805 #define L1 0x100U 6806 #define L2 0x200U 6807 #define L3 0x300U 6808 #define L4 0x400U 6809 #define L5 0x500U 6810 #define L6 0x600U 6811 #define L7 0x700U 6812 #define L8 0x800U 6813 #define L9 0x900U 6814 #define L10 0xA00U 6815 #define L11 0xB00U 6816 #define L12 0xC00U 6817 #define L13 0xD00U 6818 #define LBRD 0xF00U 6819 /* Fields brought to you by the letter M */ 6820 #define M_MIN 0U 6821 #define M_MAX 8U 6822 #define M0 0x0U 6823 #define M1 0x100U 6824 #define M2 0x200U 6825 #define M3 0x300U 6826 #define M4 0x400U 6827 #define M5 0x500U 6828 #define M6 0x600U 6829 #define M7 0x700U 6830 #define M8 0x800U 6831 #define MBRD 0xF00U 6832 /* Fields brought to you by the letter N */ 6833 #define N_MIN 0U 6834 #define N_MAX 15U 6835 #define N0 0x0U 6836 #define N1 0x100U 6837 #define N2 0x200U 6838 #define N3 0x300U 6839 #define N4 0x400U 6840 #define N5 0x500U 6841 #define N6 0x600U 6842 #define N7 0x700U 6843 #define N8 0x800U 6844 #define N9 0x900U 6845 #define N10 0xA00U 6846 #define N11 0xB00U 6847 #define N12 0xC00U 6848 #define N13 0xD00U 6849 #define N14 0xE00U 6850 #define N15 0xF00U 6851 #define NBRD 0xF00U 6852 /* Fields brought to you by the letter P */ 6853 #define P_MIN 0U 6854 #define P_MAX 3U 6855 #define P0 0x0U 6856 #define P1 0x100000U 6857 #define P2 0x200000U 6858 #define P3 0x300000U 6859 #define PBRD 0x700000U 6860 #define PP_MIN 0U 6861 #define PP_MAX 3U 6862 #define PP0 0x0U 6863 #define PP1 0x100000U 6864 #define PP2 0x200000U 6865 #define PP3 0x300000U 6866 #define PPBRD 0x700000U 6867 /* Fields brought to you by the letter Q */ 6868 #define Q_MIN 0U 6869 #define Q_MAX 3U 6870 #define Q0 0x0U 6871 #define Q1 0x100000U 6872 #define Q2 0x200000U 6873 #define Q3 0x300000U 6874 #define QBRD 0x700000U 6875 /* Fields brought to you by the letter R */ 6876 #define R_MIN 0U 6877 #define R_MAX 8U 6878 #define R0 0x0U 6879 #define R1 0x100U 6880 #define R2 0x200U 6881 #define R3 0x300U 6882 #define R4 0x400U 6883 #define R5 0x500U 6884 #define R6 0x600U 6885 #define R7 0x700U 6886 #define R8 0x800U 6887 #define RBRD 0xF00U 6888 /* Fields brought to you by the letter T */ 6889 #define T_MIN 0U 6890 #define T_MAX 15U 6891 #define T0 0x0U 6892 #define T1 0x10000U 6893 #define T2 0x20000U 6894 #define T3 0x30000U 6895 #define T4 0x40000U 6896 #define T5 0x50000U 6897 #define T6 0x60000U 6898 #define T7 0x70000U 6899 #define T8 0x80000U 6900 #define T9 0x90000U 6901 #define T10 0xA0000U 6902 #define T11 0xB0000U 6903 #define T12 0xC0000U 6904 #define T13 0xD0000U 6905 #define T14 0xE0000U 6906 #define T15 0xF0000U 6907 #define TBRD 0xF0000U 6908 /* Fields brought to you by the letter U */ 6909 #define U_MIN 0U 6910 #define U_MAX 1U 6911 #define U0 0x0U 6912 #define U1 0x100U 6913 #define UBRD 0xF00U 6914 /* Fields brought to you by the letter Y */ 6915 #define Y_MIN 0U 6916 #define Y_MAX 0U 6917 #define Y0 0x0U 6918 #define YBRD 0xF000000U 6919 6920 #define TACSM 0x40000U 6921 #define TACSMBRD 0x4F000U 6922 #define TALL 0xF0000U 6923 #define TALLBRD 0xFF000U 6924 #define TANIB 0x0U 6925 #define TANIBBRD 0xF000U 6926 #define TAPBONLY 0xD0000U 6927 #define TAPBONLYBRD 0xDF000U 6928 #define TDBYTE 0x10000U 6929 #define TDBYTEBRD 0x1F000U 6930 #define TDRTUB 0xC0000U 6931 #define TDRTUBBRD 0xCF000U 6932 #define TINITENG 0x90000U 6933 #define TINITENGBRD 0x9F000U 6934 #define TMASTER 0x20000U 6935 #define TMASTERBRD 0x2F000U 6936 #define TPPGC 0x70000U 6937 #define TPPGCBRD 0x7F000U 6938 #define TUCTL_MEM 0x50000U 6939 #define TUCTL_MEMBRD 0x5F000U 6940 6941 #define DBYTE_NUM 9U 6942 #define ANIB_NUM 12U 6943 6944 #endif /* DDRPHY_PHYINIT_CSR_ALL_DEFINES_H */ 6945