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Searched refs:CacheLineSize (Results 1 – 25 of 38) sorted by relevance

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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
DAArch64Subtarget.cpp102 CacheLineSize = 64; in initializeProperties()
154 CacheLineSize = 256; in initializeProperties()
171 CacheLineSize = 64; in initializeProperties()
195 CacheLineSize = 128; in initializeProperties()
203 CacheLineSize = 128; in initializeProperties()
242 CacheLineSize = 64; in initializeProperties()
256 CacheLineSize = 128; in initializeProperties()
263 CacheLineSize = 64; in initializeProperties()
268 CacheLineSize = 64; in initializeProperties()
280 CacheLineSize = 64; in initializeProperties()
DAArch64Subtarget.h107 uint16_t CacheLineSize = 0; variable
233 unsigned getCacheLineSize() const override { return CacheLineSize; } in getCacheLineSize()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64Subtarget.cpp96 CacheLineSize = 64; in initializeProperties()
111 CacheLineSize = 128; in initializeProperties()
119 CacheLineSize = 128; in initializeProperties()
138 CacheLineSize = 64; in initializeProperties()
152 CacheLineSize = 128; in initializeProperties()
159 CacheLineSize = 64; in initializeProperties()
DAArch64Subtarget.h201 uint16_t CacheLineSize = 0; variable
360 unsigned getCacheLineSize() const override { return CacheLineSize; } in getCacheLineSize()
/external/compiler-rt/lib/esan/
Dworking_set.cpp43 static const u32 CacheLineSize = 64; variable
195 CHECK(getFlags()->cache_line_size == CacheLineSize); in initializeShadowWorkingSet()
222 static const u32 KilobyteCachelines = (0x1 << 10) / CacheLineSize; in getSizeForPrinting()
233 return NumOfCachelines * CacheLineSize; in getSizeForPrinting()
/external/llvm/lib/Target/AArch64/
DAArch64Subtarget.cpp57 CacheLineSize = 64; in initializeProperties()
72 CacheLineSize = 128; in initializeProperties()
DAArch64Subtarget.h88 uint16_t CacheLineSize = 0; variable
197 unsigned getCacheLineSize() const { return CacheLineSize; } in getCacheLineSize()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DAMDGPUTargetStreamer.cpp305 const unsigned CacheLineSize = 1u << Log2CacheLineSize; in EmitCodeEnd() local
308 unsigned FillSize = 3 * CacheLineSize; in EmitCodeEnd()
312 FillSize = 16 * CacheLineSize; in EmitCodeEnd()
831 const unsigned CacheLineSize = 1u << Log2CacheLineSize; in EmitCodeEnd() local
834 unsigned FillSize = 3 * CacheLineSize; in EmitCodeEnd()
838 FillSize = 16 * CacheLineSize; in EmitCodeEnd()
843 OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4); in EmitCodeEnd()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
DLoopCacheAnalysis.cpp286 const SCEV *CacheLineSize = SE.getConstant(Stride->getType(), CLS); in computeRefCost() local
291 RefCost = SE.getUDivExpr(Numerator, CacheLineSize); in computeRefCost()
397 const SCEV *CacheLineSize = SE.getConstant(Stride->getType(), CLS); in isConsecutive() local
399 return SE.isKnownPredicate(ICmpInst::ICMP_ULT, Stride, CacheLineSize); in isConsecutive()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Analysis/
DLoopCacheAnalysis.cpp298 const SCEV *CacheLineSize = SE.getConstant(WiderType, CLS); in computeRefCost() local
302 RefCost = SE.getUDivExpr(Numerator, CacheLineSize); in computeRefCost()
490 const SCEV *CacheLineSize = SE.getConstant(Stride->getType(), CLS); in isConsecutive() local
493 return SE.isKnownPredicate(ICmpInst::ICMP_ULT, Stride, CacheLineSize); in isConsecutive()
DTargetTransformInfo.cpp35 static cl::opt<unsigned> CacheLineSize( variable
694 return CacheLineSize.getNumOccurrences() > 0 ? CacheLineSize in getCacheLineSize()
/external/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp27 CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64), variable
243 return CacheLineSize; in getCacheLineSize()
/external/gmmlib/Source/inc/umKmInc/
Dsharedata.h199 uint32_t CacheLineSize; // Processor CacheLine size member
/external/stressapptest/src/
Dsat.h138 int CacheLineSize();
Dsat.cc1417 line_size = CacheLineSize(); in InitializeThreads()
1487 int Sat::CacheLineSize() { in CacheLineSize() function in Sat
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp28 CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64), variable
637 if (CacheLineSize.getNumOccurrences() > 0) in getCacheLineSize()
638 return CacheLineSize; in getCacheLineSize()
/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Register/Intel/
DCpuid.h136 UINT32 CacheLineSize : 8; member
3949 UINT32 CacheLineSize : 8; member
/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/
DCpuid.h135 UINT32 CacheLineSize:8; member
3867 UINT32 CacheLineSize:8; member
/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/
DCpuid.h135 UINT32 CacheLineSize:8; member
3945 UINT32 CacheLineSize:8; member
/external/coreboot/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/
DPci22.h42 UINT8 CacheLineSize; member
DAcpi62.h2136 UINT32 CacheLineSize:16; member
/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/
DPci22.h36 UINT8 CacheLineSize; member
/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/
DPci22.h36 UINT8 CacheLineSize; member
/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/
DPci22.h36 UINT8 CacheLineSize; member
/external/coreboot/src/vendorcode/amd/pi/00730F01/Proc/CPU/
DcpuLateInit.h919 UINT16 CacheLineSize; ///< Cache line size in bytes member

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