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Searched refs:DRAM_CSR_MODIFY (Results 1 – 3 of 3) sorted by relevance

/external/coreboot/src/vendorcode/cavium/bdk/libdram/
Dlib_octeon_shared.c726 DRAM_CSR_MODIFY(c, node, BDK_LMCX_DLL_CTL2(ddr_interface_num), in cn78xx_lmc_dreset_init()
748 DRAM_CSR_MODIFY(c, node, BDK_LMCX_DLL_CTL2(ddr_interface_num), in cn78xx_lmc_dreset_init()
770 DRAM_CSR_MODIFY(c, node, BDK_LMCX_DLL_CTL2(ddr_interface_num), in cn78xx_lmc_dreset_init()
791 DRAM_CSR_MODIFY(c, node, BDK_LMCX_DLL_CTL2(ddr_interface_num), in cn78xx_lmc_dreset_init()
815 DRAM_CSR_MODIFY(c, node, BDK_LMCX_RESET_CTL(ddr_interface_num), in cn88xx_lmc_ddr3_reset()
980 DRAM_CSR_MODIFY(c, node, BDK_LMCX_DLL_CTL2(loop_interface_num), in initialize_ddr_clock()
1226 DRAM_CSR_MODIFY(c, node, BDK_LMCX_DDR_PLL_CTL(loop_interface_num), in initialize_ddr_clock()
1264 DRAM_CSR_MODIFY(c, node, BDK_LMCX_DDR_PLL_CTL(loop_interface_num), in initialize_ddr_clock()
1272 DRAM_CSR_MODIFY(c, node, BDK_LMCX_DDR_PLL_CTL(loop_interface_num), in initialize_ddr_clock()
1292 DRAM_CSR_MODIFY(c, node, BDK_LMCX_DDR_PLL_CTL(loop_interface_num), in initialize_ddr_clock()
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Ddram-csr.h81 #define DRAM_CSR_MODIFY(name, node, csr, code_block) do { \ macro
Ddram-init-ddr3.c729 DRAM_CSR_MODIFY(ext_config, node, BDK_LMCX_EXT_CONFIG(ddr_interface_num), in Perform_Read_Deskew_Training()
738 DRAM_CSR_MODIFY(phy_ctl, node, BDK_LMCX_PHY_CTL(ddr_interface_num), in Perform_Read_Deskew_Training()
747 DRAM_CSR_MODIFY(phy_ctl, node, BDK_LMCX_PHY_CTL(ddr_interface_num), in Perform_Read_Deskew_Training()
1388 DRAM_CSR_MODIFY(c, node, BDK_LMCX_RLEVEL_CTL(ddr_interface_num), in octeon_read_lmcx_ddr3_rlevel_dbg()