Searched refs:MISC_CTL_REG (Results 1 – 2 of 2) sorted by relevance
| /external/coreboot/src/superio/aspeed/common/ | ||
| D | aspeed.h | 55 #define MISC_CTL_REG 0x2C macro |
| D | early_config.c | 405 port80[Step5].reg = MISC_CTL_REG; in aspeed_enable_port80_direct_gpio() |