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Searched refs:MSM_BOOT_UART_DM_CSR (Results 1 – 8 of 8) sorted by relevance

/external/coreboot/src/soc/qualcomm/ipq40xx/
Duart.c205 if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == UART_DM_CLK_RX_TX_BIT_RATE) in uart_init()
217 write32(MSM_BOOT_UART_DM_CSR(dm_base), UART_DM_CLK_RX_TX_BIT_RATE); in uart_init()
/external/coreboot/src/soc/qualcomm/qcs405/
Duart.c208 if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == 0xFF) in uart_init()
217 write32(MSM_BOOT_UART_DM_CSR(dm_base), 0xFF); in uart_init()
/external/coreboot/src/soc/qualcomm/qcs405/include/soc/
Duart.h51 #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) macro
53 #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) macro
/external/coreboot/src/soc/qualcomm/ipq806x/
Duart.c280 if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == UART_DM_CLK_RX_TX_BIT_RATE) in uart_init()
296 write32(MSM_BOOT_UART_DM_CSR(dm_base), UART_DM_CLK_RX_TX_BIT_RATE); in uart_init()
/external/coreboot/src/soc/qualcomm/ipq806x/include/soc/
Dipq_uart.h52 #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) macro
54 #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) macro
/external/coreboot/src/soc/qualcomm/ipq40xx/include/soc/
Dipq_uart.h51 #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) macro
53 #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) macro
/external/coreboot/payloads/libpayload/drivers/serial/
Dipq40xx.c75 #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) macro
77 #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) macro
Dqcs405.c75 #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) macro
77 #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) macro