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Searched refs:NewOpcode (Results 1 – 25 of 102) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCFGOptimizer.cpp84 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
87 NewOpcode = Hexagon::J2_jumpf; in InvertAndChangeJumpTarget()
90 NewOpcode = Hexagon::J2_jumpt; in InvertAndChangeJumpTarget()
93 NewOpcode = Hexagon::J2_jumpfnewpt; in InvertAndChangeJumpTarget()
96 NewOpcode = Hexagon::J2_jumptnewpt; in InvertAndChangeJumpTarget()
102 MI.setDesc(TII->get(NewOpcode)); in InvertAndChangeJumpTarget()
/external/llvm/lib/Target/Hexagon/
DHexagonCFGOptimizer.cpp75 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
78 NewOpcode = Hexagon::J2_jumpf; in InvertAndChangeJumpTarget()
82 NewOpcode = Hexagon::J2_jumpt; in InvertAndChangeJumpTarget()
86 NewOpcode = Hexagon::J2_jumpfnewpt; in InvertAndChangeJumpTarget()
90 NewOpcode = Hexagon::J2_jumptnewpt; in InvertAndChangeJumpTarget()
97 MI.setDesc(TII->get(NewOpcode)); in InvertAndChangeJumpTarget()
DHexagonVLIWPacketizer.cpp422 int NewOpcode; in promoteToDotNew() local
424 NewOpcode = HII->getDotNewPredOp(MI, MBPI); in promoteToDotNew()
426 NewOpcode = HII->getDotNewOp(MI); in promoteToDotNew()
427 MI->setDesc(HII->get(NewOpcode)); in promoteToDotNew()
432 int NewOpcode = HII->getDotOldOp(MI->getOpcode()); in demoteToDotOld() local
433 MI->setDesc(HII->get(NewOpcode)); in demoteToDotOld()
768 int NewOpcode = HII->getDotNewOp(MI); in canPromoteToDotNew() local
769 const MCInstrDesc &D = HII->get(NewOpcode); in canPromoteToDotNew()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/
DHexagonCFGOptimizer.cpp85 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
88 NewOpcode = Hexagon::J2_jumpf; in InvertAndChangeJumpTarget()
91 NewOpcode = Hexagon::J2_jumpt; in InvertAndChangeJumpTarget()
94 NewOpcode = Hexagon::J2_jumpfnewpt; in InvertAndChangeJumpTarget()
97 NewOpcode = Hexagon::J2_jumptnewpt; in InvertAndChangeJumpTarget()
103 MI.setDesc(TII->get(NewOpcode)); in InvertAndChangeJumpTarget()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DMVEVPTBlockPass.cpp76 unsigned &NewOpcode) { in findVCMPToFoldIntoVPST() argument
83 if (!(NewOpcode = VCMPOpcodeToVPT(Def->getOpcode()))) in findVCMPToFoldIntoVPST()
144 unsigned NewOpcode; in InsertVPTBlocks() local
145 MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, RDA, NewOpcode); in InsertVPTBlocks()
148 MIBuilder = BuildMI(Block, MI, dl, TII->get(NewOpcode)); in InsertVPTBlocks()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/
DMVEVPTBlockPass.cpp68 unsigned &NewOpcode) { in findVCMPToFoldIntoVPST() argument
83 NewOpcode = VCMPOpcodeToVPT(CmpMI->getOpcode()); in findVCMPToFoldIntoVPST()
84 if (NewOpcode == 0) in findVCMPToFoldIntoVPST()
275 unsigned NewOpcode; in InsertVPTBlocks() local
277 if (MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, TRI, NewOpcode)) { in InsertVPTBlocks()
279 MIBuilder = BuildMI(Block, MI, DL, TII->get(NewOpcode)); in InsertVPTBlocks()
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp138 int NewOpcode; in InsertSPImmInst() local
140 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
146 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
147 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
153 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp137 int NewOpcode; in InsertSPImmInst() local
139 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
145 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
146 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
152 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp137 int NewOpcode; in InsertSPImmInst() local
139 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
145 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
146 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
152 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/
DSIShrinkInstructions.cpp359 unsigned NewOpcode = AMDGPU::getMIMGOpcode(Info->BaseOpcode, NewEncoding, in shrinkMIMG() local
361 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
395 unsigned NewOpcode = AMDGPU::INSTRUCTION_LIST_END; in shrinkMadFma() local
412 NewOpcode = AMDGPU::V_MADAK_F32; in shrinkMadFma()
415 NewOpcode = AMDGPU::V_FMAAK_F32; in shrinkMadFma()
418 NewOpcode = AMDGPU::V_MADAK_F16; in shrinkMadFma()
422 NewOpcode = ST->hasTrue16BitInsts() ? AMDGPU::V_FMAAK_F16_t16 in shrinkMadFma()
441 NewOpcode = AMDGPU::V_MADMK_F32; in shrinkMadFma()
444 NewOpcode = AMDGPU::V_FMAMK_F32; in shrinkMadFma()
447 NewOpcode = AMDGPU::V_MADMK_F16; in shrinkMadFma()
[all …]
DGCNCreateVOPD.cpp66 int NewOpcode = AMDGPU::getVOPDFull(AMDGPU::getVOPDOpcode(Opc1), in doReplace() local
68 assert(NewOpcode != -1 && in doReplace()
72 FirstMI->getDebugLoc(), SII->get(NewOpcode)) in doReplace()
DR600MachineCFGStructurizer.cpp200 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
202 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
204 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
205 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
208 MachineBasicBlock::iterator I, int NewOpcode,
435 int NewOpcode, const DebugLoc &DL) { in insertInstrEnd() argument
437 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
444 int NewOpcode, in insertInstrBefore() argument
447 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
457 MachineBasicBlock::iterator I, int NewOpcode) { in insertInstrBefore() argument
[all …]
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARC/
DARCOptAddrMode.cpp111 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
264 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode()); in tryToCombine() local
265 assert(NewOpcode > 0 && "No postincrement form found"); in tryToCombine()
267 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2)); in tryToCombine()
452 void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode, in changeToAddrMode() argument
470 Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode)); in changeToAddrMode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FixupLEAs.cpp389 unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode()); in optTwoAddrLEA() local
395 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
400 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
412 unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC); in optTwoAddrLEA() local
416 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
419 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
423 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp); in optTwoAddrLEA() local
426 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
430 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/
DX86FixupLEAs.cpp531 unsigned NewOpcode = AluI->getOpcode(); in optLEAALU() local
532 NewMI1 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), in optLEAALU()
537 NewMI2 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), in optLEAALU()
595 unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode()); in optTwoAddrLEA() local
601 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
606 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
619 unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC); in optTwoAddrLEA() local
623 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
626 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
630 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp); in optTwoAddrLEA() local
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCOptAddrMode.cpp100 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
253 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode()); in tryToCombine() local
254 assert(NewOpcode > 0 && "No postincrement form found"); in tryToCombine()
256 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2)); in tryToCombine()
441 void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode, in changeToAddrMode() argument
459 Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode)); in changeToAddrMode()
/external/llvm/lib/Target/X86/
DX86FixupLEAs.cpp273 int NewOpcode; in fixupIncDec() local
277 NewOpcode = isINC ? X86::INC16r : X86::DEC16r; in fixupIncDec()
281 NewOpcode = isINC ? X86::INC32r : X86::DEC32r; in fixupIncDec()
284 NewOpcode = isINC ? X86::INC64r : X86::DEC64r; in fixupIncDec()
289 BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode)) in fixupIncDec()
/external/llvm/lib/Target/AMDGPU/
DAMDILCFGStructurizer.cpp228 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
230 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
232 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
233 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
236 MachineBasicBlock::iterator I, int NewOpcode,
454 int NewOpcode, const DebugLoc &DL) { in insertInstrEnd() argument
456 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
463 int NewOpcode, in insertInstrBefore() argument
466 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
476 MachineBasicBlock::iterator I, int NewOpcode) { in insertInstrBefore() argument
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDILCFGStructurizer.cpp222 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
224 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
226 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
227 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
230 MachineBasicBlock::iterator I, int NewOpcode,
457 int NewOpcode, const DebugLoc &DL) { in insertInstrEnd() argument
459 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
466 int NewOpcode, in insertInstrBefore() argument
469 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
479 MachineBasicBlock::iterator I, int NewOpcode) { in insertInstrBefore() argument
[all …]
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp231 int NewOpcode = -1; in encodeInstruction() local
234 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
235 if (NewOpcode == -1) in encodeInstruction()
236 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
239 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); in encodeInstruction()
242 if (NewOpcode == -1) in encodeInstruction()
243 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
245 if (NewOpcode != -1) { in encodeInstruction()
249 Opcode = NewOpcode; in encodeInstruction()
250 TmpInst.setOpcode (NewOpcode); in encodeInstruction()
/external/llvm/lib/Target/SystemZ/
DSystemZFrameLowering.cpp458 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue() local
462 if (!NewOpcode) { in emitEpilogue()
467 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
468 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
471 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()
DSystemZInstrInfo.cpp52 unsigned NewOpcode) const { in splitMove()
79 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
80 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
97 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() local
98 assert(NewOpcode && "No support for huge argument lists yet"); in splitAdjDynAlloc()
99 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
845 unsigned NewOpcode; in convertToThreeAddress() local
847 NewOpcode = SystemZ::RISBG; in convertToThreeAddress()
850 NewOpcode = SystemZ::RISBGN; in convertToThreeAddress()
852 NewOpcode = SystemZ::RISBMux; in convertToThreeAddress()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp193 int NewOpcode = -1; in encodeInstruction() local
196 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
197 if (NewOpcode == -1) in encodeInstruction()
198 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
201 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); in encodeInstruction()
204 if (NewOpcode == -1) in encodeInstruction()
205 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
207 if (NewOpcode != -1) { in encodeInstruction()
211 TmpInst.setOpcode (NewOpcode); in encodeInstruction()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp191 int NewOpcode = -1; in encodeInstruction() local
194 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
195 if (NewOpcode == -1) in encodeInstruction()
196 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
199 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); in encodeInstruction()
202 if (NewOpcode == -1) in encodeInstruction()
203 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
205 if (NewOpcode != -1) { in encodeInstruction()
209 TmpInst.setOpcode (NewOpcode); in encodeInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZFrameLowering.cpp604 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue() local
608 if (!NewOpcode) { in emitEpilogue()
613 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
614 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
617 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()

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