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Searched refs:ReverseOrderSLT (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp2766 bool ReverseOrderSLT, IsUnsigned, IsLikely, AcceptsEquality; in expandCondBranches() local
2843 ReverseOrderSLT = false; in expandCondBranches()
2854 ReverseOrderSLT = true; in expandCondBranches()
2865 ReverseOrderSLT = false; in expandCondBranches()
2876 ReverseOrderSLT = true; in expandCondBranches()
3004 ReverseOrderSLT ? TrgReg : SrcReg, in expandCondBranches()
3005 ReverseOrderSLT ? SrcReg : TrgReg, IDLoc, STI); in expandCondBranches()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp3874 bool ReverseOrderSLT, IsUnsigned, IsLikely, AcceptsEquality; in expandCondBranches() local
3951 ReverseOrderSLT = false; in expandCondBranches()
3963 ReverseOrderSLT = true; in expandCondBranches()
3975 ReverseOrderSLT = false; in expandCondBranches()
3987 ReverseOrderSLT = true; in expandCondBranches()
4116 ReverseOrderSLT ? TrgReg : SrcReg, in expandCondBranches()
4117 ReverseOrderSLT ? SrcReg : TrgReg, IDLoc, STI); in expandCondBranches()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp3893 bool ReverseOrderSLT, IsUnsigned, IsLikely, AcceptsEquality; in expandCondBranches() local
3970 ReverseOrderSLT = false; in expandCondBranches()
3982 ReverseOrderSLT = true; in expandCondBranches()
3994 ReverseOrderSLT = false; in expandCondBranches()
4006 ReverseOrderSLT = true; in expandCondBranches()
4135 ReverseOrderSLT ? TrgReg : SrcReg, in expandCondBranches()
4136 ReverseOrderSLT ? SrcReg : TrgReg, IDLoc, STI); in expandCondBranches()