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Searched refs:SA_DEVFN_IPU (Results 1 – 20 of 20) sorted by relevance

/external/coreboot/src/soc/intel/alderlake/
Dacpi.c170 { SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 },
251 if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { in soc_fill_dmar()
Dchip.c96 case SA_DEVFN_IPU: return "IPU0"; in soc_acpi_name()
Dfsp_params.c94 FIXED_INT_PIRQ(SA_DEVFN_IPU, PCI_INT_A, PIRQ_A),
/external/coreboot/src/soc/intel/cannonlake/
Dacpi.c171 { SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 },
273 if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { in soc_fill_dmar()
Dfsp_params.c69 ANY_PIRQ(SA_DEVFN_IPU),
/external/coreboot/src/soc/intel/tigerlake/
Dacpi.c166 { SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 },
244 if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { in soc_fill_dmar()
Dchip.c89 case SA_DEVFN_IPU: return "IPU0"; in soc_acpi_name()
Dfsp_params.c118 ANY_PIRQ(SA_DEVFN_IPU),
/external/coreboot/src/soc/intel/jasperlake/
Dchip.c66 case SA_DEVFN_IPU: return "IPU0"; in soc_acpi_name()
Dacpi.c185 if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { in soc_fill_dmar()
/external/coreboot/src/soc/intel/cannonlake/romstage/
Dfsp_params.c96 m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU); in platform_fsp_memory_init_params_cb()
/external/coreboot/src/soc/intel/jasperlake/romstage/
Dfsp_params.c90 m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU); in soc_memory_init_params()
/external/coreboot/src/soc/intel/apollolake/include/soc/
Dpci_devs.h34 #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) macro
/external/coreboot/src/soc/intel/jasperlake/include/soc/
Dpci_devs.h34 #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) macro
/external/coreboot/src/soc/intel/cannonlake/include/soc/
Dpci_devs.h42 #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) macro
/external/coreboot/src/soc/intel/tigerlake/romstage/
Dfsp_params.c149 m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU); in soc_memory_init_params()
/external/coreboot/src/soc/intel/tigerlake/include/soc/
Dpci_devs.h42 #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) macro
/external/coreboot/src/soc/intel/alderlake/include/soc/
Dpci_devs.h41 #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) macro
/external/coreboot/src/soc/intel/alderlake/romstage/
Dfsp_params.c207 m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU); in fill_fspm_ipu_params()
/external/coreboot/src/soc/intel/apollolake/
Dchip.c450 case SA_DEVFN_IPU: in disable_dev()