| /external/mesa3d/src/amd/addrlib/src/chip/r800/ |
| D | si_gb_reg.h | 131 unsigned int array_mode : 4; member
166 unsigned int array_mode : 4; member
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| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| D | nv50_state_validate.c | 26 uint32_t array_size = 0xffff, array_mode = 0; in nv50_validate_fb() local
52 array_mode = NV50_3D_RT_ARRAY_MODE_MODE_3D; /* 1 << 16 */ in nv50_validate_fb()
55 assert(mt->layout_3d || !array_mode || array_size == 1); in nv50_validate_fb()
70 PUSH_DATA (push, array_mode | array_size); in nv50_validate_fb()
71 nv50->rt_array_mode = array_mode | array_size; in nv50_validate_fb()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_texture.c | 182 enum radeon_surf_mode array_mode, in r600_init_surface() argument
230 flags, bpe, array_mode, surface); in r600_init_surface()
278 enum radeon_surf_mode *array_mode, in r600_surface_import_metadata() argument
289 *array_mode = RADEON_SURF_MODE_2D; in r600_surface_import_metadata()
291 *array_mode = RADEON_SURF_MODE_1D; in r600_surface_import_metadata()
293 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; in r600_surface_import_metadata()
1093 enum radeon_surf_mode array_mode; in r600_texture_from_handle() local
1112 &array_mode, &is_scanout); in r600_texture_from_handle()
1114 r = r600_init_surface(rscreen, &surface, templ, array_mode, in r600_texture_from_handle()
1807 enum radeon_surf_mode array_mode; in r600_texture_from_memobj() local
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| D | r600_state.c | 665 unsigned char swizzle[4], array_mode = 0; in r600_create_sampler_view_custom() local
734 array_mode = V_038000_ARRAY_LINEAR_ALIGNED; in r600_create_sampler_view_custom()
737 array_mode = V_038000_ARRAY_1D_TILED_THIN1; in r600_create_sampler_view_custom()
740 array_mode = V_038000_ARRAY_2D_TILED_THIN1; in r600_create_sampler_view_custom()
746 S_038000_TILE_MODE(array_mode) | in r600_create_sampler_view_custom()
1032 unsigned level, pitch, slice, format, offset, array_mode; in r600_init_depth_surface() local
1043 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; in r600_init_depth_surface()
1048 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; in r600_init_depth_surface()
1055 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format); in r600_init_depth_surface()
2873 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; in r600_dma_copy_tile() local
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| D | evergreen_state.c | 739 unsigned char array_mode = 0, non_disp_tiling = 0; in evergreen_fill_tex_resource_words() local
810 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED; in evergreen_fill_tex_resource_words()
813 array_mode = V_028C70_ARRAY_2D_TILED_THIN1; in evergreen_fill_tex_resource_words()
816 array_mode = V_028C70_ARRAY_1D_TILED_THIN1; in evergreen_fill_tex_resource_words()
859 S_030004_ARRAY_MODE(array_mode)); in evergreen_fill_tex_resource_words()
1358 unsigned format, array_mode; in evergreen_init_depth_surface() local
1370 array_mode = V_028C70_ARRAY_2D_TILED_THIN1; in evergreen_init_depth_surface()
1375 array_mode = V_028C70_ARRAY_1D_TILED_THIN1; in evergreen_init_depth_surface()
1389 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) | in evergreen_init_depth_surface()
3859 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; in evergreen_dma_copy_tile() local
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | radeon_uvd_enc.h | 276 uint32_t array_mode; member
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| D | si_texture.c | 200 const struct pipe_resource *ptex, enum radeon_surf_mode array_mode, in si_init_surface() argument
257 (sscreen->info.gfx_level >= GFX9 || array_mode == RADEON_SURF_MODE_2D)) { in si_init_surface()
394 r = sscreen->ws->surface_init(sscreen->ws, &sscreen->info, ptex, flags, bpe, array_mode, in si_init_surface()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 613 unsigned array_mode = radv_choose_tiling(device, pCreateInfo, image_format); in radv_get_surface_flags() local
623 flags = RADEON_SURF_SET(array_mode, MODE); in radv_get_surface_flags()
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| /external/mesa3d/src/amd/addrlib/src/r800/ |
| D | ciaddrlib.cpp | 1590 UINT_32 regArrayMode = gbTileMode.f.array_mode; in ReadGbTileMode()
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| D | siaddrlib.cpp | 3077 UINT_32 regArrayMode = gbTileMode.f.array_mode; in ReadGbTileMode()
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| /external/flatbuffers/src/ |
| D | idl_gen_cpp.cpp | 3837 GenArrayArgMode array_mode) { in GenStructConstructor() argument
3843 const auto init_arrays = (array_mode != kArrayArgModeNone); in GenStructConstructor()
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| /external/mesa3d/docs/relnotes/ |
| D | 22.2.0.rst | 5343 - radeonsi/vcn: Add support of array_mode for gfx11
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