Home
last modified time | relevance | path

Searched refs:blsp (Results 1 – 6 of 6) sorted by relevance

/external/coreboot/src/soc/qualcomm/qcs405/
Dclock.c195 void clock_configure_spi(int blsp, int qup, uint32_t hz) in clock_configure_spi() argument
199 if (blsp == 1) { in clock_configure_spi()
225 } else if (blsp == 2) { in clock_configure_spi()
228 printk(BIOS_ERR, "BLSP %d not supported\n", blsp); in clock_configure_spi()
253 void clock_enable_spi(int blsp, int qup) in clock_enable_spi() argument
255 if (blsp == 1) { in clock_enable_spi()
273 } else if (blsp == 2) in clock_enable_spi()
276 printk(BIOS_ERR, "BLSP%d not supported\n", blsp); in clock_enable_spi()
279 void clock_disable_spi(int blsp, int qup) in clock_disable_spi() argument
281 if (blsp == 1) { in clock_disable_spi()
[all …]
Dspi.c690 int blsp = 2; in spi_ctrlr_setup() local
711 blsp = 1; in spi_ctrlr_setup()
714 clock_configure_spi(blsp, qup, ds->freq); in spi_ctrlr_setup()
715 clock_enable_spi(blsp, qup); in spi_ctrlr_setup()
DMakefile.mk12 all-y += blsp.c
/external/coreboot/src/mainboard/google/gale/
DMakefile.mk11 verstage-y += blsp.c
21 romstage-y += blsp.c
29 ramstage-y += blsp.c
/external/coreboot/src/soc/qualcomm/ipq40xx/
DMakefile.mk13 verstage-y += blsp.c
28 romstage-y += blsp.c
42 ramstage-y += blsp.c
/external/coreboot/src/soc/qualcomm/qcs405/include/soc/
Dclock.h173 void clock_configure_spi(int blsp, int qup, uint32_t hz);
176 void clock_enable_spi(int blsp, int qup);
177 void clock_disable_spi(int blsp, int qup);