| /external/llvm/test/MC/ARM/ |
| D | aligned-blx.s | 19 @ "Align(PC, 4)" during blx operation.
25 blx _elsewhere
26 blx _aligned @ PC=0 (mod 4)
27 blx _aligned @ PC=0 (mod 4)
29 blx _aligned @ PC=2 (mod 4)
31 @ CHECK: blx _elsewhere
32 @ CHECK: ff f7 fa ef blx _aligned
33 @ CHECK: ff f7 f8 ef blx _aligned
34 @ CHECK: ff f7 f6 ef blx _aligned
|
| D | misaligned-blx.s | 23 @ "Align(PC, 4)" during blx operation.
29 blx _misaligned @ PC=0 (mod 4)
31 blx _misaligned @ PC=2 (mod 4)
33 blx _aligned @ PC=0 (mod 4)
35 blx _aligned @ PC=2 (mod 4)
38 @ CHECK: blx _misaligned
40 @ CHECK: blx _misaligned
|
| D | complex-operands.s | 25 blx return
29 @ CHECK: blx return
35 blx return
39 @ CHECK: blx return
|
| D | thumb.s | 13 blx r9
14 blx r10
15 @ CHECK: blx r9 @ encoding: [0xc8,0x47]
16 @ CHECK: blx r10 @ encoding: [0xd0,0x47]
|
| D | arm-branches.s | 10 blx #2
15 @ CHECK: blx #2 @ encoding: [0x00,0x00,0x00,0xfb]
|
| D | thumb-branch-errors.s | 11 blx #2
22 @ CHECK: blx #2
|
| D | directive-tlsdescseq-diagnostics.s | 30 blx invalid(tlsdescseq)
33 @ CHECK: blx invalid(tlsdescseq)
|
| D | macho-relocs-with-addend.s | 13 blx _dest+20
19 blx _dest+20
|
| D | directive-tlsdescseq.s | 15 blx r3
32 @ CHECK-ASM: blx r3
|
| D | basic-thumb-instructions.s | 153 blx #884800
154 blx #1769600
156 @ CHECK: blx #884800 @ encoding: [0xd8,0xf0,0x20,0xe8]
157 @ CHECK: blx #1769600 @ encoding: [0xb0,0xf1,0x40,0xe8]
181 blx _baz
187 @ CHECK: blx _baz @ encoding: [A,0xf0'A',A,0xc0'A']
189 @ CHECK-BE: blx _baz @ encoding: [0xf0'A',A,0xc0'A',A]
196 blx r4
198 @ CHECK: blx r4 @ encoding: [0xa0,0x47]
|
| D | elf-reloc-condcall.s | 6 blx some_label
|
| D | coff-relocations.s | 38 blx r0
43 @ CHECK-ENCODING-NEXT: blx r0
|
| /external/llvm/test/CodeGen/ARM/ |
| D | darwin-tls.ll | 23 ; T2-MOVT-PIC: blx [[TLV_GET_ADDR]]
31 ; T2-LIT-PIC: blx [[TLV_GET_ADDR]]
40 ; T2-MOVT-STATIC: blx [[TLV_GET_ADDR]]
46 ; T2-LIT-STATIC: blx [[TLV_GET_ADDR]]
60 ; ARM-MOVT-PIC: blx [[TLV_GET_ADDR]]
68 ; ARM-LIT-PIC: blx [[TLV_GET_ADDR]]
77 ; ARM-MOVT-STATIC: blx [[TLV_GET_ADDR]]
83 ; ARM-LIT-STATIC: blx [[TLV_GET_ADDR]]
101 ; T2-MOVT-PIC: blx [[TLV_GET_ADDR]]
110 ; T2-LIT-PIC: blx [[TLV_GET_ADDR]]
[all …]
|
| D | thumb_indirect_calls.ll | 16 ; CHECK-V4T-NOT: blx
21 ; CHECK-V5T: blx [[CALLEE]]
37 ; CHECK-V5T: blx
38 ; CHECK-V5T: blx
|
| D | cxx-tlscc.ll | 28 ; THUMB: blx
30 ; THUMB: blx
33 ; THUMB: blx
55 ; CHECK: blx
57 ; CHECK: blx
60 ; CHECK: blx
73 ; CHECK-O0: blx
75 ; CHECK-O0: blx
78 ; CHECK-O0: blx
90 ; CHECK: blx
|
| D | subtarget-features-long-calls.ll | 10 ; NO-OPTION: blx [[R0]]
16 ; LONGCALL: blx [[R0]]
34 ; LONGCALL: blx [[R0]]
|
| D | fast-isel-call.ll | 122 ; ARM-LONG: blx [[R]]
143 ; THUMB-LONG: blx [[R]]
158 ; ARM: blx r1
162 ; THUMB: blx r1
183 ; ARM-LONG: blx r2
190 ; THUMB-LONG: blx r2
|
| /external/compiler-rt/test/builtins/Unit/arm/ |
| D | call_apsr.S | 27 blx ip
40 blx r2
|
| /external/capstone/suite/MC/ARM/ |
| D | thumb.s.cs | 5 0xc8,0x47 = blx r9
6 0xd0,0x47 = blx r10
|
| D | basic-thumb-instructions.s.cs | 31 0xd8,0xf0,0x20,0xe8 = blx #884804
32 0xb0,0xf1,0x40,0xe8 = blx #1769604
36 0xa0,0x47 = blx r4
|
| /external/coreboot/src/vendorcode/amd/psp_verstage/picasso/bl_uapp/ |
| D | bl_uapp_startup.S | 61 blx r2
69 blx r2
|
| /external/vixl/benchmarks/aarch32/ |
| D | asm-disasm-speed-test.cc | 344 __ blx(r2); in Generate_2() local
360 __ blx(r3); in Generate_2() local
365 __ blx(r3); in Generate_2() local
370 __ blx(r3); in Generate_2() local
396 __ blx(r3); in Generate_2() local
411 __ blx(r3); in Generate_2() local
420 __ blx(r3); in Generate_2() local
427 __ blx(r3); in Generate_2() local
445 __ blx(r3); in Generate_2() local
514 __ blx(r3); in Generate_3() local
[all …]
|
| /external/coreboot/src/vendorcode/amd/psp_verstage/common/bl_uapp/ |
| D | bl_uapp_startup.S | 61 blx r2
|
| /external/coreboot/src/vendorcode/amd/psp_verstage/cezanne/bl_uapp/ |
| D | bl_uapp_startup.S | 61 blx r2
|
| /external/coreboot/src/vendorcode/amd/psp_verstage/mendocino/bl_uapp/ |
| D | bl_uapp_startup.S | 61 blx r2
|