Searched refs:db_alpha_to_mask (Results 1 – 2 of 2) sorted by relevance
487 unsigned db_alpha_to_mask; in si_create_blend_state_mode() local489 db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) | in si_create_blend_state_mode()494 db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) | in si_create_blend_state_mode()501 ac_pm4_set_reg(&pm4->base, R_02807C_DB_ALPHA_TO_MASK, db_alpha_to_mask); in si_create_blend_state_mode()503 ac_pm4_set_reg(&pm4->base, R_028B70_DB_ALPHA_TO_MASK, db_alpha_to_mask); in si_create_blend_state_mode()
5162 unsigned db_alpha_to_mask = 0; in radv_emit_alpha_to_coverage_enable() local5165 db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) | in radv_emit_alpha_to_coverage_enable()5169 db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) | in radv_emit_alpha_to_coverage_enable()5174 db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(d->vk.ms.alpha_to_coverage_enable); in radv_emit_alpha_to_coverage_enable()5177 radeon_set_context_reg(cmd_buffer->cs, R_02807C_DB_ALPHA_TO_MASK, db_alpha_to_mask); in radv_emit_alpha_to_coverage_enable()5179 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, db_alpha_to_mask); in radv_emit_alpha_to_coverage_enable()