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Searched refs:ddr3psoft (Results 1 – 2 of 2) sorted by relevance

/external/coreboot/src/vendorcode/cavium/bdk/libdram/
Dlib_octeon_shared.c849 reset_ctl.cn8.ddr3psoft = 0; in initialize_ddr_clock()
/external/coreboot/src/vendorcode/cavium/include/bdk/libbdk-arch/
Dbdk-csrs-lmc.h16230 …uint64_t ddr3psoft : 1; /**< [ 2: 2](R/W/H) Memory reset. 1 = Enable preserve mode … member
16291 …uint64_t ddr3psoft : 1; /**< [ 2: 2](R/W/H) Memory reset. 1 = Enable preserve mode …