| /external/coreboot/src/vendorcode/cavium/bdk/libdram/ |
| D | libdram.c | 295 const ddr_configuration_t *ddr_config = dram_config->config; in libdram_config() local
299 ddr_clock_hertz = dram_get_default_spd_speed(node, ddr_config); in libdram_config()
348 if (ddr_config[i].dimm_config_table[0].spd_addr || in libdram_config()
349 ddr_config[i].dimm_config_table[0].spd_ptr) in libdram_config()
362 int ddr_type = get_ddr_type(node, &ddr_config[0].dimm_config_table[0]); in libdram_config()
363 … int spd_dimm_type = get_dimm_module_type(node, &ddr_config[0].dimm_config_table[0], ddr_type); in libdram_config()
386 ddr_config, in libdram_config()
|
| /external/coreboot/src/soc/intel/alderlake/ |
| D | meminit.c | 39 static void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct mem_ddr_config *ddr_config) in meminit_ddr() argument
41 mem_cfg->DqPinsInterleaved = ddr_config->dq_pins_interleaved; in meminit_ddr()
258 meminit_ddr(mem_cfg, &mb_cfg->ddr_config); in memcfg_init()
262 meminit_ddr(mem_cfg, &mb_cfg->ddr_config); in memcfg_init()
|
| /external/coreboot/src/mainboard/msi/ms7d25/ |
| D | romstage_fsp_params.c | 20 .ddr_config = {
36 .ddr_config = {
|
| /external/coreboot/src/mainboard/msi/ms7e06/ |
| D | romstage_fsp_params.c | 20 .ddr_config = {
36 .ddr_config = {
|
| /external/coreboot/src/soc/intel/meteorlake/ |
| D | meminit.c | 31 static void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct mem_ddr_config *ddr_config) in meminit_ddr() argument
33 mem_cfg->DqPinsInterleaved = ddr_config->dq_pins_interleaved; in meminit_ddr()
206 meminit_ddr(mem_cfg, &mb_cfg->ddr_config); in memcfg_init()
|
| /external/trusty/arm-trusted-firmware/plat/intel/soc/agilex5/soc/ |
| D | agilex5_memory_controller.c | 28 #define DDR_CONFIG_ELEMENTS (ARRAY_SIZE(ddr_config))
37 uint32_t ddr_config[] = { variable
67 if (ddr_conf == ddr_config[i]) in match_ddr_conf()
|
| /external/arm-trusted-firmware/plat/intel/soc/agilex/soc/ |
| D | agilex_memory_controller.c | 27 #define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t))
36 uint32_t ddr_config[] = { variable
66 if (ddr_conf == ddr_config[i]) in match_ddr_conf()
|
| /external/trusty/arm-trusted-firmware/plat/intel/soc/agilex/soc/ |
| D | agilex_memory_controller.c | 27 #define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t))
36 uint32_t ddr_config[] = { variable
66 if (ddr_conf == ddr_config[i]) in match_ddr_conf()
|
| /external/arm-trusted-firmware/plat/intel/soc/stratix10/soc/ |
| D | s10_memory_controller.c | 31 #define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t))
40 uint32_t ddr_config[] = { variable
70 if (ddr_conf == ddr_config[i]) in match_ddr_conf()
|
| /external/trusty/arm-trusted-firmware/plat/intel/soc/stratix10/soc/ |
| D | s10_memory_controller.c | 31 #define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t))
40 uint32_t ddr_config[] = { variable
70 if (ddr_conf == ddr_config[i]) in match_ddr_conf()
|
| /external/coreboot/src/mainboard/google/brya/variants/moli/ |
| D | memory.c | 25 .ddr_config = {
|
| /external/coreboot/src/mainboard/google/brya/variants/aurash/ |
| D | memory.c | 25 .ddr_config = {
|
| /external/coreboot/src/mainboard/aoostar/wtr_r1/ |
| D | romstage_fsp_params.c | 21 .ddr_config = {
|
| /external/coreboot/src/mainboard/google/brya/variants/baseboard/hades/ |
| D | memory.c | 25 .ddr_config = {
|
| /external/coreboot/src/mainboard/system76/rpl/variants/addw3/ |
| D | romstage.c | 12 .ddr_config = { in mainboard_memory_init_params()
|
| /external/coreboot/src/mainboard/system76/rpl/variants/addw4/ |
| D | romstage.c | 12 .ddr_config = { in mainboard_memory_init_params()
|
| /external/coreboot/src/mainboard/system76/rpl/variants/bonw15/ |
| D | romstage.c | 12 .ddr_config = { in mainboard_memory_init_params()
|
| /external/coreboot/src/mainboard/system76/rpl/variants/serw13/ |
| D | romstage.c | 12 .ddr_config = { in mainboard_memory_init_params()
|
| /external/coreboot/src/mainboard/system76/rpl/variants/oryp12/ |
| D | romstage.c | 12 .ddr_config = { in mainboard_memory_init_params()
|
| /external/coreboot/src/mainboard/google/brya/variants/gaelin/ |
| D | memory.c | 25 .ddr_config = {
|
| /external/coreboot/src/mainboard/google/brox/variants/greenbayupoc/ |
| D | memory.c | 20 .ddr_config = {
|
| /external/coreboot/src/mainboard/google/brya/variants/baseboard/brask/ |
| D | memory.c | 25 .ddr_config = {
|
| /external/coreboot/src/mainboard/google/brya/variants/kinox/ |
| D | memory.c | 26 .ddr_config = {
|
| /external/coreboot/src/mainboard/intel/adlrvp/ |
| D | memory.c | 26 .ddr_config = {
168 .ddr_config = {
|
| /external/coreboot/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/ |
| D | memory.c | 84 .ddr_config = {
|