Searched refs:ddrconf0 (Results 1 – 3 of 3) sorted by relevance
| /external/coreboot/src/soc/mediatek/mt8183/include/soc/ |
| D | dramc_register.h | 203 uint32_t ddrconf0; member
332 check_member(dramc_ao_regs, ddrconf0, 0x0000);
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| /external/coreboot/src/soc/mediatek/mt8183/ |
| D | dramc_pi_calibration_api.c | 1091 SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 1); in dram_phy_reset()
1100 SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 0); in dram_phy_reset()
1135 SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_DM4TO1MODE, 0); in dramc_rx_dqs_gating_cal_pre()
1327 {&ch[chn].ao.ddrconf0}, in dramc_rx_dqs_gating_cal()
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| D | dramc_init_setting.c | 1239 setbits32(&ch[0].ao.ddrconf0, in dramc_setting()
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