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Searched refs:getCondCode (Results 1 – 25 of 39) sorted by relevance

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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/MSP430/Disassembler/
DMSP430Disassembler.cpp324 static MSP430CC::CondCodes getCondCode(unsigned Cond) { in getCondCode() function
353 MI.addOperand(MCOperand::createImm(getCondCode(Cond))); in getInstructionCJ()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/
DMSP430Disassembler.cpp324 static MSP430CC::CondCodes getCondCode(unsigned Cond) { in getCondCode() function
353 MI.addOperand(MCOperand::createImm(getCondCode(Cond))); in getInstructionCJ()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp751 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT()
761 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT()
841 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
847 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
875 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
883 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
915 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
941 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp890 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT()
900 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT()
980 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
986 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
1014 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1022 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1054 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
1080 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1064 DAG.getCondCode(ISD::SETNE) in LowerFPTOUINT()
1147 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
1153 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
1181 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1189 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1221 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
1247 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp870 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
939 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
961 NewRHS, DAG.getCondCode(CCCode)); in SoftenFloatOp_SETCC()
964 DAG.getCondCode(CCCode)), 0); in SoftenFloatOp_SETCC()
1737 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1836 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
1853 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SETCC()
DLegalizeDAG.cpp1652 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
1665 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
3597 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3727 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3759 Tmp4 = DAG.getCondCode(ISD::SETNE); in ExpandNode()
DLegalizeIntegerTypes.cpp3878 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
3934 DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
3963 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
3982 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
3999 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DSelectionDAG.h746 SDValue getCondCode(ISD::CondCode Cond);
1007 {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)});
1008 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
1028 False, getCondCode(Cond));
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp881 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
934 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
956 DAG.getCondCode(CCCode)), in SoftenFloatOp_SETCC()
1578 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1674 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
1691 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SETCC()
DLegalizeIntegerTypes.cpp2866 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
2920 LHSHi, RHSHi, LowCmp.getValue(1), DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
2951 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
2970 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
2987 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
DLegalizeDAG.cpp1583 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
1634 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
3538 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3652 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3683 Tmp4 = DAG.getCondCode(ISD::SETNE); in ExpandNode()
DTargetLowering.cpp267 NewLHS, NewRHS, DAG.getCondCode(CCCode)); in softenSetCCOperands()
273 NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); in softenSetCCOperands()
/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/
DSelectionDAG.h812 SDValue getCondCode(ISD::CondCode Cond);
1178 {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)});
1179 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
1190 return getNode(ISD::VP_SETCC, DL, VT, LHS, RHS, getCondCode(Cond), Mask,
1209 False, getCondCode(Cond));
/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h625 SDValue getCondCode(ISD::CondCode Cond);
821 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
842 LHS, RHS, True, False, getCondCode(Cond));
/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp940 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
1025 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
1047 NewRHS, DAG.getCondCode(CCCode)); in SoftenFloatOp_SETCC()
1050 DAG.getCondCode(CCCode)), 0); in SoftenFloatOp_SETCC()
1883 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1968 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
DLegalizeIntegerTypes.cpp4954 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
5012 DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
5041 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
5060 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
5077 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
DLegalizeDAG.cpp3639 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3784 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3816 Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE); in ExpandNode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp878 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anon46badc9a0111::ARMOperand
2288 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeNoAL()
2295 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedI()
2302 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedS()
2310 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedU()
2317 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedFP()
2344 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2345 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
2395 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
2400 Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode())))); in addITCondCodeInvOperands()
[all …]
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp2026 {Src, Src, DAG.getCondCode(ISD::SETNE), in lowerFP_TO_INT_SAT()
2128 {Abs, MaxValSplat, DAG.getCondCode(ISD::SETOLT), in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
4614 SDValue SetNE = DAG.getCondCode(ISD::SETNE); in lowerSELECT()
4665 SDValue TargetCC = DAG.getCondCode(CCVal); in lowerSELECT()
4671 TargetCC = DAG.getCondCode(ISD::getSetCCInverse(CCVal, LHS.getValueType())); in lowerSELECT()
4691 SDValue TargetCC = DAG.getCondCode(CCVal); in lowerBRCOND()
4698 DAG.getCondCode(ISD::SETNE), Op.getOperand(2)); in lowerBRCOND()
5051 {Trunc, SplatZero, DAG.getCondCode(ISD::SETNE), in lowerVectorMaskTruncLike()
5679 {VID, SplattedIdx, DAG.getCondCode(ISD::SETEQ), in LowerINTRINSIC_WO_CHAIN()
7198 {Result, SplatZero, DAG.getCondCode(ISD::SETNE), in lowerVPFPIntConvOp()
[all …]
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp954 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anonac9141600111::ARMOperand
2429 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeNoAL()
2436 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedI()
2443 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedS()
2451 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedU()
2458 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedFP()
2485 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2486 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
2538 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
2543 Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode())))); in addITCondCodeInvOperands()
[all …]
/external/mesa3d/src/nouveau/codegen/
Dnv50_ir_from_nir.cpp178 CondCode getCondCode(nir_op);
701 Converter::getCondCode(nir_op op) in getCondCode() function in __anona672d96f0111::Converter
2758 getCondCode(op), in visit()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp354 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anon1337604a0211::AArch64Operand
1279 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands()
1800 OS << "<condcode " << getCondCode() << ">"; in print()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp603 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anonf1d269b80311::ARMOperand
1761 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
1762 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
1788 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
2883 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print()
4797 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); in cvtThumbBranches()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp514 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anon104d952c0111::AArch64Operand
1564 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands()
2030 OS << "<condcode " << getCondCode() << ">"; in print()

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