/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
D | PPCCallingConv.cpp | 42 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() 67 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() 93 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCCallingConv.cpp | 42 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() 67 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() 93 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
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/external/llvm/include/llvm/CodeGen/ |
D | CallingConvLower.h | 332 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() function 360 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg() 401 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
D | CallingConvLower.h | 344 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() function 372 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg() 413 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
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/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/ |
D | CallingConvLower.h | 313 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() function 348 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg() 389 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
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/external/llvm/lib/Target/X86/ |
D | X86CallingConv.h | 88 unsigned FirstFree = State.getFirstUnallocated(RegList); in CC_X86_32_MCUInReg()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMCallingConv.cpp | 203 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() 247 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate()
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/external/llvm/lib/Target/ARM/ |
D | ARMCallingConv.h | 210 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() 251 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate()
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
D | ARMCallingConv.cpp | 201 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() 247 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86CallingConv.cpp | 277 unsigned FirstFree = State.getFirstUnallocated(RegList); in CC_X86_32_MCUInReg()
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D | X86CallLowering.cpp | 169 NumXMMRegs = State.getFirstUnallocated(XMMArgRegs); in assignArg()
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
D | X86CallingConv.cpp | 277 unsigned FirstFree = State.getFirstUnallocated(RegList); in CC_X86_32_MCUInReg()
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D | X86CallLowering.cpp | 79 NumXMMRegs = State.getFirstUnallocated(XMMArgRegs); in assignArg()
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
D | MipsCallLowering.cpp | 410 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in lowerFormalArguments()
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D | MipsISelLowering.cpp | 2912 State.getFirstUnallocated(F32Regs) != ValNo; in CC_MipsO32() 4498 unsigned Idx = State.getFirstUnallocated(ArgRegs); in writeVarArgRegs() 4564 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
D | RISCVISelLowering.cpp | 1496 if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s)) in CC_RISCV() 1498 if (State.getFirstUnallocated(ArgFPR64s) == array_lengthof(ArgFPR64s)) in CC_RISCV() 1522 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); in CC_RISCV() 1957 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsCallLowering.cpp | 502 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in lowerFormalArguments()
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D | MipsISelLowering.cpp | 2902 State.getFirstUnallocated(F32Regs) != ValNo; in CC_MipsO32() 4457 unsigned Idx = State.getFirstUnallocated(ArgRegs); in writeVarArgRegs() 4523 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
D | ARCISelLowering.cpp | 524 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCallArguments()
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARC/ |
D | ARCISelLowering.cpp | 560 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCallArguments()
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/LoongArch/ |
D | LoongArchISelLowering.cpp | 1922 if (State.getFirstUnallocated(ArgFPR32s) == std::size(ArgFPR32s)) in CC_LoongArch() 1945 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); in CC_LoongArch() 2265 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments()
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/external/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 2493 State.getFirstUnallocated(F32Regs) != ValNo; in CC_MipsO32() 3872 unsigned Idx = State.getFirstUnallocated(ArgRegs); in writeVarArgRegs() 3938 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/CSKY/ |
D | CSKYISelLowering.cpp | 368 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments()
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/external/llvm/lib/Target/XCore/ |
D | XCoreISelLowering.cpp | 1361 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCCCArguments()
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/XCore/ |
D | XCoreISelLowering.cpp | 1344 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCCCArguments()
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