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Searched refs:getTargetExtractSubreg (Results 1 – 25 of 55) sorted by relevance

123

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp243 SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32, in tryInlineAsm()
245 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm()
DSparcISelLowering.cpp2705 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, in LowerF64Op()
2707 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, in LowerF64Op()
2855 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, in LowerFNEGorFABS()
2857 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, in LowerFNEGorFABS()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp249 SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32, in tryInlineAsm()
251 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm()
DSparcISelLowering.cpp2887 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, in LowerF64Op()
2889 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, in LowerF64Op()
3036 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, in LowerFNEGorFABS()
3038 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, in LowerFNEGorFABS()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp477 return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, VecTy, S); in buildHvxVectorReg()
547 return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, P); in createHvxPrefixPred()
550 return DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, P); in createHvxPrefixPred()
788 VecV = DAG.getTargetExtractSubreg(SubIdx, dl, VecTy, VecV); in extractHvxSubvectorReg()
893 V0 = DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, SingleTy, VecV); in insertHvxSubvectorReg()
894 V1 = DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, SingleTy, VecV); in insertHvxSubvectorReg()
940 SDValue R0 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, V); in insertHvxSubvectorReg()
941 SDValue R1 = DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, V); in insertHvxSubvectorReg()
1398 return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, ResTy, Pair); in LowerHvxMulh()
1401 return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, ResTy, Pair); in LowerHvxMulh()
DHexagonISelDAGToDAGHVX.cpp1016 Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op); in materialize()
1407 Vec = DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, SingleTy, Vec); in scalarizeShuffle()
1409 Vec = DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, SingleTy, Vec); in scalarizeShuffle()
DHexagonISelLowering.cpp2377 T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1); in extractVector()
2399 ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV); in extractVector()
2444 ValR = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, ValR); in insertVector()
2614 W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W); in LowerCONCAT_VECTORS()
/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp244 SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32, in tryInlineAsm()
246 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/CSKY/
DCSKYISelDAGToDAG.cpp213 CurDAG->getTargetExtractSubreg(CSKY::sub32_0, dl, MVT::i32, RegCopy); in selectInlineAsm()
215 CurDAG->getTargetExtractSubreg(CSKY::sub32_32, dl, MVT::i32, RegCopy); in selectInlineAsm()
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp2277 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); in Select()
2286 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); in Select()
2474 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result); in Select()
2543 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, in Select()
2578 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl, in Select()
2603 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, in Select()
2626 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl, in Select()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/
DHexagonISelLowering.h457 return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, V); in LoHalf()
468 return DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, V); in HiHalf()
DHexagonISelDAGToDAGHVX.cpp1196 Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op); in materialize()
1856 Vec = DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, SingleTy, Vec); in scalarizeShuffle()
1858 Vec = DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, SingleTy, Vec); in scalarizeShuffle()
2556 SDValue Ext = DAG.getTargetExtractSubreg(SubReg, SDLoc(N), ResTy, Inp); in selectExtractSubvector()
DHexagonISelDAGToDAG.cpp525 Value = CurDAG->getTargetExtractSubreg(Hexagon::isub_lo, in SelectIndexedStore()
715 SDValue Ext = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(N), ResTy, Inp); in SelectExtractSubvector()
828 SDValue E = CurDAG->getTargetExtractSubreg(Hexagon::isub_lo, dl, ResTy, in SelectVAlign()
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp590 Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg, in SelectIndexedStore()
1109 SDValue SubregHI = CurDAG->getTargetExtractSubreg(Hexagon::subreg_hireg, dl, in SelectBitOp()
1112 SDValue SubregLO = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg, dl, in SelectBitOp()
DHexagonISelLowering.cpp2456 return DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::v2i16, in LowerBUILD_VECTOR()
2633 N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec); in LowerEXTRACT_VECTOR()
2640 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N); in LowerEXTRACT_VECTOR()
2661 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N); in LowerEXTRACT_VECTOR()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp2245 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2529 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
2838 CurDAG->getTargetExtractSubreg(ARM::qsub_0 + i, Loc, VT, in SelectMVE_VLD()
2944 SDValue SubReg = CurDAG->getTargetExtractSubreg(SubRegs[ResIdx], Loc, in SelectCDE_CXxD()
3074 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg)); in SelectVLDDup()
3131 SDValue NewExt = CurDAG->getTargetExtractSubreg( in tryInsertVectorElt()
3143 SDValue Inp1 = CurDAG->getTargetExtractSubreg( in tryInsertVectorElt()
3145 SDValue Inp2 = CurDAG->getTargetExtractSubreg( in tryInsertVectorElt()
4070 SDValue Lo = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in Select()
4072 SDValue Hi = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in Select()
[all …]
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp1623 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1662 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1745 ReplaceUses(SDValue(N, I), CurDAG->getTargetExtractSubreg( in SelectWhilePair()
1760 ReplaceUses(SDValue(N, i), CurDAG->getTargetExtractSubreg( in SelectCVTIntrinsic()
1791 ReplaceUses(SDValue(N, i), CurDAG->getTargetExtractSubreg( in SelectPredicatedLoad()
1914 return DAG.getTargetExtractSubreg(AArch64::dsub, SDLoc(V128Reg), NarrowTy, in NarrowVector()
1947 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1999 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, in SelectPostLoadLane()
3641 SDValue Lo = CurDAG->getTargetExtractSubreg(AArch64::sube64, DL, MVT::i64, in tryReadRegister()
3643 SDValue Hi = CurDAG->getTargetExtractSubreg(AArch64::subo64, DL, MVT::i64, in tryReadRegister()
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp1149 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1180 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1255 return DAG.getTargetExtractSubreg(AArch64::dsub, SDLoc(V128Reg), NarrowTy, in NarrowVector()
1288 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1340 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, in SelectPostLoadLane()
2657 SDValue Extract = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(Node), VT, in Select()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/
DRISCVISelDAGToDAG.cpp349 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEG()
393 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEGFF()
448 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLXSEG()
1786 SDValue Extract = CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, V); in Select()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1937 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2207 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
2289 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg)); in SelectVLDDup()
4270 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in tryInlineAsm()
4272 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp956 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N); in convertTo()
1180 Node, CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, Op).getNode()); in loadVectorConstant()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp949 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N); in convertTo()
1170 Node, CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, Op).getNode()); in loadVectorConstant()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp2140 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2418 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
2682 CurDAG->getTargetExtractSubreg(ARM::qsub_0 + i, Loc, VT, Data)); in SelectMVE_VLD()
2810 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg)); in SelectVLDDup()
4977 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in tryInlineAsm()
4979 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp1294 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1330 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1409 return DAG.getTargetExtractSubreg(AArch64::dsub, SDLoc(V128Reg), NarrowTy, in NarrowVector()
1442 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1494 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, in SelectPostLoadLane()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp5506 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result); in Select()
5582 CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl, MVT::i8, FNSTSW); in Select()
5711 CurDAG->getTargetExtractSubreg(SubRegIdx, dl, SubRegVT, Shift); in Select()
5796 Reg = CurDAG->getTargetExtractSubreg(SubRegOp, dl, VT, Reg); in Select()
5909 Result = CurDAG->getTargetExtractSubreg(SubIndex, dl, VT, Result); in Select()
5930 Result = CurDAG->getTargetExtractSubreg(SubIndex, dl, VT, Result); in Select()

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