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Searched refs:gfx_cs (Results 1 – 25 of 29) sorted by relevance

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/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_cp_reg_shadowing.c41 sctx->ws->cs_set_mcbp_reg_shadowing_va(&sctx->gfx_cs, in si_init_cp_reg_shadowing()
60 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, &sctx->shadowing.registers->b.b, in si_init_cp_reg_shadowing()
72 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->shadowing.registers, in si_init_cp_reg_shadowing()
75 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->shadowing.csa, in si_init_cp_reg_shadowing()
80 ac_emulate_clear_state(&sctx->screen->info, &sctx->gfx_cs, si_set_context_reg_array); in si_init_cp_reg_shadowing()
98 sctx->ws->cs_setup_preemption(&sctx->gfx_cs, shadowing_preamble->base.pm4, in si_init_cp_reg_shadowing()
Dsi_fence.c75 if (!ctx->ws->cs_is_secure(&ctx->gfx_cs)) { in si_cp_release_mem()
97 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, scratch, in si_cp_release_mem()
126 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, scratch, in si_cp_release_mem()
141 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, buf, RADEON_USAGE_WRITE | RADEON_PRIO_QUERY); in si_cp_release_mem()
173 ws->cs_add_fence_dependency(&sctx->gfx_cs, fence); in si_add_fence_dependency()
178 sctx->ws->cs_add_syncobj_signal(&sctx->gfx_cs, fence); in si_add_syncobj_signal()
254 … radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, fine->buf, RADEON_USAGE_WRITE | RADEON_PRIO_QUERY); in si_fine_fence_set()
255 si_cp_release_mem(ctx, &ctx->gfx_cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, in si_fine_fence_set()
465 if (!radeon_emitted(&sctx->gfx_cs, sctx->initial_gfx_cs_size)) { in si_flush_all_queues()
469 ws->cs_sync_flush(&sctx->gfx_cs); in si_flush_all_queues()
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Dsi_gfx_cs.c78 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_flush_gfx_cs()
156 si_cp_dma_wait_for_idle(ctx, &ctx->gfx_cs); in si_flush_gfx_cs()
224 si_handle_sqtt(ctx, &ctx->gfx_cs); in si_flush_gfx_cs()
267 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->current_saved_cs->trace_buf, in si_begin_gfx_cs_debug()
400 if (secure != sctx->ws->cs_is_secure(&sctx->gfx_cs)) { in si_tmz_preamble()
440 is_secure = ctx->ws->cs_is_secure(&ctx->gfx_cs); in si_begin_new_gfx_cs()
450 ctx->ws->cs_add_buffer(&ctx->gfx_cs, ctx->screen->gds_oa, RADEON_USAGE_READWRITE, 0); in si_begin_new_gfx_cs()
488 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->screen->attribute_pos_prim_ring, in si_begin_new_gfx_cs()
492 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->border_color_buffer, in si_begin_new_gfx_cs()
496 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->shadowing.registers, in si_begin_new_gfx_cs()
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Dsi_cp_dma.c113 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(dst), in si_cp_dma_prepare()
116 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(src), in si_cp_dma_prepare()
218 si_emit_cp_dma(sctx, &sctx->gfx_cs, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags); in si_cp_dma_realign_engine()
273 if (secure != sctx->ws->cs_is_secure(&sctx->gfx_cs)) { in si_cp_dma_copy_buffer()
312 si_emit_cp_dma(sctx, &sctx->gfx_cs, main_dst_offset, main_src_offset, byte_count, dma_flags); in si_cp_dma_copy_buffer()
326 si_emit_cp_dma(sctx, &sctx->gfx_cs, dst_offset, src_offset, skipped_size, dma_flags); in si_cp_dma_copy_buffer()
339 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_cp_write_data()
365 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, dst, RADEON_USAGE_WRITE | RADEON_PRIO_CP_DMA); in si_cp_copy_data()
368 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, src, RADEON_USAGE_READ | RADEON_PRIO_CP_DMA); in si_cp_copy_data()
Dsi_utrace.c22 if (ctx->gfx_cs.current.buf == ctx->last_timestamp_cmd && in si_utrace_record_ts()
23 ctx->gfx_cs.current.cdw == ctx->last_timestamp_cmd_cdw) { in si_utrace_record_ts()
30 ctx->last_timestamp_cmd = ctx->gfx_cs.current.buf; in si_utrace_record_ts()
31 ctx->last_timestamp_cmd_cdw = ctx->gfx_cs.current.cdw; in si_utrace_record_ts()
Dsi_state_msaa.c149 radeon_begin(&sctx->gfx_cs); in si_emit_max_4_sample_locs()
162 radeon_begin(&sctx->gfx_cs); in si_emit_max_4_sample_locs()
173 radeon_begin(&sctx->gfx_cs); in si_emit_max_4_sample_locs()
189 radeon_begin(&sctx->gfx_cs); in si_emit_max_16_sample_locs()
215 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_sample_locations()
Dsi_pm4.c42 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pm4_emit_commands()
52 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pm4_emit_state()
70 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, ((struct si_shader*)state)->bo, in si_pm4_emit_shader()
Dsi_state_streamout.c256 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_flush_vgt_streamout()
291 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_streamout_begin()
355 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, in si_emit_streamout_begin()
376 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_streamout_end()
400 si_cp_copy_data(sctx, &sctx->gfx_cs, COPY_DATA_DST_MEM, in si_emit_streamout_end()
426 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, in si_emit_streamout_end()
447 radeon_begin(&sctx->gfx_cs); in si_emit_streamout_enable()
Dsi_state_viewport.c97 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->small_prim_cull_info_buf, in si_emit_cull_state()
109 radeon_begin(&sctx->gfx_cs); in si_emit_cull_state()
365 radeon_begin(&sctx->gfx_cs); in si_emit_guardband()
379 radeon_begin(&sctx->gfx_cs); in si_emit_guardband()
393 radeon_begin(&sctx->gfx_cs); in si_emit_guardband()
407 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_emit_scissors()
503 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in gfx6_emit_one_viewport()
517 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in gfx6_emit_viewports()
554 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in gfx6_emit_depth_ranges()
593 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in gfx12_emit_viewport_states()
[all …]
Dsi_compute.c431 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_switch_compute_shader()
506 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->compute_scratch_buffer, in si_switch_compute_shader()
517 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->bo, in si_switch_compute_shader()
606 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in setup_scratch_rsrc_user_sgprs()
650 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_setup_user_sgprs_co_v2()
697 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, dispatch_buf, in si_setup_user_sgprs_co_v2()
754 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, input_buffer, in si_upload_compute_input()
766 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_setup_nir_user_data()
775 si_cp_copy_data(sctx, &sctx->gfx_cs, COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i, in si_setup_nir_user_data()
912 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_dispatch_packets()
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Dsi_perfcounter.c45 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_instance()
83 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_select()
109 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_start()
111 si_cp_copy_data(sctx, &sctx->gfx_cs, COPY_DATA_DST_MEM, buffer, va - buffer->gpu_address, in si_pc_emit_start()
127 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_stop()
198 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_read()
257 radeon_begin(&sctx->gfx_cs); in si_inhibit_clockgating()
283 si_pc_emit_shaders(&sctx->gfx_cs, query->shaders); in si_pc_query_resume()
285 si_inhibit_clockgating(sctx, &sctx->gfx_cs, true); in si_pc_query_resume()
339 si_inhibit_clockgating(sctx, &sctx->gfx_cs, false); in si_pc_query_suspend()
Dsi_state_draw.cpp538 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_cp_dma_prefetch_inline()
928 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_rasterizer_prim_state()
992 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_vs_state()
1067 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_ia_multi_vgt_param()
1101 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_draw_registers()
1179 radeon_begin(&sctx->gfx_cs); in gfx11_emit_buffered_sh_regs_inline()
1191 radeon_begin(&sctx->gfx_cs); in gfx11_emit_buffered_sh_regs_inline()
1223 radeon_begin(&sctx->gfx_cs); in si_emit_buffered_compute_sh_regs()
1246 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_draw_packets()
1249 si_sqtt_write_event_marker(sctx, &sctx->gfx_cs, sctx->sqtt_next_event, in si_emit_draw_packets()
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Dsi_pipe.c208 sscreen->ws->cs_set_pstate(&sctx->gfx_cs, RADEON_CTX_PSTATE_NONE); in si_destroy_context()
314 if (sctx->gfx_cs.priv) in si_destroy_context()
315 sctx->ws->cs_destroy(&sctx->gfx_cs); in si_destroy_context()
437 si_write_user_event(sctx, &sctx->gfx_cs, UserEventTrigger, string, len); in si_emit_string_marker()
576 if (!ws->cs_create(&sctx->gfx_cs, sctx->ctx, sctx->has_graphics ? AMD_IP_GFX : AMD_IP_COMPUTE, in si_create_context()
579 sctx->gfx_cs.priv = NULL; in si_create_context()
582 assert(sctx->gfx_cs.priv); in si_create_context()
796 assert(sctx->gfx_cs.current.cdw == 0); in si_create_context()
815 assert(sctx->gfx_cs.current.cdw == sctx->initial_gfx_cs_size); in si_create_context()
839 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, sctx->null_const_buf.buffer, 0, in si_create_context()
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Dsi_state.c41 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_cb_render_state()
847 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_blend_color()
881 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_clip_state()
923 radeon_begin(&sctx->gfx_cs); in si_emit_clip_regs()
932 radeon_begin(&sctx->gfx_cs); in si_emit_clip_regs()
941 radeon_begin(&sctx->gfx_cs); in si_emit_clip_regs()
1152 radeon_begin(&sctx->gfx_cs); in si_pm4_emit_rasterizer()
1202 radeon_begin(&sctx->gfx_cs); in si_pm4_emit_rasterizer()
1247 radeon_begin(&sctx->gfx_cs); in si_pm4_emit_rasterizer()
1408 radeon_begin(&sctx->gfx_cs); in si_emit_stencil_ref()
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Dsi_descriptors.c150 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, desc->buffer, in si_upload_descriptors()
168 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, desc->buffer, in si_add_descriptors_to_bo_list()
215 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, usage | priority); in si_sampler_view_add_buffer()
961 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, in si_update_ps_colorbuf0_slot()
1084 sctx, &sctx->gfx_cs, si_resource(buffers->buffers[i]), in si_buffer_resources_begin_new_cs()
1191 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(buffer), in si_set_constant_buffer()
1345 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, buf, in si_set_shader_buffer()
1516 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(buffer), in si_set_ring_buffer()
1628 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(buffer), in si_reset_buffer_resources()
1673 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, buf, in si_rebind_buffer()
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Dsi_debug.c402 si_parse_current_ib(f, &sctx->gfx_cs, 0, sctx->gfx_cs.prev_dw + sctx->gfx_cs.current.cdw, in si_print_current_ib()
438 si_parse_current_ib(f, &ctx->gfx_cs, chunk->gfx_begin, chunk->gfx_end, &last_trace_id, in si_log_chunk_type_cs_print()
461 unsigned gfx_cur = ctx->gfx_cs.prev_dw + ctx->gfx_cs.current.cdw; in si_log_cs()
1123 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_gather_context_rolls()
Dsi_buffer.c18 return sctx->ws->cs_is_buffer_referenced(&sctx->gfx_cs, buf, usage); in si_cs_is_buffer_referenced()
24 return sctx->ws->buffer_map(sctx->ws, resource->buf, &sctx->gfx_cs, usage); in si_buffer_map()
745 if (radeon_emitted(&ctx->gfx_cs, ctx->initial_gfx_cs_size) && in si_resource_commit()
746 ctx->ws->cs_is_buffer_referenced(&ctx->gfx_cs, res->buf, RADEON_USAGE_READWRITE)) { in si_resource_commit()
749 ctx->ws->cs_sync_flush(&ctx->gfx_cs); in si_resource_commit()
Dsi_state_shaders.cpp778 radeon_begin(&sctx->gfx_cs); in si_emit_shader_es()
953 radeon_begin(&sctx->gfx_cs); in si_emit_shader_gs()
1004 radeon_begin_again(&sctx->gfx_cs); in si_emit_shader_gs()
1208 radeon_begin(&sctx->gfx_cs); in gfx10_emit_shader_ngg()
1238 radeon_begin_again(&sctx->gfx_cs); in gfx10_emit_shader_ngg()
1267 radeon_begin(&sctx->gfx_cs); in gfx11_dgpu_emit_shader_ngg()
1331 radeon_begin(&sctx->gfx_cs); in gfx12_emit_shader_ngg()
1781 radeon_begin(&sctx->gfx_cs); in si_emit_shader_vs()
1824 radeon_begin_again(&sctx->gfx_cs); in si_emit_shader_vs()
2006 radeon_begin(&sctx->gfx_cs); in gfx6_emit_shader_ps()
[all …]
Dsi_state_binning.c391 radeon_begin(&sctx->gfx_cs); in si_emit_dpbb_disable()
514 radeon_begin(&sctx->gfx_cs); in si_emit_dpbb_state()
Dsi_barrier.c254 si_sqtt_describe_barrier_start(ctx, &ctx->gfx_cs); in gfx10_emit_barrier()
260 si_sqtt_describe_barrier_end(ctx, &ctx->gfx_cs, flags); in gfx10_emit_barrier()
493 sctx->emit_barrier(sctx, &sctx->gfx_cs); in si_emit_barrier_as_atom()
Dgfx11_query.c162 si_cp_release_mem(sctx, &sctx->gfx_cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, in gfx11_sh_query_end()
393 si_cp_wait_mem(sctx, &sctx->gfx_cs, va, 0x00000001, 0x00000001, 0); in gfx11_sh_query_get_result_resource()
Dsi_query.c791 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_query_hw_do_emit_start()
871 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, query->buffer.buf, in si_query_hw_do_emit_start()
931 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_query_hw_do_emit_stop()
1002 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, query->buffer.buf, in si_query_hw_do_emit_stop()
1042 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in emit_set_predicate()
1058 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, buf, RADEON_USAGE_READ | RADEON_PRIO_QUERY); in emit_set_predicate()
1646 si_cp_wait_mem(sctx, &sctx->gfx_cs, va, 0x80000000, 0x80000000, WAIT_REG_MEM_EQUAL); in si_query_hw_get_result_resource()
Dsi_test_dma_perf.c120 sscreen->ws->cs_set_pstate(&sctx->gfx_cs, RADEON_CTX_PSTATE_PEAK); in si_test_dma_perf()
246 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, dst, dst_offset, size, in si_test_dma_perf()
Dsi_pipe.h938 struct radeon_cmdbuf gfx_cs; /* compute IB if graphics is disabled */ member
2036 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_need_gfx_cs_space()
2235 sctx->emit_barrier(sctx, &sctx->gfx_cs); in si_emit_barrier_direct()
Dsi_test_blit_perf.c211 sscreen->ws->cs_set_pstate(&sctx->gfx_cs, RADEON_CTX_PSTATE_PEAK); in si_test_blit_perf()

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