1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_MT8183_MCUCFG_H 4 #define SOC_MEDIATEK_MT8183_MCUCFG_H 5 6 #include <soc/addressmap.h> 7 #include <types.h> 8 9 struct mt8183_mcucfg_regs { 10 u32 mp0_ca7l_cache_config; 11 u32 mp0_cpu0_mem_delsel0; 12 u32 mp0_cpu0_mem_delsel1; 13 u32 reserved1[6]; 14 u32 mp0_cache_mem_delsel0; 15 u32 mp0_cache_mem_delsel1; 16 u32 mp0_axi_config; 17 u32 mp0_misc_config0; 18 u32 reserved2[1]; 19 u32 mp0_misc_config2; 20 u32 mp0_misc_config3; 21 u32 mp0_misc_config4; 22 u32 mp0_misc_config5; 23 u32 mp0_misc_config6; 24 u32 mp0_misc_config7; 25 u32 mp0_misc_config8; 26 u32 mp0_misc_config9; 27 u32 mp0_ca7l_cfg_dis; 28 u32 mp0_ca7l_clken_ctrl; 29 u32 mp0_ca7l_rst_ctrl; 30 u32 mp0_ca7l_misc_config; 31 u32 mp0_ca7l_dbg_pwr_ctrl; 32 u32 mp0_rw_rsvd0; 33 u32 mp0_rw_rsvd1; 34 u32 mp0_ro_rsvd; 35 u32 reserved3[1]; 36 u32 mp0_l2_cache_parity1_rdata; 37 u32 mp0_l2_cache_parity2_rdata; 38 u32 reserved4[1]; 39 u32 mp0_rgu_dcm_config; 40 u32 mp0_ca53_specific_ctrl; 41 u32 mp0_esr_case; 42 u32 mp0_esr_mask; 43 u32 mp0_esr_trig_en; 44 u32 reserved5[1]; 45 u32 mp0_ses_cg_en; 46 u32 reserved6[216]; 47 u32 mp_dbg_ctrl; 48 u32 reserved7[1]; 49 u32 mp0_ca7l_ir_mon; 50 u32 reserved8[32]; 51 u32 mp_dfd_ctrl; 52 u32 dfd_cnt_l; 53 u32 dfd_cnt_h; 54 u32 misccfg_ro_rsvd; 55 u32 reserved9[1]; 56 u32 dvm_dbg_monitor_gpu; 57 u32 dvm_dbg_monitor_psys; 58 u32 dvm_dbg_monitor_mp1; 59 u32 dvm_dbg_monitor_mp0; 60 u32 dvm_dbg_monitor_mp2; 61 u32 reserved10[2]; 62 u32 dvm_op_arid_mp0; 63 u32 dvm_op_arid_mp1; 64 u32 dvm_op_arid_mp2; 65 u32 reserved11[5]; 66 u32 cci_s6_if_debug; 67 u32 reserved12[7]; 68 u32 mp1_rst_status; 69 u32 mp1_dbg_ctrl; 70 u32 mp1_dbg_flag; 71 u32 mp1_ca7l_ir_mon; 72 u32 reserved13[32]; 73 u32 mcusys_dbg_mon_sel_a; 74 u32 mcusys_dbg_mon; 75 u32 misccfg_sec_vio_status0; 76 u32 misccfg_sec_vio_status1; 77 u32 cci_top_if_debug; 78 u32 cci_m0_if_debug; 79 u32 cci_m1_if_debug; 80 u32 cci_m2_if_debug; 81 u32 cci_s1_if_debug; 82 u32 cci_s2_if_debug; 83 u32 cci_s3_if_debug; 84 u32 cci_s4_if_debug; 85 u32 cci_m0_tra_debug; 86 u32 cci_m1_tra_debug; 87 u32 cci_m2_tra_debug; 88 u32 cci_s1_tra_debug; 89 u32 cci_s2_tra_debug; 90 u32 cci_s3_tra_debug; 91 u32 cci_s4_tra_debug; 92 u32 cci_tra_dbg_cfg; 93 u32 cci_s5_if_debug; 94 u32 cci_s5_tra_debug; 95 u32 gic500_int_mask; 96 u32 core_rst_en_latch; 97 u32 reserved14[3]; 98 u32 dbg_core_ret; 99 u32 mcusys_config_a; 100 u32 mcusys_config1_a; 101 u32 mcusys_gic_peribase_a; 102 u32 mcusys_pinmux; 103 u32 sec_range0_start; 104 u32 sec_range0_end; 105 u32 sec_range_enable; 106 u32 l2c_mm_base; 107 u32 reserved15[8]; 108 u32 aclken_div; 109 u32 pclken_div; 110 u32 l2c_sram_ctrl; 111 u32 armpll_jit_ctrl; 112 u32 cci_addrmap; 113 u32 cci_config; 114 u32 cci_periphbase; 115 u32 cci_nevntcntovfl; 116 u32 cci_status; 117 u32 cci_acel_s1_ctrl; 118 u32 mcusys_bus_fabric_dcm_ctrl; 119 u32 mcu_misc_dcm_ctrl; 120 u32 xgpt_ctl; 121 u32 xgpt_idx; 122 u32 reserved16[3]; 123 u32 mcusys_rw_rsvd0; 124 u32 mcusys_rw_rsvd1; 125 u32 reserved17[13]; 126 u32 gic500_delsel_ctl; 127 u32 etb_delsel_ctl; 128 u32 etb_rst_ctl; 129 u32 reserved18[13]; 130 u32 mp_gen_timer_reset_mask_secur_en; 131 u32 mp_gen_timer_reset_mask_0; 132 u32 mp_gen_timer_reset_mask_1; 133 u32 mp_gen_timer_reset_mask_2; 134 u32 mp_gen_timer_reset_mask_3; 135 u32 mp_gen_timer_reset_mask_4; 136 u32 mp_gen_timer_reset_mask_5; 137 u32 mp_gen_timer_reset_mask_6; 138 u32 mp_gen_timer_reset_mask_7; 139 u32 reserved19[7]; 140 u32 mp_cci_adb400_dcm_config; 141 u32 mp_sync_dcm_config; 142 u32 reserved20[1]; 143 u32 mp_sync_dcm_cluster_config; 144 u32 sw_udi; 145 u32 reserved21[1]; 146 u32 gic_sync_dcm; 147 u32 big_dbg_pwr_ctrl; 148 u32 gic_cpu_periphbase; 149 u32 axi_cpu_config; 150 u32 reserved22[2]; 151 u32 mcsib_sys_ctrl1; 152 u32 mcsib_sys_ctrl2; 153 u32 mcsib_sys_ctrl3; 154 u32 mcsib_sys_ctrl4; 155 u32 mcsib_dbg_ctrl1; 156 u32 pwrmcu_apb2to1; 157 u32 reserved23[1]; 158 u32 mp1_spmc; 159 u32 reserved24[1]; 160 u32 mp1_spmc_sram_ctl; 161 u32 reserved25[1]; 162 u32 mp1_sw_rst_wait_cycle; 163 u32 mp0_pll_divider_cfg; 164 u32 reserved26[1]; 165 u32 mp2_pll_divider_cfg; 166 u32 reserved27[5]; 167 u32 bus_pll_divider_cfg; 168 u32 reserved28[7]; 169 u32 clusterid_aff1; 170 u32 clusterid_aff2; 171 u32 hack_ice_rom_table_access; 172 u32 mp_top_mem_delay_cfg; 173 u32 l2c_cfg_mp0; 174 u32 reserved29[1]; 175 u32 l2c_cfg_mp2; 176 u32 reserved30[1]; 177 u32 cci_bw_pmu_ctl; 178 u32 cci_bw_pmu_cnt0to1_sel; 179 u32 cci_bw_pmu_cnt2to3_sel; 180 u32 cci_bw_pmu_cnt4to5_sel; 181 u32 cci_bw_pmu_cnt6to7_sel; 182 u32 cci_bw_pmu_cnt0to3_mask; 183 u32 cci_bw_pmu_cnt4to7_mask; 184 u32 cci_bw_pmu_ref_cnt; 185 u32 cci_bw_pmu_acc_cnt0; 186 u32 cci_bw_pmu_acc_cnt1; 187 u32 cci_bw_pmu_acc_cnt2; 188 u32 cci_bw_pmu_acc_cnt3; 189 u32 cci_bw_pmu_acc_cnt4; 190 u32 cci_bw_pmu_acc_cnt5; 191 u32 cci_bw_pmu_acc_cnt6; 192 u32 cci_bw_pmu_acc_cnt7; 193 u32 reserved31[8]; 194 u32 cci_bw_pmu_id_ext_cnt0to3; 195 u32 cci_bw_pmu_id_ext_cnt4to7; 196 u32 cci_bw_pmu_mask_ext_cnt0to3; 197 u32 cci_bw_pmu_mask_ext_cnt4to7; 198 u32 reserved32[16]; 199 u32 etb_acc_ctl; 200 u32 etb_ck_ctl; 201 u32 reserved33[4]; 202 u32 mbista_mp1_ocp_con; 203 u32 reserved34[1]; 204 u32 mbista_gic_con; 205 u32 mbista_gic_result; 206 u32 mbista_mcsib_sf1_con; 207 u32 mbista_mcsib_sf1_result; 208 u32 mbista_mcsib_sf2_con; 209 u32 mbista_mcsib_sf2_result; 210 u32 reserved35[2]; 211 u32 mbista_rstb; 212 u32 mbista_all_result; 213 u32 reserved36[2]; 214 u32 mp0_hang_monitor_ctrl0; 215 u32 mp0_hang_monitor_ctrl1; 216 u32 reserved37[2]; 217 u32 mp1_hang_monitor_ctrl0; 218 u32 mp1_hang_monitor_ctrl1; 219 u32 reserved38[2]; 220 u32 mp2_hang_monitor_ctrl0; 221 u32 mp2_hang_monitor_ctrl1; 222 u32 reserved39[6]; 223 u32 gpu_hang_monitor_ctrl0; 224 u32 gpu_hang_monitor_ctrl1; 225 u32 reserved40[2]; 226 u32 psys_hang_monitor_ctrl0; 227 u32 psys_hang_monitor_ctrl1; 228 u32 reserved41[42]; 229 u32 sec_pol_ctl_en0; 230 u32 sec_pol_ctl_en1; 231 u32 sec_pol_ctl_en2; 232 u32 sec_pol_ctl_en3; 233 u32 sec_pol_ctl_en4; 234 u32 sec_pol_ctl_en5; 235 u32 sec_pol_ctl_en6; 236 u32 sec_pol_ctl_en7; 237 u32 sec_pol_ctl_en8; 238 u32 sec_pol_ctl_en9; 239 u32 sec_pol_ctl_en10; 240 u32 sec_pol_ctl_en11; 241 u32 sec_pol_ctl_en12; 242 u32 sec_pol_ctl_en13; 243 u32 sec_pol_ctl_en14; 244 u32 sec_pol_ctl_en15; 245 u32 sec_pol_ctl_en16; 246 u32 sec_pol_ctl_en17; 247 u32 sec_pol_ctl_en18; 248 u32 sec_pol_ctl_en19; 249 u32 reserved42[12]; 250 u32 int_pol_ctl0; 251 u32 int_pol_ctl1; 252 u32 int_pol_ctl2; 253 u32 int_pol_ctl3; 254 u32 int_pol_ctl4; 255 u32 int_pol_ctl5; 256 u32 int_pol_ctl6; 257 u32 int_pol_ctl7; 258 u32 int_pol_ctl8; 259 u32 int_pol_ctl9; 260 u32 int_pol_ctl10; 261 u32 int_pol_ctl11; 262 u32 int_pol_ctl12; 263 u32 int_pol_ctl13; 264 u32 int_pol_ctl14; 265 u32 int_pol_ctl15; 266 u32 int_pol_ctl16; 267 u32 int_pol_ctl17; 268 u32 int_pol_ctl18; 269 u32 int_pol_ctl19; 270 u32 reserved43[12]; 271 u32 dfd_internal_ctl; 272 u32 dfd_internal_counter; 273 u32 dfd_internal_pwr_on; 274 u32 dfd_internal_chain_legth_0; 275 u32 dfd_internal_shift_clk_ratio; 276 u32 dfd_internal_counter_return; 277 u32 dfd_internal_sram_access; 278 u32 dfd_internal_chain_length_1; 279 u32 dfd_internal_chain_length_2; 280 u32 dfd_internal_chain_length_3; 281 u32 dfd_internal_test_so_0; 282 u32 dfd_internal_test_so_1; 283 u32 dfd_internal_num_of_test_so_gp; 284 u32 dfd_internal_test_so_over_64; 285 u32 dfd_internal_mask_out; 286 u32 dfd_internal_sw_ns_trigger; 287 u32 dfd_internal_mcsib; 288 u32 dfd_internal_mcsib_sel_status; 289 u32 dfd_internal_sram_base_addr; 290 u32 dfd_internal_sram_delsel; 291 u32 mcsib_iccs_ctrl1; 292 u32 reserved44[1]; 293 u32 mcu_all_pwr_on_ctrl; 294 u32 emi_wfifo; 295 u32 mcsia_dcm_en; 296 u32 reserved45[294]; 297 u32 mcu_apb_base; 298 u32 reserved46[384]; 299 u32 mp0_cpu_avg_stall_ratio; 300 u32 mp0_cpu0_avg_stall_ratio_ctrl; 301 u32 mp0_cpu1_avg_stall_ratio_ctrl; 302 u32 mp0_cpu2_avg_stall_ratio_ctrl; 303 u32 mp0_cpu3_avg_stall_ratio_ctrl; 304 u32 mp0_avg_stall_ratio_status; 305 u32 mp0_cpu0_stall_counter; 306 u32 mp0_cpu1_stall_counter; 307 u32 mp0_cpu2_stall_counter; 308 u32 mp0_cpu3_stall_counter; 309 u32 mp0_cpu0_non_wfi_counter; 310 u32 mp0_cpu1_non_wfi_counter; 311 u32 mp0_cpu2_non_wfi_counter; 312 u32 mp0_cpu3_non_wfi_counter; 313 u32 reserved47[370]; 314 u32 cpusys0_sparkvretcntrl; 315 u32 cpusys0_sparken; 316 u32 cpusys0_amuxsel; 317 u32 cpusys0_cg_dis; 318 u32 cpusys0_cpu0_counter; 319 u32 cpusys0_cpu1_counter; 320 u32 cpusys0_cpu2_counter; 321 u32 cpusys0_cpu3_counter; 322 u32 cpusys0_spark_debug_overwrite; 323 u32 reserved48[3]; 324 u32 cpusys0_cpu0_spmc_ctl; 325 u32 cpusys0_cpu1_spmc_ctl; 326 u32 cpusys0_cpu2_spmc_ctl; 327 u32 cpusys0_cpu3_spmc_ctl; 328 u32 sesv3_rg_toggle; 329 u32 reserved49[7]; 330 u32 mp0_sync_dcm_cgavg_ctrl; 331 u32 mp0_sync_dcm_cgavg_fact; 332 u32 mp0_sync_dcm_cgavg_rfact; 333 u32 mp0_sync_dcm_cgavg; 334 }; 335 336 check_member(mt8183_mcucfg_regs, mp0_cache_mem_delsel0, 0x0024); 337 check_member(mt8183_mcucfg_regs, mp_dbg_ctrl, 0x0404); 338 check_member(mt8183_mcucfg_regs, mp_dfd_ctrl, 0x0490); 339 check_member(mt8183_mcucfg_regs, dvm_op_arid_mp0, 0x04c0); 340 check_member(mt8183_mcucfg_regs, cci_s6_if_debug, 0x04e0); 341 check_member(mt8183_mcucfg_regs, mp1_rst_status, 0x0500); 342 check_member(mt8183_mcucfg_regs, mcusys_dbg_mon_sel_a, 0x0590); 343 check_member(mt8183_mcucfg_regs, dbg_core_ret, 0x05fc); 344 check_member(mt8183_mcucfg_regs, aclken_div, 0x0640); 345 check_member(mt8183_mcucfg_regs, mcusys_rw_rsvd0, 0x0684); 346 check_member(mt8183_mcucfg_regs, gic500_delsel_ctl, 0x06c0); 347 check_member(mt8183_mcucfg_regs, mp_gen_timer_reset_mask_secur_en, 0x0700); 348 check_member(mt8183_mcucfg_regs, mp_cci_adb400_dcm_config, 0x0740); 349 check_member(mt8183_mcucfg_regs, mcsib_sys_ctrl1, 0x0770); 350 check_member(mt8183_mcucfg_regs, bus_pll_divider_cfg, 0x07c0); 351 check_member(mt8183_mcucfg_regs, clusterid_aff1, 0x07e0); 352 check_member(mt8183_mcucfg_regs, cci_bw_pmu_id_ext_cnt0to3, 0x0860); 353 check_member(mt8183_mcucfg_regs, etb_acc_ctl, 0x08b0); 354 check_member(mt8183_mcucfg_regs, mbista_mp1_ocp_con, 0x08c8); 355 check_member(mt8183_mcucfg_regs, mbista_rstb, 0x08f0); 356 check_member(mt8183_mcucfg_regs, mp0_hang_monitor_ctrl0, 0x0900); 357 check_member(mt8183_mcucfg_regs, mp1_hang_monitor_ctrl0, 0x0910); 358 check_member(mt8183_mcucfg_regs, mp2_hang_monitor_ctrl0, 0x0920); 359 check_member(mt8183_mcucfg_regs, gpu_hang_monitor_ctrl0, 0x0940); 360 check_member(mt8183_mcucfg_regs, psys_hang_monitor_ctrl0, 0x0950); 361 check_member(mt8183_mcucfg_regs, sec_pol_ctl_en0, 0x0a00); 362 check_member(mt8183_mcucfg_regs, int_pol_ctl0, 0x0a80); 363 check_member(mt8183_mcucfg_regs, dfd_internal_ctl, 0x0b00); 364 check_member(mt8183_mcucfg_regs, mcu_apb_base, 0x0ffc); 365 check_member(mt8183_mcucfg_regs, mp0_cpu_avg_stall_ratio, 0x1600); 366 check_member(mt8183_mcucfg_regs, cpusys0_sparkvretcntrl, 0x1c00); 367 check_member(mt8183_mcucfg_regs, cpusys0_cpu0_spmc_ctl, 0x1c30); 368 check_member(mt8183_mcucfg_regs, mp0_sync_dcm_cgavg_ctrl, 0x1c60); 369 check_member(mt8183_mcucfg_regs, mp0_sync_dcm_cgavg, 0x1c6c); 370 371 static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE; 372 373 #endif /* SOC_MEDIATEK_MT8183_MCUCFG_H */ 374