Searched refs:meta_alignment_log2 (Results 1 – 6 of 6) sorted by relevance
321 surf->meta_alignment_log2 = util_logbase2(base_align); in si_compute_htile()422 surf_ws->meta_offset = align64(surf_ws->total_size, 1 << surf_ws->meta_alignment_log2); in radeon_winsys_surface_init()
937 …surf->meta_alignment_log2 = MAX2(surf->meta_alignment_log2, util_logbase2(AddrDccOut->dccRamBaseAl… in gfx6_compute_level()1021 surf->meta_alignment_log2 = util_logbase2(AddrHtileOut->baseAlign); in gfx6_compute_level()1423 surf->meta_alignment_log2 = 0; in gfx6_compute_surface()1572 surf->meta_size = align64(surf->surf_size >> 8, (1ull << surf->meta_alignment_log2) * 4); in gfx6_compute_surface()1586 surf->meta_size = align(surf->meta_size, 1 << surf->meta_alignment_log2); in gfx6_compute_surface()2074 surf->meta_alignment_log2 = util_logbase2(hout.baseAlign); in gfx9_compute_miptree()2186 surf->meta_alignment_log2 = util_logbase2(dout.dccRamBaseAlign); in gfx9_compute_miptree()2234 surf->u.gfx9.color.display_dcc_alignment_log2 = surf->meta_alignment_log2; in gfx9_compute_miptree()3437 surf->meta_offset = align64(surf->total_size, 1ull << surf->meta_alignment_log2); in ac_compute_surface()3439 surf->alignment_log2 = MAX2(surf->alignment_log2, surf->meta_alignment_log2); in ac_compute_surface()[all …]
372 uint8_t meta_alignment_log2; /* DCC or HTILE */ member
603 dcc_tile_swizzle &= (1 << surf->meta_alignment_log2) - 1; in ac_set_mutable_tex_desc_fields()1414 dcc_tile_swizzle &= ((1 << surf->meta_alignment_log2) - 1) >> 8; in ac_set_mutable_cb_surface_fields()
783 rtex->surface.meta_alignment_log2 = util_logbase2(base_align); in r600_texture_get_htile_size()797 rtex->htile_offset = align(rtex->size, 1 << rtex->surface.meta_alignment_log2); in r600_texture_allocate_htile()841 1 << rtex->surface.meta_alignment_log2); in r600_print_texture_info()
585 token.image.metadata_alignment_log2 = image->planes[0].surface.meta_alignment_log2; in radv_rmv_log_image_create()