| /external/mesa3d/src/amd/vulkan/ |
| D | radv_query.c | 71 nir_push_if(b, nir_test_mask(b, flags, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)); in radv_store_availability()
73 nir_push_if(b, nir_test_mask(b, flags, VK_QUERY_RESULT_64_BIT)); in radv_store_availability()
202 nir_def *query_result_wait = nir_test_mask(&b, flags, VK_QUERY_RESULT_WAIT_BIT); in build_occlusion_query_shader()
263 nir_def *result_is_64bit = nir_test_mask(&b, flags, VK_QUERY_RESULT_64_BIT); in build_occlusion_query_shader()
265 …nir_push_if(&b, nir_ior(&b, nir_test_mask(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT), nir_load_var(&b… in build_occlusion_query_shader()
494 …nir_push_if(&b, nir_test_mask(&b, stats_mask, VK_QUERY_PIPELINE_STATISTIC_TASK_SHADER_INVOCATIONS_… in build_pipeline_statistics_query_shader()
513 nir_def *result_is_64bit = nir_test_mask(&b, flags, VK_QUERY_RESULT_64_BIT); in build_pipeline_statistics_query_shader()
524 nir_push_if(&b, nir_test_mask(&b, stats_mask, BITFIELD64_BIT(i))); in build_pipeline_statistics_query_shader()
569 nir_push_if(&b, nir_test_mask(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT)); in build_pipeline_statistics_query_shader()
886 nir_def *result_is_available = nir_test_mask(&b, nir_iand(&b, avails[0], avails[1]), 0x80000000); in build_tfb_query_shader()
[all …]
|
| D | radv_dgc.c | 1139 nir_def *has_drawid = nir_test_mask(b, vtx_base_sgpr, DGC_USES_DRAWID); in dgc_emit_userdata_vertex()
1140 nir_def *has_baseinstance = nir_test_mask(b, vtx_base_sgpr, DGC_USES_BASEINSTANCE); in dgc_emit_userdata_vertex()
1212 nir_def *has_drawid = nir_test_mask(b, vtx_base_sgpr, DGC_USES_DRAWID); in dgc_emit_pkt3_draw_indirect()
1213 nir_def *has_baseinstance = nir_test_mask(b, vtx_base_sgpr, DGC_USES_BASEINSTANCE); in dgc_emit_pkt3_draw_indirect()
1344 nir_def *has_drawid = nir_test_mask(b, vtx_base_sgpr, DGC_USES_DRAWID); in dgc_emit_draw_with_count()
1345 nir_def *has_baseinstance = nir_test_mask(b, vtx_base_sgpr, DGC_USES_BASEINSTANCE); in dgc_emit_draw_with_count()
1652 nir_push_if(b, nir_test_mask(b, push_constant_stages, mesa_to_vk_shader_stage(s))); in dgc_emit_push_constant()
2007 nir_def *has_grid_size = nir_test_mask(b, vtx_base_sgpr, DGC_USES_GRID_SIZE); in dgc_emit_userdata_mesh()
2008 nir_def *has_drawid = nir_test_mask(b, vtx_base_sgpr, DGC_USES_DRAWID); in dgc_emit_userdata_mesh()
2049 nir_def *has_grid_size = nir_test_mask(b, vtx_base_sgpr, DGC_USES_GRID_SIZE); in dgc_emit_dispatch_taskmesh_gfx()
[all …]
|
| /external/mesa3d/src/gallium/frontends/lavapipe/ |
| D | lvp_nir_ray_tracing.c | 301 nir_def *switch_ccw = nir_test_mask(b, nir_load_deref(b, args->vars.sbt_offset_and_flags), in lvp_build_triangle_case()
312 nir_test_mask(b, nir_load_deref(b, args->vars.sbt_offset_and_flags), in lvp_build_triangle_case()
393 .force_opaque = nir_test_mask(b, args->flags, SpvRayFlagsOpaqueKHRMask), in lvp_build_ray_traversal()
394 .force_not_opaque = nir_test_mask(b, args->flags, SpvRayFlagsNoOpaqueKHRMask), in lvp_build_ray_traversal()
396 nir_test_mask(b, args->flags, SpvRayFlagsTerminateOnFirstHitKHRMask), in lvp_build_ray_traversal()
|
| D | lvp_nir_lower_ray_queries.c | 273 nir_test_mask(b, rq_load_var(b, index, vars->flags), SpvRayFlagsTerminateOnFirstHitKHRMask); in insert_terminate_on_first_hit()
|
| D | lvp_ray_tracing_pipeline.c | 796 nir_def *skip_chit = nir_test_mask(b, flags, SpvRayFlagsSkipClosestHitShaderKHRMask); in lvp_trace_ray()
|
| /external/mesa3d/src/amd/vulkan/nir/ |
| D | radv_nir_rt_common.c | 393 …nir_test_mask(b, nir_load_deref(b, args->vars.sbt_offset_and_flags), RADV_INSTANCE_TRIANGLE_FLIP_F… in insert_traversal_triangle_case()
402 … nir_test_mask(b, nir_load_deref(b, args->vars.sbt_offset_and_flags), in insert_traversal_triangle_case()
477 result = nir_test_mask(b, args->flags, flag); in radv_test_flag()
585 nir_push_if(b, nir_test_mask(b, bvh_node, BITFIELD64_BIT(ffs(radv_bvh_node_box16) - 1))); in radv_build_ray_traversal()
587 … nir_push_if(b, nir_test_mask(b, bvh_node, BITFIELD64_BIT(ffs(radv_bvh_node_instance) - 1))); in radv_build_ray_traversal()
589 nir_push_if(b, nir_test_mask(b, bvh_node, BITFIELD64_BIT(ffs(radv_bvh_node_aabb) - 1))); in radv_build_ray_traversal()
|
| D | radv_nir_lower_abi.c | 44 return nir_test_mask(b, settings, mask); in nggc_bool_setting()
58 return nir_test_mask(b, settings, mask); in shader_query_bool_setting()
|
| D | radv_nir_rt_shader.c | 642 …nir_test_mask(b, nir_load_var(b, vars->cull_mask_and_flags), SpvRayFlagsTerminateOnFirstHitKHRMask… in radv_lower_rt_instruction()
674 …nir_test_mask(b, nir_load_var(b, vars->cull_mask_and_flags), SpvRayFlagsSkipClosestHitShaderKHRMas… in radv_lower_rt_instruction()
1643 …nir_test_mask(b, nir_load_var(b, vars->cull_mask_and_flags), SpvRayFlagsSkipClosestHitShaderKHRMas… in radv_build_traversal()
|
| D | radv_nir_lower_ray_queries.c | 291 … nir_test_mask(b, rq_load_var(b, index, vars->flags), SpvRayFlagsTerminateOnFirstHitKHRMask); in insert_terminate_on_first_hit()
|
| /external/mesa3d/src/compiler/nir/ |
| D | nir_lower_ubo_vec4.c | 145 result = nir_bcsel(b, nir_test_mask(b, byte_offset, 8), in nir_lower_ubo_vec4_lower()
|
| D | nir_lower_texcoord_replace.c | 117 nir_def *cond = nir_test_mask(&b, mask, coord_replace); in nir_lower_texcoord_replace_impl()
|
| D | nir_builder.c | 642 nir_def *c1cmp = nir_test_mask(b, vertex_id, 1); in nir_gen_rect_vertices()
|
| D | nir_lower_subgroups.c | 1197 return nir_test_mask(b, nir_ushr(b, int_val, idx), 1); in lower_subgroups_instr()
|
| D | nir_builder.h | 1055 nir_test_mask(nir_builder *build, nir_def *x, uint64_t mask) in nir_test_mask() function
|
| /external/mesa3d/src/intel/compiler/ |
| D | brw_nir_lower_alpha_to_coverage.c | 179 nir_test_mask(&b, push_flags, INTEL_MSAA_FLAG_ALPHA_TO_COVERAGE); in brw_nir_lower_alpha_to_coverage()
|
| D | brw_nir_rt.c | 220 nir_def *skip_closest_hit = nir_test_mask(b, nir_load_ray_flags(b), in build_terminate_ray()
301 nir_def *terminate = nir_test_mask(&b, nir_load_ray_flags(&b), in lower_ray_walk_intrinsics()
|
| D | brw_nir_lower_intersection_shader.c | 253 nir_def *terminate = nir_test_mask(b, nir_load_ray_flags(b), in brw_nir_lower_intersection_shader()
|
| /external/mesa3d/src/intel/compiler/elk/ |
| D | elk_nir_lower_alpha_to_coverage.c | 179 nir_test_mask(&b, push_flags, INTEL_MSAA_FLAG_ALPHA_TO_COVERAGE); in elk_nir_lower_alpha_to_coverage()
|
| /external/mesa3d/src/panfrost/vulkan/jm/ |
| D | panvk_vX_cmd_query.c | 376 nir_push_if(b, nir_test_mask(b, flags, VK_QUERY_RESULT_64_BIT)); in nir_write_query_result()
442 nir_def *partial = nir_test_mask(b, flags, VK_QUERY_RESULT_PARTIAL_BIT); in panvk_nir_copy_query()
465 nir_test_mask(b, flags, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)); in panvk_nir_copy_query()
|
| /external/mesa3d/src/microsoft/vulkan/ |
| D | dzn_nir.c | 400 index_val = nir_bcsel(&b, nir_test_mask(&b, old_index_offset, 0x2), in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader()
421 index12 = nir_bcsel(&b, nir_test_mask(&b, old_index_offset, 0x2), in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader()
502 old_index0 = nir_bcsel(&b, nir_test_mask(&b, old_index0_offset, 0x2), in dzn_nir_triangle_fan_rewrite_index_shader()
518 old_index12 = nir_bcsel(&b, nir_test_mask(&b, old_index1_offset, 0x2), in dzn_nir_triangle_fan_rewrite_index_shader()
|
| /external/mesa3d/src/nouveau/vulkan/ |
| D | nvk_query_pool.c | 726 nir_push_if(b, nir_test_mask(b, flags, VK_QUERY_RESULT_64_BIT)); in nir_write_query_result()
778 nir_def *partial = nir_test_mask(b, flags, VK_QUERY_RESULT_PARTIAL_BIT); in nvk_nir_copy_query()
839 nir_push_if(b, nir_test_mask(b, flags, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)); in nvk_nir_copy_query()
|
| /external/mesa3d/src/vulkan/runtime/ |
| D | vk_texcompress_etc2.c | 216 nir_def *flip = nir_test_mask(&b, color_y, 1); in etc2_build_shader()
221 …nir_def *punchthrough_init = nir_iand(&b, alpha_bits_1, nir_inot(&b, nir_test_mask(&b, color_y, 2)… in etc2_build_shader()
248 …nir_push_if(&b, nir_iand(&b, nir_inot(&b, alpha_bits_1), nir_inot(&b, nir_test_mask(&b, color_y, 2… in etc2_build_shader()
|
| /external/mesa3d/src/microsoft/spirv_to_dxil/ |
| D | dxil_spirv_nir.c | 486 nir_def *flip = nir_test_mask(builder, y_flip_mask, 1); in lower_yz_flip()
493 nir_def *flip = nir_test_mask(builder, z_flip_mask, 1); in lower_yz_flip()
|
| /external/mesa3d/src/gallium/drivers/d3d12/ |
| D | d3d12_nir_passes.c | 343 …nir_push_if(b, nir_test_mask(b, nir_ishl(b, nir_imm_int(b, 1), state->viewport_index), state->view… in invert_depth_impl()
|
| /external/mesa3d/docs/relnotes/ |
| D | 22.2.0.rst | 3495 - nir: Add a nir_test_mask helper
3496 - radv: Use nir_test_mask instead of i2b(iand)
3497 - nir: Use nir_test_mask instead of i2b(iand)
3498 - d3d12: Use nir_test_mask instead of i2b(iand)
3499 - intel: Use nir_test_mask instead of i2b(iand)
3500 - microsoft: Use nir_test_mask instead of i2b(iand)
3501 - dozen: Use nir_test_mask instead of i2b(iand)
|