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Searched refs:num_rts (Results 1 – 13 of 13) sorted by relevance

/external/linux-kselftest/tools/testing/selftests/drivers/net/mlxsw/
Dfib_offload.sh260 local num_rts=$((40 * 1024))
275 total=$((nums_nhs * num_rts))
282 for i in $(seq 1 $num_rts); do
303 log_info "inserted $num_rts routes in $diff seconds"
/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_screen.c322 screen->specs.num_rts / 2 : in etna_init_screen_caps()
323 screen->specs.num_rts; in etna_init_screen_caps()
750 screen->specs.num_rts = 8; in etna_determine_num_rts()
752 screen->specs.num_rts = 4; in etna_determine_num_rts()
754 screen->specs.num_rts = 1; in etna_determine_num_rts()
Detnaviv_internal.h129 unsigned num_rts; member
Detnaviv_emit.c469 if (screen->specs.num_rts == 8) in etna_emit_state()
580 if (screen->specs.num_rts == 4) { in etna_emit_state()
587 } else if (screen->specs.num_rts == 8) { in etna_emit_state()
Detnaviv_compiler_nir.c1192 NIR_PASS_V(s, nir_lower_fragcolor, specs->num_rts); in etna_compile_shader()
/external/mesa3d/src/gallium/drivers/zink/
Dzink_render_pass.c346 …mesa_hash_data(key, offsetof(struct zink_render_pass_state, rts) + sizeof(s->rts[0]) * s->num_rts); in hash_render_pass_state()
353 if (s_a->num_rts != s_b->num_rts) in equals_render_pass_state()
355 …mcmp(a, b, offsetof(struct zink_render_pass_state, rts) + sizeof(s_a->rts[0]) * s_a->num_rts) == 0; in equals_render_pass_state()
479 state.num_rts++; in get_render_pass()
500 state.num_rts++; in get_render_pass()
Dzink_state.c362 cso->num_rts = blend_state->max_rt + 1; in zink_create_blend_state()
442 if (old_blend && blend->num_rts == old_blend->num_rts) { in zink_bind_blend_state()
443 if (memcmp(blend->ds3.eq, old_blend->ds3.eq, blend->num_rts * sizeof(blend->ds3.eq[0]))) in zink_bind_blend_state()
Dzink_types.h349 unsigned num_rts; member
1180 unsigned num_rts; member
Dzink_pipeline.c105 state->render_pass->state.num_rts : in zink_create_gfx_pipeline()
/external/mesa3d/src/freedreno/vulkan/
Dtu_clear_blit.cc845 for (uint32_t num_rts = 0; num_rts <= MAX_RTS; num_rts++) { in tu_init_clear_blit_shaders() local
846 compile_shader(dev, build_clear_fs_shader(num_rts), num_rts, &offset, in tu_init_clear_blit_shaders()
847 (enum global_shader) (GLOBAL_SH_FS_CLEAR0 + num_rts)); in tu_init_clear_blit_shaders()
892 unsigned num_rts = util_bitcount(rts_mask); in r3d_common() local
894 fs_id = (enum global_shader) (GLOBAL_SH_FS_CLEAR0 + num_rts); in r3d_common()
3991 unsigned num_rts = util_bitcount(clear_rts); in tu_clear_sysmem_attachments() local
4000 if (num_rts > 0) in tu_clear_sysmem_attachments()
4002 0, packed_clear_value, num_rts); in tu_clear_sysmem_attachments()
Dtu_pipeline.cc2962 unsigned num_rts = alpha_to_coverage_enable ? in tu6_blend_size() local
2964 return 8 + 3 * num_rts; in tu6_blend_size()
2996 unsigned num_rts = alpha_to_coverage_enable ? in tu6_emit_blend() local
3001 tu_cs_emit_regs(cs, A6XX_SP_FS_OUTPUT_CNTL1(.mrt = num_rts)); in tu6_emit_blend()
3002 tu_cs_emit_regs(cs, A6XX_RB_FS_OUTPUT_CNTL1(.mrt = num_rts)); in tu6_emit_blend()
3019 for (unsigned i = 0; i < num_rts; i++) { in tu6_emit_blend()
/external/mesa3d/src/imagination/vulkan/
Dpvr_hw_pass.c909 const uint32_t num_rts = hw_subpass->setup.num_render_targets; in pvr_copy_storage_details() local
911 hw_subpass->input_access[i].on_chip_rt = num_rts; in pvr_copy_storage_details()
915 hw_subpass->setup.mrt_resources[num_rts] = int_attach->resource; in pvr_copy_storage_details()
Dpvr_job_transfer.c1167 uint32_t num_rts = vk_format_get_plane_count(dst->vk_format); in pvr_pbe_setup() local
1175 num_rts = state->custom_mapping.passes[state->pass_idx].clip_rects_count; in pvr_pbe_setup()
1180 for (uint32_t i = 0U; i < num_rts; i++) { in pvr_pbe_setup()
1246 pvr_pbe_setup_emit(transfer_cmd, ctx, state, num_rts, pbe_setup_words); in pvr_pbe_setup()