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Searched +refs:tablegen +refs:mode +refs:syntax +refs:table (Results 1 – 8 of 8) sorted by relevance

/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
22 // A string representing subtarget features that turn on this HW mode.
23 // For example, "+feat1,-feat2" will indicate that the mode is active
31 // A special mode recognized by tablegen. This mode is considered active
32 // when no other mode is active. For targets that do not use specific hw
33 // modes, this is the only mode.
46 // dependent on a HW mode. This class inherits from ValueType itself,
64 // The register size/alignment information, parameterized by a HW mode.
161 // is invalid for this mode/flavour.
176 // generated table. It will considerably reduce the table size.
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
24 // A string representing subtarget features that turn on this HW mode.
25 // For example, "+feat1,-feat2" will indicate that the mode is active
33 // A special mode recognized by tablegen. This mode is considered active
34 // when no other mode is active. For targets that do not use specific hw
35 // modes, this is the only mode.
48 // dependent on a HW mode. This class inherits from ValueType itself,
66 // The register size/alignment information, parameterized by a HW mode.
163 // is invalid for this mode/flavour.
214 // The register size/alignment information, parameterized by a HW mode.
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/external/clang/docs/
DInternalsManual.rst257 The parser is very unforgiving. A syntax error, even whitespace, will abort,
365 semicolon at the end of a statement or a use of deprecated syntax that is
444 mode. Instead of formatting and printing out the diagnostics, this
448 documentation for the ``-verify`` mode can be found in the Clang API
599 not reading in "raw" mode) this contains a pointer to the unique hash value
731 * The lexer can operate in "raw" mode. This mode has several features that
734 This mode is used for lexing within an "``#if 0``" block, for example.
736 support the ``-C`` preprocessor mode, which passes comments through, and is
738 * The lexer can be in ``ParsingFilename`` mode, which happens when
739 preprocessing after reading a ``#include`` directive. This mode changes the
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/external/llvm/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
110 // is invalid for this mode/flavour.
301 // is invalid for this mode/flavour.
975 // syntax on X86 for example).
1008 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
1097 /// InstAlias - This defines an alternate assembly syntax that is allowed to
1127 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
1144 // syntax. If the asmstring contains {|} characters in them, this integer
1255 // instructions in a row of the relation table. Think of this as a set of
1271 // in a column of the relation table.
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td1 //===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===//
271 // FP rounding mode: bits 30 and 31 of the FP status and control register
290 // This also helps setting the correct `NumOfGPRsSaved' in traceback table.
454 // In the default PowerPC assembler syntax, registers are specified simply
787 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
/external/llvm/docs/
DGettingStarted.rst196 table below lists those required packages. The Package column is the usual name
239 * **ranlib** --- symbol table builder for archive libraries
305 **Clang in C++11 mode and libstdc++ 4.7.2**. This version of libstdc++
753 | LLVM_OPTIMIZED_TABLEGEN | Builds a release tablegen that gets used during |
1119 Emacs and XEmacs syntax highlighting for LLVM assembly files and TableGen
1154 vim syntax-highlighting for LLVM assembly files
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
166 // A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
185 // A subset of NEON instructions are legal in Streaming SVE execution mode,
931 // 32-bit jump table destination is actually only 2 instructions since we can
932 // use the table itself as a PC-relative base. But optimization occurs after
937 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,
940 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,
943 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,
1597 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
3224 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
665 // 32-bit jump table destination is actually only 2 instructions since we can
666 // use the table itself as a PC-relative base. But optimization occurs after
670 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,
673 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,
676 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,
1039 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
2528 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
2701 // FIXME: Use dedicated range-checked addressing mode operand here.
6477 // In big endian mode every memory access has an implicit byte swap. LDR and