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/external/python/cpython3/Lib/test/
Dtest_difflib.py354 unified = difflib.unified_diff
358 check(difflib.diff_bytes(unified, a, a))
359 check(difflib.diff_bytes(unified, a, b))
362 check(difflib.diff_bytes(unified, a, a, b'a', b'a'))
363 check(difflib.diff_bytes(unified, a, b, b'a', b'b'))
366 check(difflib.diff_bytes(unified, a, a, b'a', b'a', b'2005', b'2013'))
367 check(difflib.diff_bytes(unified, a, b, b'a', b'b', b'2005', b'2013'))
387 unified = difflib.unified_diff
389 check(difflib.diff_bytes(unified, a, b, fna, fnb))
407 actual = difflib.diff_bytes(unified, a, b, fna, fnb, lineterm=b'')
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/external/compiler-rt/lib/builtins/arm/
Daeabi_cfcmp.S27 .syntax unified
53 .syntax unified
81 .syntax unified
Daeabi_cdcmp.S27 .syntax unified
53 .syntax unified
81 .syntax unified
Dsync-ops.h21 .syntax unified ; \
37 .syntax unified ; \
Dnegdf2vfp.S18 .syntax unified
Dnegsf2vfp.S18 .syntax unified
Dsave_vfp_d8_d15_regs.S23 .syntax unified
Drestore_vfp_d8_d15_regs.S23 .syntax unified
/external/pytorch/test/cpp/jit/
Dtest_jit_type.cpp33 auto unified = unifyTypes(opt_bool_tensor, tensor); in TEST() local
34 TORCH_INTERNAL_ASSERT(unified); in TEST()
35 auto elem = (*unified)->expectRef<OptionalType>().getElementType(); in TEST()
/external/llvm/include/llvm/IR/
DIntrinsicsNVVM.td1415 "llvm.nvvm.tex.unified.1d.v4f32.s32">;
1419 "llvm.nvvm.tex.unified.1d.v4f32.f32">;
1423 "llvm.nvvm.tex.unified.1d.level.v4f32.f32">;
1428 "llvm.nvvm.tex.unified.1d.grad.v4f32.f32">;
1432 "llvm.nvvm.tex.unified.1d.v4s32.s32">;
1436 "llvm.nvvm.tex.unified.1d.v4s32.f32">;
1440 "llvm.nvvm.tex.unified.1d.level.v4s32.f32">;
1445 "llvm.nvvm.tex.unified.1d.grad.v4s32.f32">;
1449 "llvm.nvvm.tex.unified.1d.v4u32.s32">;
1453 "llvm.nvvm.tex.unified.1d.v4u32.f32">;
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/external/googleapis/google/ads/searchads360/v0/resources/
Dasset.proto105 // Output only. A unified callout asset.
109 // Output only. A unified sitelink asset.
113 // Output only. A unified page feed asset.
120 // Output only. A unified call asset.
128 // Output only. A unified location asset.
/external/llvm/test/CodeGen/NVPTX/
Dtex-read-cuda.ll7 declare { float, float, float, float } @llvm.nvvm.tex.unified.1d.v4f32.s32(i64, i32)
17 …%val = tail call { float, float, float, float } @llvm.nvvm.tex.unified.1d.v4f32.s32(i64 %img, i32 …
35 …%val = tail call { float, float, float, float } @llvm.nvvm.tex.unified.1d.v4f32.s32(i64 %texHandle…
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsNVVM.td1720 "llvm.nvvm.tex.unified.1d.v4f32.s32">;
1724 "llvm.nvvm.tex.unified.1d.v4f32.f32">;
1728 "llvm.nvvm.tex.unified.1d.level.v4f32.f32">;
1733 "llvm.nvvm.tex.unified.1d.grad.v4f32.f32">;
1737 "llvm.nvvm.tex.unified.1d.v4s32.s32">;
1741 "llvm.nvvm.tex.unified.1d.v4s32.f32">;
1745 "llvm.nvvm.tex.unified.1d.level.v4s32.f32">;
1750 "llvm.nvvm.tex.unified.1d.grad.v4s32.f32">;
1754 "llvm.nvvm.tex.unified.1d.v4u32.s32">;
1758 "llvm.nvvm.tex.unified.1d.v4u32.f32">;
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/external/sdv/vsomeip/third_party/boost/config/test/
Dboost_no_unified_init.ipp9 // TITLE: C++0x unified initialization syntax unavailable
10 // DESCRIPTION: The compiler does not support C++0x unified initialization syntax: see http://en…
/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/IR/
DIntrinsicsNVVM.td2141 "llvm.nvvm.tex.unified.1d.v4f32.s32">;
2145 "llvm.nvvm.tex.unified.1d.v4f32.f32">;
2149 "llvm.nvvm.tex.unified.1d.level.v4f32.f32">;
2154 "llvm.nvvm.tex.unified.1d.grad.v4f32.f32">;
2158 "llvm.nvvm.tex.unified.1d.v4s32.s32">;
2162 "llvm.nvvm.tex.unified.1d.v4s32.f32">;
2166 "llvm.nvvm.tex.unified.1d.level.v4s32.f32">;
2171 "llvm.nvvm.tex.unified.1d.grad.v4s32.f32">;
2175 "llvm.nvvm.tex.unified.1d.v4u32.s32">;
2179 "llvm.nvvm.tex.unified.1d.v4u32.f32">;
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/external/arm-trusted-firmware/docs/plat/
Dnvidia-tegra.rst11 a dedicated 2 MiB Level-2 unified cache. A high speed coherency fabric connects
27 unified cache. The Cortex-A57 processors each have 48 KB Instruction and 32 KB
28 Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A
65 Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
66 and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
/external/trusty/arm-trusted-firmware/docs/plat/
Dnvidia-tegra.rst11 a dedicated 2 MiB Level-2 unified cache. A high speed coherency fabric connects
27 unified cache. The Cortex-A57 processors each have 48 KB Instruction and 32 KB
28 Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A
65 Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
66 and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
/external/bcc/docs/
Dspecial_filtering.md40 `/sys/fs/cgroup/unified/system.slice/test.service`.
49 # ./cgroupid hex /sys/fs/cgroup/unified/system.slice/test.service
58 cgroupid cgroupid hex /sys/fs/cgroup/unified/system.slice/test.service
/external/parameter-framework/upstream/test/xml-generator/
Dtest.py80 unified = difflib.unified_diff(reference,
85 raise AssertionError("The result and the reference don't match:" + "\n".join(unified))
/external/musl/src/thread/arm/
D__unmapself.s1 .syntax unified
/external/trusty/musl/src/thread/arm/
D__unmapself.s1 .syntax unified
/external/musl/src/ldso/arm/
Ddlsym.s1 .syntax unified
/external/trusty/musl/crt/arm/
Dcrtn.s1 .syntax unified
/external/musl/crt/arm/
Dcrtn.s1 .syntax unified
/external/trusty/musl/src/ldso/arm/
Ddlsym.s1 .syntax unified

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