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Searched refs:width_in_tiles (Results 1 – 8 of 8) sorted by relevance

/external/ComputeLibrary/src/core/NEON/kernels/arm_conv/pooling/
Dpooling_depthfirst_cache_oblivious.hpp297 const unsigned int width_in_tiles = item.output_width / strategy::out_cols(); in execute() local
298 const unsigned int tiles_first = width_in_tiles - width_in_tiles / 2; in execute()
/external/minigbm/
Dxe.c553 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128); in xe_bo_compute_metadata() local
555 uint32_t size = width_in_tiles * height_in_tiles * 4096; in xe_bo_compute_metadata()
558 bo->meta.strides[0] = width_in_tiles * 128; in xe_bo_compute_metadata()
567 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32); in xe_bo_compute_metadata()
Di915.c685 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128); in i915_bo_compute_metadata() local
687 uint32_t size = width_in_tiles * height_in_tiles * 4096; in i915_bo_compute_metadata()
690 bo->meta.strides[0] = width_in_tiles * 128; in i915_bo_compute_metadata()
699 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32); in i915_bo_compute_metadata()
/external/mesa3d/src/amd/common/
Dac_surface.h230 uint16_t width_in_tiles; member
Dac_descriptors.c1023 ds->u.gfx12.hiz_size_xy = S_028BA4_X_MAX(surf->u.gfx9.zs.hiz.width_in_tiles - 1) | in ac_init_gfx12_ds_surface()
1032 ds->u.gfx12.his_size_xy = S_028BB0_X_MAX(surf->u.gfx9.zs.his.width_in_tiles - 1) | in ac_init_gfx12_ds_surface()
Dac_surface.c3074 hizs->width_in_tiles = in.width; in gfx12_compute_hiz_his_info()
4242 surf->u.gfx9.zs.hiz.width_in_tiles, surf->u.gfx9.zs.hiz.height_in_tiles); in ac_surface_print_info()
4249 surf->u.gfx9.zs.his.width_in_tiles, surf->u.gfx9.zs.his.height_in_tiles); in ac_surface_print_info()
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_draw.c86 bin.width_in_tiles = job->draw_tiles_x; in vc4_start_draw()
/external/mesa3d/src/imagination/vulkan/
Dpvr_job_transfer.c125 uint32_t width_in_tiles; member
785 state->width_in_tiles = 1U; in pvr_pbe_setup_codegen_defaults()
824 state->width_in_tiles = in pvr_pbe_setup_codegen_defaults()
832 state->width_in_tiles -= state->origin_x_in_tiles; in pvr_pbe_setup_codegen_defaults()
1272 state->width_in_tiles = in pvr_pbe_setup()
1295 uint32_t width = state->width_in_tiles; in pvr_isp_tiles()
3521 bias = state->width_in_tiles <= 256U && state->height_in_tiles <= 256U; in pvr_isp_prim_block_isp_vertices()