Home
last modified time | relevance | path

Searched refs:AND_OPCODE (Results 1 – 7 of 7) sorted by relevance

/hardware/google/apf/v4/
Dapf.h143 #define AND_OPCODE 10 // And, e.g. "and R0,5" macro
Dapf_interpreter.c230 case AND_OPCODE: in accept_packet()
/hardware/google/apf/next/
Dapf.h177 #define AND_OPCODE 10 // And, e.g. "and R0,5" macro
Dapf_interpreter.c233 #define AND_OPCODE 10 /* And, e.g. "and R0,5" */ macro
949 case AND_OPCODE: ARITH_REG &= (ctx->v6) ? (u32)arith_signed_imm : arith_imm; break; in do_apf_run()
Dapf_interpreter_source.c344 case AND_OPCODE: ARITH_REG &= (ctx->v6) ? (u32)arith_signed_imm : arith_imm; break; in do_apf_run()
/hardware/google/apf/
Ddisassembler.c65 [AND_OPCODE] = "and",
281 case AND_OPCODE: { in apf_disassemble()
287 } else if (opcode == AND_OPCODE) { in apf_disassemble()
295 } else if (opcode == AND_OPCODE) { in apf_disassemble()
/hardware/google/apf/v6/
Dapf_interpreter.c233 #define AND_OPCODE 10 /* And, e.g. "and R0,5" */ macro
853 case AND_OPCODE: ARITH_REG &= (ctx->v6) ? (u32)arith_signed_imm : arith_imm; break; in do_apf_run()