1# 2# Copyright (C) 2018 Red Hat 3# Copyright (C) 2014 Intel Corporation 4# 5# Permission is hereby granted, free of charge, to any person obtaining a 6# copy of this software and associated documentation files (the "Software"), 7# to deal in the Software without restriction, including without limitation 8# the rights to use, copy, modify, merge, publish, distribute, sublicense, 9# and/or sell copies of the Software, and to permit persons to whom the 10# Software is furnished to do so, subject to the following conditions: 11# 12# The above copyright notice and this permission notice (including the next 13# paragraph) shall be included in all copies or substantial portions of the 14# Software. 15# 16# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22# IN THE SOFTWARE. 23# 24 25# This file defines all the available intrinsics in one place. 26# 27# The Intrinsic class corresponds one-to-one with nir_intrinsic_info 28# structure. 29 30src0 = ('src', 0) 31src1 = ('src', 1) 32src2 = ('src', 2) 33src3 = ('src', 3) 34src4 = ('src', 4) 35 36class Index(object): 37 def __init__(self, c_data_type, name): 38 self.c_data_type = c_data_type 39 self.name = name 40 41class Intrinsic(object): 42 """Class that represents all the information about an intrinsic opcode. 43 NOTE: this must be kept in sync with nir_intrinsic_info. 44 """ 45 def __init__(self, name, src_components, dest_components, 46 indices, flags, sysval, bit_sizes): 47 """Parameters: 48 49 - name: the intrinsic name 50 - src_components: list of the number of components per src, 0 means 51 vectorized instruction with number of components given in the 52 num_components field in nir_intrinsic_instr. 53 - dest_components: number of destination components, -1 means no 54 dest, 0 means number of components given in num_components field 55 in nir_intrinsic_instr. 56 - indices: list of constant indicies 57 - flags: list of semantic flags 58 - sysval: is this a system-value intrinsic 59 - bit_sizes: allowed dest bit_sizes or the source it must match 60 """ 61 assert isinstance(name, str) 62 assert isinstance(src_components, list) 63 if src_components: 64 assert isinstance(src_components[0], int) 65 assert isinstance(dest_components, int) 66 assert isinstance(indices, list) 67 if indices: 68 assert isinstance(indices[0], Index) 69 assert isinstance(flags, list) 70 if flags: 71 assert isinstance(flags[0], str) 72 assert isinstance(sysval, bool) 73 if isinstance(bit_sizes, list): 74 assert not bit_sizes or isinstance(bit_sizes[0], int) 75 else: 76 assert isinstance(bit_sizes, tuple) 77 assert bit_sizes[0] == 'src' 78 assert isinstance(bit_sizes[1], int) 79 80 self.name = name 81 self.num_srcs = len(src_components) 82 self.src_components = src_components 83 self.has_dest = (dest_components >= 0) 84 self.dest_components = dest_components 85 self.num_indices = len(indices) 86 self.indices = indices 87 self.flags = flags 88 self.sysval = sysval 89 self.bit_sizes = bit_sizes if isinstance(bit_sizes, list) else [] 90 self.bit_size_src = bit_sizes[1] if isinstance(bit_sizes, tuple) else -1 91 92# 93# Possible flags: 94# 95 96CAN_ELIMINATE = "NIR_INTRINSIC_CAN_ELIMINATE" 97CAN_REORDER = "NIR_INTRINSIC_CAN_REORDER" 98 99INTR_INDICES = [] 100INTR_OPCODES = {} 101 102def index(c_data_type, name): 103 idx = Index(c_data_type, name) 104 INTR_INDICES.append(idx) 105 globals()[name.upper()] = idx 106 107# Defines a new NIR intrinsic. By default, the intrinsic will have no sources 108# and no destination. 109# 110# You can set dest_comp=n to enable a destination for the intrinsic, in which 111# case it will have that many components, or =0 for "as many components as the 112# NIR destination value." 113# 114# Set src_comp=n to enable sources for the intruction. It can be an array of 115# component counts, or (for convenience) a scalar component count if there's 116# only one source. If a component count is 0, it will be as many components as 117# the intrinsic has based on the dest_comp. 118def intrinsic(name, src_comp=[], dest_comp=-1, indices=[], 119 flags=[], sysval=False, bit_sizes=[]): 120 assert name not in INTR_OPCODES 121 INTR_OPCODES[name] = Intrinsic(name, src_comp, dest_comp, 122 indices, flags, sysval, bit_sizes) 123 124# 125# Possible indices: 126# 127 128# Generally instructions that take a offset src argument, can encode 129# a constant 'base' value which is added to the offset. 130index("int", "base") 131 132# For store instructions, a writemask for the store. 133index("unsigned", "write_mask") 134 135# The stream-id for GS emit_vertex/end_primitive intrinsics. 136index("unsigned", "stream_id") 137 138# The clip-plane id for load_user_clip_plane intrinsic. 139index("unsigned", "ucp_id") 140 141# The offset to the start of the NIR_INTRINSIC_RANGE. This is an alternative 142# to NIR_INTRINSIC_BASE for describing the valid range in intrinsics that don't 143# have the implicit addition of a base to the offset. 144# 145# If the [range_base, range] is [0, ~0], then we don't know the possible 146# range of the access. 147index("unsigned", "range_base") 148 149# The amount of data, starting from BASE or RANGE_BASE, that this 150# instruction may access. This is used to provide bounds if the offset is 151# not constant. 152index("unsigned", "range") 153 154# The Vulkan descriptor set for vulkan_resource_index intrinsic. 155index("unsigned", "desc_set") 156 157# The Vulkan descriptor set binding for vulkan_resource_index intrinsic. 158index("unsigned", "binding") 159 160# Component offset 161index("unsigned", "component") 162 163# Column index for matrix system values 164index("unsigned", "column") 165 166# Interpolation mode (only meaningful for FS inputs) 167index("unsigned", "interp_mode") 168 169# A binary nir_op to use when performing a reduction or scan operation 170index("unsigned", "reduction_op") 171 172# Cluster size for reduction operations 173index("unsigned", "cluster_size") 174 175# Parameter index for a load_param intrinsic 176index("unsigned", "param_idx") 177 178# Image dimensionality for image intrinsics 179index("enum glsl_sampler_dim", "image_dim") 180 181# Non-zero if we are accessing an array image 182index("bool", "image_array") 183 184# Image format for image intrinsics 185# Vertex buffer format for load_typed_buffer_amd 186index("enum pipe_format", "format") 187 188# Access qualifiers for image and memory access intrinsics. ACCESS_RESTRICT is 189# not set at the intrinsic if the NIR was created from SPIR-V. 190index("enum gl_access_qualifier", "access") 191 192# call index for split raytracing shaders 193index("unsigned", "call_idx") 194 195# The stack size increment/decrement for split raytracing shaders 196index("unsigned", "stack_size") 197 198# Alignment for offsets and addresses 199# 200# These two parameters, specify an alignment in terms of a multiplier and 201# an offset. The multiplier is always a power of two. The offset or 202# address parameter X of the intrinsic is guaranteed to satisfy the 203# following: 204# 205# (X - align_offset) % align_mul == 0 206# 207# For constant offset values, align_mul will be NIR_ALIGN_MUL_MAX and the 208# align_offset will be modulo that. 209index("unsigned", "align_mul") 210index("unsigned", "align_offset") 211 212# The Vulkan descriptor type for a vulkan_resource_[re]index intrinsic. 213index("unsigned", "desc_type") 214 215# The nir_alu_type of input data to a store or conversion 216index("nir_alu_type", "src_type") 217 218# The nir_alu_type of the data output from a load or conversion 219index("nir_alu_type", "dest_type") 220 221# The swizzle mask for quad_swizzle_amd & masked_swizzle_amd 222index("unsigned", "swizzle_mask") 223 224# Allow FI=1 for quad_swizzle_amd & masked_swizzle_amd 225index("bool", "fetch_inactive") 226 227# Offsets for load_shared2_amd/store_shared2_amd 228index("uint8_t", "offset0") 229index("uint8_t", "offset1") 230 231# If true, both offsets have an additional stride of 64 dwords (ie. they are multiplied by 256 bytes 232# in hardware, instead of 4). 233index("bool", "st64") 234 235# When set, range analysis will use it for nir_unsigned_upper_bound 236index("unsigned", "arg_upper_bound_u32_amd") 237 238# Separate source/dest access flags for copies 239index("enum gl_access_qualifier", "dst_access") 240index("enum gl_access_qualifier", "src_access") 241 242# Driver location of attribute 243index("unsigned", "driver_location") 244 245# Ordering and visibility of a memory operation 246index("nir_memory_semantics", "memory_semantics") 247 248# Modes affected by a memory operation 249index("nir_variable_mode", "memory_modes") 250 251# Scope of a memory operation 252index("mesa_scope", "memory_scope") 253 254# Scope of a control barrier 255index("mesa_scope", "execution_scope") 256 257# Semantics of an IO instruction 258index("struct nir_io_semantics", "io_semantics") 259 260# Transform feedback info 261index("struct nir_io_xfb", "io_xfb") 262index("struct nir_io_xfb", "io_xfb2") 263 264# Ray query values accessible from the RayQueryKHR object 265index("nir_ray_query_value", "ray_query_value") 266 267# Select between committed and candidate ray queriy intersections 268index("bool", "committed") 269 270# Rounding mode for conversions 271index("nir_rounding_mode", "rounding_mode") 272 273# Whether or not to saturate in conversions 274index("unsigned", "saturate") 275 276# Whether or not trace_ray_intel is synchronous 277index("bool", "synchronous") 278 279# Value ID to identify SSA value loaded/stored on the stack 280index("unsigned", "value_id") 281 282# Whether to sign-extend offsets in address arithmatic (else zero extend) 283index("bool", "sign_extend") 284 285# Instruction specific flags 286index("unsigned", "flags") 287 288# Logical operation of an atomic intrinsic 289index("nir_atomic_op", "atomic_op") 290 291# Block identifier to push promotion 292index("unsigned", "resource_block_intel") 293 294# Various flags describing the resource access 295index("nir_resource_data_intel", "resource_access_intel") 296 297# Register metadata 298# number of vector components 299index("unsigned", "num_components") 300# size of array (0 for no array) 301index("unsigned", "num_array_elems") 302# The bit-size of each channel; must be one of 1, 8, 16, 32, or 64 303index("unsigned", "bit_size") 304# True if this register may have different values in different SIMD invocations 305# of the shader. 306index("bool", "divergent") 307 308# On a register load, floating-point absolute value/negate loaded value. 309index("bool", "legacy_fabs") 310index("bool", "legacy_fneg") 311 312# On a register store, floating-point saturate the stored value. 313index("bool", "legacy_fsat") 314 315# For Cooperative Matrix intrinsics. 316index("struct glsl_cmat_description", "cmat_desc") 317index("enum glsl_matrix_layout", "matrix_layout") 318index("nir_cmat_signed", "cmat_signed_mask") 319index("nir_op", "alu_op") 320 321# For Intel DPAS instrinsic. 322index("unsigned", "systolic_depth") 323index("unsigned", "repeat_count") 324 325# For an AGX tilebuffer intrinsics, whether the coordinates are implicit or 326# explicit. Implicit coordinates are used in fragment shaders, explicit 327# coordinates in compute. 328index("bool", "explicit_coord") 329 330intrinsic("nop", flags=[CAN_ELIMINATE]) 331 332# Uses a value and cannot be eliminated. 333# 334# This is helpful when writing unit tests 335intrinsic("use", src_comp=[0], flags=[]) 336 337intrinsic("convert_alu_types", dest_comp=0, src_comp=[0], 338 indices=[SRC_TYPE, DEST_TYPE, ROUNDING_MODE, SATURATE], 339 flags=[CAN_ELIMINATE, CAN_REORDER]) 340 341intrinsic("load_param", dest_comp=0, indices=[PARAM_IDX], flags=[CAN_ELIMINATE]) 342 343intrinsic("load_deref", dest_comp=0, src_comp=[-1], 344 indices=[ACCESS], flags=[CAN_ELIMINATE]) 345intrinsic("store_deref", src_comp=[-1, 0], indices=[WRITE_MASK, ACCESS]) 346intrinsic("copy_deref", src_comp=[-1, -1], indices=[DST_ACCESS, SRC_ACCESS]) 347intrinsic("memcpy_deref", src_comp=[-1, -1, 1], indices=[DST_ACCESS, SRC_ACCESS]) 348 349# Returns an opaque handle representing a register indexed by BASE. The 350# logically def-use list of a register is given by the use list of this handle. 351# The shape of the underlying register is given by the indices, the handle 352# itself is always a 32-bit scalar. 353intrinsic("decl_reg", dest_comp=1, 354 indices=[NUM_COMPONENTS, NUM_ARRAY_ELEMS, BIT_SIZE, DIVERGENT], 355 flags=[CAN_ELIMINATE]) 356 357# Load a register given as the source directly with base offset BASE. 358intrinsic("load_reg", dest_comp=0, src_comp=[1], 359 indices=[BASE, LEGACY_FABS, LEGACY_FNEG], flags=[CAN_ELIMINATE]) 360 361# Load a register given as first source indirectly with base offset BASE and 362# indirect offset as second source. 363intrinsic("load_reg_indirect", dest_comp=0, src_comp=[1, 1], 364 indices=[BASE, LEGACY_FABS, LEGACY_FNEG], flags=[CAN_ELIMINATE]) 365 366# Store the value in the first source to a register given as the second source 367# directly with base offset BASE. 368intrinsic("store_reg", src_comp=[0, 1], 369 indices=[BASE, WRITE_MASK, LEGACY_FSAT]) 370 371# Store the value in the first source to a register given as the second 372# source indirectly with base offset BASE and indirect offset as third source. 373intrinsic("store_reg_indirect", src_comp=[0, 1, 1], 374 indices=[BASE, WRITE_MASK, LEGACY_FSAT]) 375 376# Interpolation of input. The interp_deref_at* intrinsics are similar to the 377# load_var intrinsic acting on a shader input except that they interpolate the 378# input differently. The at_sample, at_offset and at_vertex intrinsics take an 379# additional source that is an integer sample id, a vec2 position offset, or a 380# vertex ID respectively. 381 382intrinsic("interp_deref_at_centroid", dest_comp=0, src_comp=[1], 383 flags=[ CAN_ELIMINATE, CAN_REORDER]) 384intrinsic("interp_deref_at_sample", src_comp=[1, 1], dest_comp=0, 385 flags=[CAN_ELIMINATE, CAN_REORDER]) 386intrinsic("interp_deref_at_offset", src_comp=[1, 2], dest_comp=0, 387 flags=[CAN_ELIMINATE, CAN_REORDER]) 388intrinsic("interp_deref_at_vertex", src_comp=[1, 1], dest_comp=0, 389 flags=[CAN_ELIMINATE, CAN_REORDER]) 390 391# Gets the length of an unsized array at the end of a buffer 392intrinsic("deref_buffer_array_length", src_comp=[-1], dest_comp=1, 393 indices=[ACCESS], flags=[CAN_ELIMINATE, CAN_REORDER]) 394 395# Gets the length of an unsized array 396intrinsic("deref_implicit_array_length", src_comp=[-1], dest_comp=1, 397 flags=[CAN_ELIMINATE, CAN_REORDER]) 398 399# Ask the driver for the size of a given SSBO. It takes the buffer index 400# as source. 401intrinsic("get_ssbo_size", src_comp=[-1], dest_comp=1, bit_sizes=[32], 402 indices=[ACCESS], flags=[CAN_ELIMINATE, CAN_REORDER]) 403intrinsic("get_ubo_size", src_comp=[-1], dest_comp=1, 404 flags=[CAN_ELIMINATE, CAN_REORDER]) 405 406# Intrinsics which provide a run-time mode-check. Unlike the compile-time 407# mode checks, a pointer can only have exactly one mode at runtime. 408intrinsic("deref_mode_is", src_comp=[-1], dest_comp=1, 409 indices=[MEMORY_MODES], flags=[CAN_ELIMINATE, CAN_REORDER]) 410intrinsic("addr_mode_is", src_comp=[-1], dest_comp=1, 411 indices=[MEMORY_MODES], flags=[CAN_ELIMINATE, CAN_REORDER]) 412 413intrinsic("is_sparse_texels_resident", dest_comp=1, src_comp=[1], bit_sizes=[1,32], 414 flags=[CAN_ELIMINATE, CAN_REORDER]) 415# result code is resident only if both inputs are resident 416intrinsic("sparse_residency_code_and", dest_comp=1, src_comp=[1, 1], bit_sizes=[32], 417 flags=[CAN_ELIMINATE, CAN_REORDER]) 418 419# Unlike is_sparse_texels_resident, this intrinsic is required to consume 420# the destination of the nir_tex_instr or sparse_load intrinsic directly. 421# As such it is allowed to ignore the .e component where we usually store 422# sparse information. 423intrinsic("is_sparse_resident_zink", dest_comp=1, src_comp=[0], bit_sizes=[1], 424 flags=[CAN_ELIMINATE, CAN_REORDER]) 425 426# The following intrinsics calculate screen-space partial derivatives. These are 427# not CAN_REORDER as they cannot be moved across discards. 428for suffix in ["", "_fine", "_coarse"]: 429 for axis in ["x", "y"]: 430 intrinsic(f"dd{axis}{suffix}", dest_comp=0, src_comp=[0], 431 bit_sizes=[16, 32], flags=[CAN_ELIMINATE]) 432 433# a barrier is an intrinsic with no inputs/outputs but which can't be moved 434# around/optimized in general 435def barrier(name): 436 intrinsic(name) 437 438# Demote fragment shader invocation to a helper invocation. Any stores to 439# memory after this instruction are suppressed and the fragment does not write 440# outputs to the framebuffer. Unlike discard, demote needs to ensure that 441# derivatives will still work for invocations that were not demoted. 442# 443# As specified by SPV_EXT_demote_to_helper_invocation. 444barrier("demote") 445intrinsic("is_helper_invocation", dest_comp=1, flags=[CAN_ELIMINATE]) 446 447# SpvOpTerminateInvocation from SPIR-V. Essentially a discard "for real". 448barrier("terminate") 449 450# NonSemantic.DebugBreak from SPIR-V. Essentially used to emit breakpoints in 451# shaders. 452barrier("debug_break") 453 454# Control/Memory barrier with explicit scope. Follows the semantics of SPIR-V 455# OpMemoryBarrier and OpControlBarrier, used to implement Vulkan Memory Model. 456# Storage that the barrier applies is represented using NIR variable modes. 457# For an OpMemoryBarrier, set EXECUTION_SCOPE to SCOPE_NONE. 458intrinsic("barrier", 459 indices=[EXECUTION_SCOPE, MEMORY_SCOPE, MEMORY_SEMANTICS, MEMORY_MODES]) 460 461# Shader clock intrinsic with semantics analogous to the clock2x32ARB() 462# GLSL intrinsic. 463# The latter can be used as code motion barrier, which is currently not 464# feasible with NIR. 465intrinsic("shader_clock", dest_comp=2, bit_sizes=[32], flags=[CAN_ELIMINATE], 466 indices=[MEMORY_SCOPE]) 467 468# Shader ballot intrinsics with semantics analogous to the 469# 470# ballotARB() 471# readInvocationARB() 472# readFirstInvocationARB() 473# 474# GLSL functions from ARB_shader_ballot. 475intrinsic("ballot", src_comp=[1], dest_comp=0, flags=[CAN_ELIMINATE]) 476intrinsic("read_invocation", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 477intrinsic("read_first_invocation", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 478 479# Same as ballot, but inactive invocations contribute undefined bits. 480intrinsic("ballot_relaxed", src_comp=[1], dest_comp=0, flags=[CAN_ELIMINATE]) 481 482# Allows the backend compiler to move this value to an uniform register. 483# Result is undefined if src is not uniform. 484# Unlike read_first_invocation, it may be replaced by a divergent move or CSE'd. 485intrinsic("as_uniform", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 486 487# Returns the value of the first source for the lane where the second source is 488# true. The second source must be true for exactly one lane. 489intrinsic("read_invocation_cond_ir3", src_comp=[0, 1], dest_comp=0, flags=[CAN_ELIMINATE]) 490 491# Like read_first_invocation but using the getlast instruction instead of 492# getone. More specifically, this will read the value from the last active 493# invocation of the first cluster of 8 invocations with an active invocation. 494intrinsic("read_getlast_ir3", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 495 496# Additional SPIR-V ballot intrinsics 497# 498# These correspond to the SPIR-V opcodes 499# 500# OpGroupNonUniformElect 501# OpSubgroupFirstInvocationKHR 502# OpGroupNonUniformInverseBallot 503intrinsic("elect", dest_comp=1, flags=[CAN_ELIMINATE]) 504intrinsic("first_invocation", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 505intrinsic("last_invocation", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 506intrinsic("inverse_ballot", src_comp=[0], dest_comp=1, flags=[CAN_ELIMINATE]) 507 508barrier("begin_invocation_interlock") 509barrier("end_invocation_interlock") 510 511# A conditional demote/terminate, with a single boolean source. 512intrinsic("demote_if", src_comp=[1]) 513intrinsic("terminate_if", src_comp=[1]) 514 515# ARB_shader_group_vote intrinsics 516intrinsic("vote_any", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 517intrinsic("vote_all", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 518intrinsic("vote_feq", src_comp=[0], dest_comp=1, flags=[CAN_ELIMINATE]) 519intrinsic("vote_ieq", src_comp=[0], dest_comp=1, flags=[CAN_ELIMINATE]) 520 521# Ballot ALU operations from SPIR-V. 522# 523# These operations work like their ALU counterparts except that the operate 524# on a uvec4 which is treated as a 128bit integer. Also, they are, in 525# general, free to ignore any bits which are above the subgroup size. 526intrinsic("ballot_bitfield_extract", src_comp=[4, 1], dest_comp=1, flags=[CAN_REORDER, CAN_ELIMINATE]) 527intrinsic("ballot_bit_count_reduce", src_comp=[4], dest_comp=1, flags=[CAN_REORDER, CAN_ELIMINATE]) 528intrinsic("ballot_bit_count_inclusive", src_comp=[4], dest_comp=1, flags=[CAN_REORDER, CAN_ELIMINATE]) 529intrinsic("ballot_bit_count_exclusive", src_comp=[4], dest_comp=1, flags=[CAN_REORDER, CAN_ELIMINATE]) 530intrinsic("ballot_find_lsb", src_comp=[4], dest_comp=1, flags=[CAN_REORDER, CAN_ELIMINATE]) 531intrinsic("ballot_find_msb", src_comp=[4], dest_comp=1, flags=[CAN_REORDER, CAN_ELIMINATE]) 532 533# Shuffle operations from SPIR-V. 534intrinsic("shuffle", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 535intrinsic("shuffle_xor", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 536intrinsic("shuffle_up", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 537intrinsic("shuffle_down", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 538 539# Quad operations from SPIR-V. 540intrinsic("quad_broadcast", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 541intrinsic("quad_swap_horizontal", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 542intrinsic("quad_swap_vertical", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 543intrinsic("quad_swap_diagonal", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 544 545# Similar to vote_any and vote_all, but per-quad instead of per-wavefront. 546# Equivalent to subgroupOr(val, 4) and subgroupAnd(val, 4) assuming val is 547# boolean. 548intrinsic("quad_vote_any", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 549intrinsic("quad_vote_all", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 550 551# Rotate operation from SPIR-V: SpvOpGroupNonUniformRotateKHR. 552intrinsic("rotate", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, 553 indices=[CLUSTER_SIZE], flags=[CAN_ELIMINATE]); 554 555intrinsic("reduce", src_comp=[0], dest_comp=0, bit_sizes=src0, 556 indices=[REDUCTION_OP, CLUSTER_SIZE], flags=[CAN_ELIMINATE]) 557intrinsic("inclusive_scan", src_comp=[0], dest_comp=0, bit_sizes=src0, 558 indices=[REDUCTION_OP], flags=[CAN_ELIMINATE]) 559intrinsic("exclusive_scan", src_comp=[0], dest_comp=0, bit_sizes=src0, 560 indices=[REDUCTION_OP], flags=[CAN_ELIMINATE]) 561 562# AMD shader ballot operations 563intrinsic("quad_swizzle_amd", src_comp=[0], dest_comp=0, bit_sizes=src0, 564 indices=[SWIZZLE_MASK, FETCH_INACTIVE], flags=[CAN_ELIMINATE]) 565intrinsic("masked_swizzle_amd", src_comp=[0], dest_comp=0, bit_sizes=src0, 566 indices=[SWIZZLE_MASK, FETCH_INACTIVE], flags=[CAN_ELIMINATE]) 567intrinsic("write_invocation_amd", src_comp=[0, 0, 1], dest_comp=0, bit_sizes=src0, 568 flags=[CAN_ELIMINATE]) 569# src = [ mask, addition ] 570intrinsic("mbcnt_amd", src_comp=[1, 1], dest_comp=1, bit_sizes=[32], flags=[CAN_REORDER, CAN_ELIMINATE]) 571# Compiled to v_permlane16_b32. src = [ value, lanesel_lo, lanesel_hi ] 572intrinsic("lane_permute_16_amd", src_comp=[1, 1, 1], dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 573# subgroup shuffle up/down with cluster size 16. 574# base in [-15, -1]: DPP_ROW_SR 575# base in [ 1, 15]: DPP_ROW_SL, otherwise invalid. 576# Returns zero for invocations that try to read out of bounds 577intrinsic("dpp16_shift_amd", src_comp=[0], dest_comp=0, bit_sizes=src0, indices=[BASE], flags=[CAN_ELIMINATE]) 578 579# Basic Geometry Shader intrinsics. 580# 581# emit_vertex implements GLSL's EmitStreamVertex() built-in. It takes a single 582# index, which is the stream ID to write to. 583# 584# end_primitive implements GLSL's EndPrimitive() built-in. 585intrinsic("emit_vertex", indices=[STREAM_ID]) 586intrinsic("end_primitive", indices=[STREAM_ID]) 587 588# Geometry Shader intrinsics with a vertex count. 589# 590# Alternatively, drivers may implement these intrinsics, and use 591# nir_lower_gs_intrinsics() to convert from the basic intrinsics. 592# 593# These contain four additional unsigned integer sources: 594# 1. The total number of vertices emitted so far. 595# 2. The number of vertices emitted for the current primitive 596# so far if we're counting, otherwise undef. 597# 3. The total number of primitives emitted so far. 598# 4. The total number of decomposed primitives emitted so far. This counts like 599# the PRIMITIVES_GENERATED query: a triangle strip with 5 vertices is counted 600# as 3 primitives (not 1). 601intrinsic("emit_vertex_with_counter", src_comp=[1, 1, 1, 1], indices=[STREAM_ID]) 602intrinsic("end_primitive_with_counter", src_comp=[1, 1, 1, 1], indices=[STREAM_ID]) 603# Contains the final total vertex, primitive, and decomposed primitives counts 604# in the current GS thread. 605intrinsic("set_vertex_and_primitive_count", src_comp=[1, 1, 1], indices=[STREAM_ID]) 606 607# Launches mesh shader workgroups from a task shader, with explicit task_payload. 608# Rules: 609# - This is a terminating instruction. 610# - May only occur in workgroup-uniform control flow. 611# - Dispatch sizes may be divergent (in which case the values 612# from the first invocation are used). 613# Meaning of indices: 614# - BASE: address of the task_payload variable used. 615# - RANGE: size of the task_payload variable used. 616# 617# src[] = {vec(x, y, z)} 618intrinsic("launch_mesh_workgroups", src_comp=[3], indices=[BASE, RANGE]) 619 620# Launches mesh shader workgroups from a task shader, with task_payload variable deref. 621# Same rules as launch_mesh_workgroups apply here as well. 622# src[] = {vec(x, y, z), payload pointer} 623intrinsic("launch_mesh_workgroups_with_payload_deref", src_comp=[3, -1], indices=[]) 624 625# Trace a ray through an acceleration structure 626# 627# This instruction has a lot of parameters: 628# 0. Acceleration Structure 629# 1. Ray Flags 630# 2. Cull Mask 631# 3. SBT Offset 632# 4. SBT Stride 633# 5. Miss shader index 634# 6. Ray Origin 635# 7. Ray Tmin 636# 8. Ray Direction 637# 9. Ray Tmax 638# 10. Payload 639intrinsic("trace_ray", src_comp=[-1, 1, 1, 1, 1, 1, 3, 1, 3, 1, -1]) 640# src[] = { hit_t, hit_kind } 641intrinsic("report_ray_intersection", src_comp=[1, 1], dest_comp=1) 642intrinsic("ignore_ray_intersection") 643intrinsic("accept_ray_intersection") # Not in SPIR-V; useful for lowering 644intrinsic("terminate_ray") 645# src[] = { sbt_index, payload } 646intrinsic("execute_callable", src_comp=[1, -1]) 647 648# Initialize a ray query 649# 650# 0. Ray Query 651# 1. Acceleration Structure 652# 2. Ray Flags 653# 3. Cull Mask 654# 4. Ray Origin 655# 5. Ray Tmin 656# 6. Ray Direction 657# 7. Ray Tmax 658intrinsic("rq_initialize", src_comp=[-1, -1, 1, 1, 3, 1, 3, 1]) 659# src[] = { query } 660intrinsic("rq_terminate", src_comp=[-1]) 661# src[] = { query } 662intrinsic("rq_proceed", src_comp=[-1], dest_comp=1) 663# src[] = { query, hit } 664intrinsic("rq_generate_intersection", src_comp=[-1, 1]) 665# src[] = { query } 666intrinsic("rq_confirm_intersection", src_comp=[-1]) 667# src[] = { query } 668intrinsic("rq_load", src_comp=[-1], dest_comp=0, indices=[RAY_QUERY_VALUE,COMMITTED,COLUMN]) 669 670# Driver independent raytracing helpers 671 672# rt_resume is a helper that that be the first instruction accesing the 673# stack/scratch in a resume shader for a raytracing pipeline. It includes the 674# resume index (for nir_lower_shader_calls_internal reasons) and the stack size 675# of the variables spilled during the call. The stack size can be use to e.g. 676# adjust a stack pointer. 677intrinsic("rt_resume", indices=[CALL_IDX, STACK_SIZE]) 678 679# Lowered version of execute_callabe that includes the index of the resume 680# shader, and the amount of scratch space needed for this call (.ie. how much 681# to increase a stack pointer by). 682# src[] = { sbt_index, payload } 683intrinsic("rt_execute_callable", src_comp=[1, -1], indices=[CALL_IDX,STACK_SIZE]) 684 685# Lowered version of trace_ray in a similar vein to rt_execute_callable. 686# src same as trace_ray 687intrinsic("rt_trace_ray", src_comp=[-1, 1, 1, 1, 1, 1, 3, 1, 3, 1, -1], 688 indices=[CALL_IDX, STACK_SIZE]) 689 690 691# Atomic counters 692# 693# The *_deref variants take an atomic_uint nir_variable, while the other, 694# lowered, variants take a buffer index and register offset. The buffer index 695# is always constant, as there's no way to declare an array of atomic counter 696# buffers. 697# 698# The register offset may be non-constant but must by dynamically uniform 699# ("Atomic counters aggregated into arrays within a shader can only be indexed 700# with dynamically uniform integral expressions, otherwise results are 701# undefined.") 702def atomic(name, flags=[]): 703 intrinsic(name + "_deref", src_comp=[-1], dest_comp=1, flags=flags) 704 intrinsic(name, src_comp=[1], dest_comp=1, indices=[BASE, RANGE_BASE], flags=flags) 705 706def atomic2(name): 707 intrinsic(name + "_deref", src_comp=[-1, 1], dest_comp=1) 708 intrinsic(name, src_comp=[1, 1], dest_comp=1, indices=[BASE, RANGE_BASE]) 709 710def atomic3(name): 711 intrinsic(name + "_deref", src_comp=[-1, 1, 1], dest_comp=1) 712 intrinsic(name, src_comp=[1, 1, 1], dest_comp=1, indices=[BASE, RANGE_BASE]) 713 714atomic("atomic_counter_inc") 715atomic("atomic_counter_pre_dec") 716atomic("atomic_counter_post_dec") 717atomic("atomic_counter_read", flags=[CAN_ELIMINATE]) 718atomic2("atomic_counter_add") 719atomic2("atomic_counter_min") 720atomic2("atomic_counter_max") 721atomic2("atomic_counter_and") 722atomic2("atomic_counter_or") 723atomic2("atomic_counter_xor") 724atomic2("atomic_counter_exchange") 725atomic3("atomic_counter_comp_swap") 726 727# Image load, store and atomic intrinsics. 728# 729# All image intrinsics come in three versions. One which take an image target 730# passed as a deref chain as the first source, one which takes an index as the 731# first source, and one which takes a bindless handle as the first source. 732# In the first version, the image variable contains the memory and layout 733# qualifiers that influence the semantics of the intrinsic. In the second and 734# third, the image format and access qualifiers are provided as constant 735# indices. Up through GLSL ES 3.10, the image index source may only be a 736# constant array access. GLSL ES 3.20 and GLSL 4.00 allow dynamically uniform 737# indexing. 738# 739# All image intrinsics take a four-coordinate vector and a sample index as 740# 2nd and 3rd sources, determining the location within the image that will be 741# accessed by the intrinsic. Components not applicable to the image target 742# in use are undefined. Image store takes an additional four-component 743# argument with the value to be written, and image atomic operations take 744# either one or two additional scalar arguments with the same meaning as in 745# the ARB_shader_image_load_store specification. 746# 747# The last source of many image intrinsics is the LOD. This source is zero 748# unless e.g. SPV_AMD_shader_image_load_store_lod is supported. 749def image(name, src_comp=[], extra_indices=[], **kwargs): 750 intrinsic("image_deref_" + name, src_comp=[-1] + src_comp, 751 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) 752 intrinsic("image_" + name, src_comp=[1] + src_comp, 753 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS, RANGE_BASE] + extra_indices, **kwargs) 754 intrinsic("bindless_image_" + name, src_comp=[-1] + src_comp, 755 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) 756 757image("load", src_comp=[4, 1, 1], extra_indices=[DEST_TYPE], dest_comp=0, flags=[CAN_ELIMINATE]) 758image("sparse_load", src_comp=[4, 1, 1], extra_indices=[DEST_TYPE], dest_comp=0, flags=[CAN_ELIMINATE]) 759image("store", src_comp=[4, 1, 0, 1], extra_indices=[SRC_TYPE]) 760image("atomic", src_comp=[4, 1, 1], dest_comp=1, extra_indices=[ATOMIC_OP]) 761image("atomic_swap", src_comp=[4, 1, 1, 1], dest_comp=1, extra_indices=[ATOMIC_OP]) 762image("size", dest_comp=0, src_comp=[1], flags=[CAN_ELIMINATE, CAN_REORDER]) 763image("levels", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 764image("samples", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 765image("texel_address", dest_comp=1, src_comp=[4, 1], 766 flags=[CAN_ELIMINATE, CAN_REORDER]) 767# This returns true if all samples within the pixel have equal color values. 768image("samples_identical", dest_comp=1, src_comp=[4], flags=[CAN_ELIMINATE]) 769# Non-uniform access is not lowered for image_descriptor_amd. 770# dest_comp can be either 4 (buffer) or 8 (image). 771image("descriptor_amd", dest_comp=0, src_comp=[], flags=[CAN_ELIMINATE, CAN_REORDER]) 772# CL-specific format queries 773image("format", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 774image("order", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 775# Multisample fragment mask load 776# src_comp[0] is same as image load src_comp[0] 777image("fragment_mask_load_amd", src_comp=[4], dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 778 779# Vulkan descriptor set intrinsics 780# 781# The Vulkan API uses a different binding model from GL. In the Vulkan 782# API, all external resources are represented by a tuple: 783# 784# (descriptor set, binding, array index) 785# 786# where the array index is the only thing allowed to be indirect. The 787# vulkan_surface_index intrinsic takes the descriptor set and binding as 788# its first two indices and the array index as its source. The third 789# index is a nir_variable_mode in case that's useful to the backend. 790# 791# The intended usage is that the shader will call vulkan_surface_index to 792# get an index and then pass that as the buffer index ubo/ssbo calls. 793# 794# The vulkan_resource_reindex intrinsic takes a resource index in src0 795# (the result of a vulkan_resource_index or vulkan_resource_reindex) which 796# corresponds to the tuple (set, binding, index) and computes an index 797# corresponding to tuple (set, binding, idx + src1). 798intrinsic("vulkan_resource_index", src_comp=[1], dest_comp=0, 799 indices=[DESC_SET, BINDING, DESC_TYPE], 800 flags=[CAN_ELIMINATE, CAN_REORDER]) 801intrinsic("vulkan_resource_reindex", src_comp=[0, 1], dest_comp=0, 802 indices=[DESC_TYPE], flags=[CAN_ELIMINATE, CAN_REORDER]) 803intrinsic("load_vulkan_descriptor", src_comp=[-1], dest_comp=0, 804 indices=[DESC_TYPE], flags=[CAN_ELIMINATE, CAN_REORDER]) 805 806# atomic intrinsics 807# 808# All of these atomic memory operations read a value from memory, compute a new 809# value using one of the operations below, write the new value to memory, and 810# return the original value read. 811# 812# All variable operations take 2 sources except CompSwap that takes 3. These 813# sources represent: 814# 815# 0: A deref to the memory on which to perform the atomic 816# 1: The data parameter to the atomic function (i.e. the value to add 817# in shared_atomic_add, etc). 818# 2: For CompSwap only: the second data parameter. 819# 820# All SSBO operations take 3 sources except CompSwap that takes 4. These 821# sources represent: 822# 823# 0: The SSBO buffer index (dynamically uniform in GLSL, possibly non-uniform 824# with VK_EXT_descriptor_indexing). 825# 1: The offset into the SSBO buffer of the variable that the atomic 826# operation will operate on. 827# 2: The data parameter to the atomic function (i.e. the value to add 828# in ssbo_atomic_add, etc). 829# 3: For CompSwap only: the second data parameter. 830# 831# All shared (and task payload) variable operations take 2 sources 832# except CompSwap that takes 3. 833# These sources represent: 834# 835# 0: The offset into the shared variable storage region that the atomic 836# operation will operate on. 837# 1: The data parameter to the atomic function (i.e. the value to add 838# in shared_atomic_add, etc). 839# 2: For CompSwap only: the second data parameter. 840# 841# All global operations take 2 sources except CompSwap that takes 3. These 842# sources represent: 843# 844# 0: The memory address that the atomic operation will operate on. 845# 1: The data parameter to the atomic function (i.e. the value to add 846# in shared_atomic_add, etc). 847# 2: For CompSwap only: the second data parameter. 848# 849# The 2x32 global variants use a vec2 for the memory address where component X 850# has the low 32-bit and component Y has the high 32-bit. 851# 852# IR3 global operations take 32b vec2 as memory address. IR3 doesn't support 853# float atomics. 854# 855# AGX global variants take a 64-bit base address plus a 32-bit offset in words. 856# The offset is sign-extended or zero-extended based on the SIGN_EXTEND index. 857 858intrinsic("deref_atomic", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS, ATOMIC_OP]) 859intrinsic("ssbo_atomic", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS, ATOMIC_OP]) 860intrinsic("shared_atomic", src_comp=[1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 861intrinsic("task_payload_atomic", src_comp=[1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 862intrinsic("global_atomic", src_comp=[1, 1], dest_comp=1, indices=[ATOMIC_OP]) 863intrinsic("global_atomic_2x32", src_comp=[2, 1], dest_comp=1, indices=[ATOMIC_OP]) 864intrinsic("global_atomic_amd", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 865intrinsic("global_atomic_ir3", src_comp=[2, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 866intrinsic("global_atomic_agx", src_comp=[1, 1, 1], dest_comp=1, indices=[ATOMIC_OP, SIGN_EXTEND]) 867 868intrinsic("deref_atomic_swap", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS, ATOMIC_OP]) 869intrinsic("ssbo_atomic_swap", src_comp=[-1, 1, 1, 1], dest_comp=1, indices=[ACCESS, ATOMIC_OP]) 870intrinsic("shared_atomic_swap", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 871intrinsic("task_payload_atomic_swap", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 872intrinsic("global_atomic_swap", src_comp=[1, 1, 1], dest_comp=1, indices=[ATOMIC_OP]) 873intrinsic("global_atomic_swap_2x32", src_comp=[2, 1, 1], dest_comp=1, indices=[ATOMIC_OP]) 874intrinsic("global_atomic_swap_amd", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 875intrinsic("global_atomic_swap_ir3", src_comp=[2, 1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 876intrinsic("global_atomic_swap_agx", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ATOMIC_OP, SIGN_EXTEND]) 877 878def system_value(name, dest_comp, indices=[], bit_sizes=[32], can_reorder=True): 879 flags = [CAN_ELIMINATE, CAN_REORDER] if can_reorder else [CAN_ELIMINATE] 880 intrinsic("load_" + name, [], dest_comp, indices, 881 flags=flags, sysval=True, 882 bit_sizes=bit_sizes) 883 884system_value("frag_coord", 4) 885# 16-bit integer vec2 of the pixel X/Y in the framebuffer. 886system_value("pixel_coord", 2, bit_sizes=[16]) 887# Scalar load of frag_coord Z/W components (component=2 for Z, component=3 for 888# W). Backends can lower frag_coord to pixel_coord + frag_coord_zw, in case 889# X/Y is available as an integer but Z/W requires interpolation. 890system_value("frag_coord_zw", 1, indices=[COMPONENT]) 891system_value("point_coord", 2) 892system_value("line_coord", 1) 893system_value("front_face", 1, bit_sizes=[1, 32]) 894system_value("front_face_fsign", 1, bit_sizes=[32]) # front_face ? 1.0 : -1.0 895system_value("vertex_id", 1) 896system_value("vertex_id_zero_base", 1) 897system_value("first_vertex", 1) 898system_value("is_indexed_draw", 1) 899system_value("base_vertex", 1) 900system_value("instance_id", 1) 901system_value("base_instance", 1) 902system_value("draw_id", 1) 903system_value("sample_id", 1) 904# sample_id_no_per_sample is like sample_id but does not imply per- 905# sample shading. See the lower_helper_invocation option. 906system_value("sample_id_no_per_sample", 1) 907system_value("sample_pos", 2) 908# sample_pos_or_center is like sample_pos but does not imply per-sample 909# shading. When per-sample dispatch is not enabled, it returns (0.5, 0.5). 910system_value("sample_pos_or_center", 2) 911system_value("sample_mask_in", 1) 912system_value("primitive_id", 1) 913system_value("invocation_id", 1) 914system_value("tess_coord", 3) 915# First 2 components of tess_coord only 916system_value("tess_coord_xy", 2) 917system_value("tess_level_outer", 4) 918system_value("tess_level_inner", 2) 919system_value("tess_level_outer_default", 4) 920system_value("tess_level_inner_default", 2) 921system_value("patch_vertices_in", 1) 922system_value("local_invocation_id", 3) 923system_value("local_invocation_index", 1) 924# workgroup_id does not include the base_workgroup_id 925system_value("workgroup_id", 3) 926# The workgroup_index is intended for situations when a 3 dimensional 927# workgroup_id is not available on the HW, but a 1 dimensional index is. 928system_value("workgroup_index", 1) 929# API specific base added to the workgroup_id, e.g. baseGroup* of vkCmdDispatchBase 930system_value("base_workgroup_id", 3, bit_sizes=[32, 64]) 931system_value("user_clip_plane", 4, indices=[UCP_ID]) 932system_value("num_workgroups", 3) 933system_value("num_vertices", 1) 934# This can't be reordered because it's undefined after an invocation is demoted. 935system_value("helper_invocation", 1, bit_sizes=[1, 32], can_reorder=False) 936system_value("layer_id", 1) 937system_value("view_index", 1) 938system_value("subgroup_size", 1) 939system_value("subgroup_invocation", 1) 940 941# These intrinsics provide a bitmask for all invocations, with one bit per 942# invocation starting with the least significant bit, according to the 943# following table, 944# 945# variable equation for bit values 946# ---------------- -------------------------------- 947# subgroup_eq_mask bit index == subgroup_invocation 948# subgroup_ge_mask bit index >= subgroup_invocation 949# subgroup_gt_mask bit index > subgroup_invocation 950# subgroup_le_mask bit index <= subgroup_invocation 951# subgroup_lt_mask bit index < subgroup_invocation 952# 953# These correspond to gl_SubGroupEqMaskARB, etc. from GL_ARB_shader_ballot, 954# and the above documentation is "borrowed" from that extension spec. 955system_value("subgroup_eq_mask", 0, bit_sizes=[32, 64]) 956system_value("subgroup_ge_mask", 0, bit_sizes=[32, 64]) 957system_value("subgroup_gt_mask", 0, bit_sizes=[32, 64]) 958system_value("subgroup_le_mask", 0, bit_sizes=[32, 64]) 959system_value("subgroup_lt_mask", 0, bit_sizes=[32, 64]) 960 961system_value("num_subgroups", 1) 962system_value("subgroup_id", 1) 963system_value("workgroup_size", 3) 964# note: the definition of global_invocation_id is based on 965# ((workgroup_id + base_workgroup_id) * workgroup_size) + local_invocation_id. 966system_value("global_invocation_id", 3, bit_sizes=[32, 64]) 967# API specific base added to the global_invocation_id 968# e.g. global_work_offset of clEnqueueNDRangeKernel 969system_value("base_global_invocation_id", 3, bit_sizes=[32, 64]) 970system_value("global_invocation_index", 1, bit_sizes=[32, 64]) 971# threads per dimension in an invocation 972system_value("global_size", 3, bit_sizes=[32, 64]) 973system_value("work_dim", 1) 974system_value("line_width", 1) 975system_value("aa_line_width", 1) 976# BASE=0 for global/shader, BASE=1 for local/function 977system_value("scratch_base_ptr", 0, bit_sizes=[32,64], indices=[BASE]) 978system_value("constant_base_ptr", 0, bit_sizes=[32,64]) 979system_value("shared_base_ptr", 0, bit_sizes=[32,64]) 980system_value("global_base_ptr", 0, bit_sizes=[32,64]) 981# Address and size of a transform feedback buffer, indexed by BASE 982system_value("xfb_address", 1, bit_sizes=[32,64], indices=[BASE]) 983system_value("xfb_size", 1, bit_sizes=[32], indices=[BASE]) 984 985# Address of the associated index buffer in a transform feedback program for an 986# indexed draw. This will be used so transform feedback can pull the gl_VertexID 987# from the index buffer. 988system_value("xfb_index_buffer", 1, bit_sizes=[32,64]) 989 990system_value("frag_size", 2) 991system_value("frag_invocation_count", 1) 992# Whether smooth lines or polygon smoothing is enabled 993system_value("poly_line_smooth_enabled", 1, bit_sizes=[1]) 994 995# System values for ray tracing. 996system_value("ray_launch_id", 3) 997system_value("ray_launch_size", 3) 998system_value("ray_world_origin", 3) 999system_value("ray_world_direction", 3) 1000system_value("ray_object_origin", 3) 1001system_value("ray_object_direction", 3) 1002system_value("ray_t_min", 1) 1003system_value("ray_t_max", 1) 1004system_value("ray_object_to_world", 3, indices=[COLUMN]) 1005system_value("ray_world_to_object", 3, indices=[COLUMN]) 1006system_value("ray_hit_kind", 1) 1007system_value("ray_flags", 1) 1008system_value("ray_geometry_index", 1) 1009system_value("ray_instance_custom_index", 1) 1010system_value("shader_record_ptr", 1, bit_sizes=[64]) 1011system_value("cull_mask", 1) 1012system_value("ray_triangle_vertex_positions", 3, indices=[COLUMN]) 1013 1014# Driver-specific viewport scale/offset parameters. 1015# 1016# VC4 and V3D need to emit a scaled version of the position in the vertex 1017# shaders for binning, and having system values lets us move the math for that 1018# into NIR. 1019# 1020# Panfrost needs to implement all coordinate transformation in the 1021# vertex shader; system values allow us to share this routine in NIR. 1022system_value("viewport_x_scale", 1) 1023system_value("viewport_y_scale", 1) 1024system_value("viewport_z_scale", 1) 1025system_value("viewport_x_offset", 1) 1026system_value("viewport_y_offset", 1) 1027system_value("viewport_z_offset", 1) 1028system_value("viewport_scale", 3) 1029system_value("viewport_offset", 3) 1030# Pack xy scale and offset into a vec4 load (used by AMD NGG primitive culling) 1031system_value("cull_triangle_viewport_xy_scale_and_offset_amd", 4) 1032system_value("cull_line_viewport_xy_scale_and_offset_amd", 4) 1033 1034# Blend constant color values. Float values are clamped. Vectored versions are 1035# provided as well for driver convenience 1036 1037system_value("blend_const_color_r_float", 1) 1038system_value("blend_const_color_g_float", 1) 1039system_value("blend_const_color_b_float", 1) 1040system_value("blend_const_color_a_float", 1) 1041system_value("blend_const_color_rgba", 4) 1042system_value("blend_const_color_rgba8888_unorm", 1) 1043system_value("blend_const_color_aaaa8888_unorm", 1) 1044 1045# System values for gl_Color, for radeonsi which interpolates these in the 1046# shader prolog to handle two-sided color without recompiles and therefore 1047# doesn't handle these in the main shader part like normal varyings. 1048system_value("color0", 4) 1049system_value("color1", 4) 1050 1051# System value for internal compute shaders in radeonsi. 1052system_value("user_data_amd", 8) 1053 1054# In a fragment shader, the current sample mask. At the beginning of the shader, 1055# this is the same as load_sample_mask_in, but as the shader is executed, it may 1056# be affected by writes, discards, etc. 1057# 1058# No frontend generates this, but drivers may use it for internal lowerings. 1059intrinsic("load_sample_mask", [], 1, [], flags=[CAN_ELIMINATE], sysval=True, 1060 bit_sizes=[32]) 1061 1062# Barycentric coordinate intrinsics. 1063# 1064# These set up the barycentric coordinates for a particular interpolation. 1065# The first four are for the simple cases: pixel, centroid, per-sample 1066# (at gl_SampleID), or pull model (1/W, 1/I, 1/J) at the pixel center. The next 1067# two handle interpolating at a specified sample location, or interpolating 1068# with a vec2 offset, 1069# 1070# The interp_mode index should be either the INTERP_MODE_SMOOTH or 1071# INTERP_MODE_NOPERSPECTIVE enum values. 1072# 1073# The vec2 value produced by these intrinsics is intended for use as the 1074# barycoord source of a load_interpolated_input intrinsic. 1075# 1076# The vec3 variants are intended to be used for input barycentric coordinates 1077# which are system values on most hardware, compared to the vec2 variants which 1078# interpolates input varyings. 1079 1080def barycentric(name, dst_comp, src_comp=[]): 1081 intrinsic("load_barycentric_" + name, src_comp=src_comp, dest_comp=dst_comp, 1082 indices=[INTERP_MODE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1083 1084# no sources. 1085barycentric("pixel", 2) 1086barycentric("coord_pixel", 3) 1087barycentric("centroid", 2) 1088barycentric("coord_centroid", 3) 1089barycentric("sample", 2) 1090barycentric("coord_sample", 3) 1091barycentric("model", 3) 1092# src[] = { sample_id }. 1093barycentric("at_sample", 2, [1]) 1094barycentric("coord_at_sample", 3, [1]) 1095# src[] = { offset.xy }. 1096barycentric("at_offset", 2, [2]) 1097barycentric("at_offset_nv", 2, [1]) 1098barycentric("coord_at_offset", 3, [2]) 1099 1100# Load sample position: 1101# 1102# Takes a sample # and returns a sample position. Used for lowering 1103# interpolateAtSample() to interpolateAtOffset() 1104intrinsic("load_sample_pos_from_id", src_comp=[1], dest_comp=2, 1105 flags=[CAN_ELIMINATE, CAN_REORDER]) 1106 1107intrinsic("load_persp_center_rhw_ir3", dest_comp=1, 1108 flags=[CAN_ELIMINATE, CAN_REORDER]) 1109 1110# Load texture scaling values: 1111# 1112# Takes a sampler # and returns 1/size values for multiplying to normalize 1113# texture coordinates. Used for lowering rect textures. 1114intrinsic("load_texture_scale", src_comp=[1], dest_comp=2, 1115 flags=[CAN_ELIMINATE, CAN_REORDER]) 1116 1117# Gets the texture src. This intrinsic will be lowered once functions have 1118# been inlined and we know if the src is bindless or not. 1119intrinsic("deref_texture_src", src_comp=[1], dest_comp=1, 1120 flags=[CAN_ELIMINATE, CAN_REORDER]) 1121 1122# Fragment shader input interpolation delta intrinsic. 1123# 1124# For hw where fragment shader input interpolation is handled in shader, the 1125# load_fs_input_interp deltas intrinsics can be used to load the input deltas 1126# used for interpolation as follows: 1127# 1128# vec3 iid = load_fs_input_interp_deltas(varying_slot) 1129# vec2 bary = load_barycentric_*(...) 1130# float result = iid.x + iid.y * bary.y + iid.z * bary.x 1131 1132intrinsic("load_fs_input_interp_deltas", src_comp=[1], dest_comp=3, 1133 indices=[BASE, COMPONENT, IO_SEMANTICS], flags=[CAN_ELIMINATE, CAN_REORDER]) 1134 1135# Load operations pull data from some piece of GPU memory. All load 1136# operations operate in terms of offsets into some piece of theoretical 1137# memory. Loads from externally visible memory (UBO and SSBO) simply take a 1138# byte offset as a source. Loads from opaque memory (uniforms, inputs, etc.) 1139# take a base+offset pair where the nir_intrinsic_base() gives the location 1140# of the start of the variable being loaded and and the offset source is a 1141# offset into that variable. 1142# 1143# Uniform load operations have a nir_intrinsic_range() index that specifies the 1144# range (starting at base) of the data from which we are loading. If 1145# range == 0, then the range is unknown. 1146# 1147# UBO load operations have a nir_intrinsic_range_base() and 1148# nir_intrinsic_range() that specify the byte range [range_base, 1149# range_base+range] of the UBO that the src offset access must lie within. 1150# 1151# Some load operations such as UBO/SSBO load and per_vertex loads take an 1152# additional source to specify which UBO/SSBO/vertex to load from. 1153# 1154# The exact address type depends on the lowering pass that generates the 1155# load/store intrinsics. Typically, this is vec4 units for things such as 1156# varying slots and float units for fragment shader inputs. UBO and SSBO 1157# offsets are always in bytes. 1158 1159def load(name, src_comp, indices=[], flags=[]): 1160 intrinsic("load_" + name, src_comp, dest_comp=0, indices=indices, 1161 flags=flags) 1162 1163# src[] = { offset }. 1164load("uniform", [1], [BASE, RANGE, DEST_TYPE], [CAN_ELIMINATE, CAN_REORDER]) 1165# src[] = { buffer_index, offset }. 1166load("ubo", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET, RANGE_BASE, RANGE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1167# src[] = { buffer_index, offset in vec4 units }. base is also in vec4 units. 1168load("ubo_vec4", [-1, 1], [ACCESS, BASE, COMPONENT], flags=[CAN_ELIMINATE, CAN_REORDER]) 1169# src[] = { offset }. 1170load("input", [1], [BASE, RANGE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1171# src[] = { vertex_id, offset }. 1172load("input_vertex", [1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1173# src[] = { vertex, offset }. 1174load("per_vertex_input", [1, 1], [BASE, RANGE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1175# src[] = { barycoord, offset }. 1176load("interpolated_input", [2, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1177# src[] = { offset }. 1178load("per_primitive_input", [1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1179 1180# src[] = { buffer_index, offset }. 1181load("ssbo", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1182# src[] = { buffer_index, offset } 1183load("ssbo_address", [1, 1], [], [CAN_ELIMINATE, CAN_REORDER]) 1184# src[] = { offset }. 1185load("output", [1], [BASE, RANGE, COMPONENT, DEST_TYPE, IO_SEMANTICS], flags=[CAN_ELIMINATE]) 1186# src[] = { vertex, offset }. 1187load("per_vertex_output", [1, 1], [BASE, RANGE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE]) 1188# src[] = { view_index, offset }. 1189# when nir_shader_compiler_options::compact_view_index is set, the view_index 1190# src refers to the Nth enabled view, and do not correspond directly to 1191# gl_ViewIndex. See the compact_view_index docs for more details. 1192load("per_view_output", [1, 1], [BASE, RANGE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE]) 1193# src[] = { primitive, offset }. 1194load("per_primitive_output", [1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE]) 1195# src[] = { offset }. 1196load("shared", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1197# src[] = { offset }. 1198load("task_payload", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1199# src[] = { offset }. 1200load("push_constant", [1], [BASE, RANGE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE, CAN_REORDER]) 1201# src[] = { offset }. 1202load("constant", [1], [BASE, RANGE, ACCESS, ALIGN_MUL, ALIGN_OFFSET], 1203 [CAN_ELIMINATE, CAN_REORDER]) 1204# src[] = { address }. 1205load("global", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1206# src[] = { address }. 1207load("global_2x32", [2], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1208# src[] = { address }. 1209load("global_constant", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], 1210 [CAN_ELIMINATE, CAN_REORDER]) 1211# src[] = { base_address, offset }. 1212load("global_constant_offset", [1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], 1213 [CAN_ELIMINATE, CAN_REORDER]) 1214# src[] = { base_address, offset, bound }. 1215load("global_constant_bounded", [1, 1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], 1216 [CAN_ELIMINATE, CAN_REORDER]) 1217# src[] = { address }. 1218load("kernel_input", [1], [BASE, RANGE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE, CAN_REORDER]) 1219# src[] = { offset }. 1220load("scratch", [1], [ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1221 1222# Stores work the same way as loads, except now the first source is the value 1223# to store and the second (and possibly third) source specify where to store 1224# the value. SSBO and shared memory stores also have a 1225# nir_intrinsic_write_mask() 1226 1227def store(name, srcs, indices=[], flags=[]): 1228 intrinsic("store_" + name, [0] + srcs, indices=indices, flags=flags) 1229 1230# src[] = { value, offset }. 1231store("output", [1], [BASE, RANGE, WRITE_MASK, COMPONENT, SRC_TYPE, IO_SEMANTICS, IO_XFB, IO_XFB2]) 1232# src[] = { value, vertex, offset }. 1233store("per_vertex_output", [1, 1], [BASE, RANGE, WRITE_MASK, COMPONENT, SRC_TYPE, IO_SEMANTICS]) 1234# src[] = { value, view_index, offset }. 1235store("per_view_output", [1, 1], [BASE, RANGE, WRITE_MASK, COMPONENT, SRC_TYPE, IO_SEMANTICS]) 1236# src[] = { value, primitive, offset }. 1237store("per_primitive_output", [1, 1], [BASE, RANGE, WRITE_MASK, COMPONENT, SRC_TYPE, IO_SEMANTICS]) 1238# src[] = { value, block_index, offset } 1239store("ssbo", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1240# src[] = { value, offset }. 1241store("shared", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) 1242# src[] = { value, offset }. 1243store("task_payload", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) 1244# src[] = { value, address }. 1245store("global", [1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1246# src[] = { value, address }. 1247store("global_2x32", [2], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1248# src[] = { value, offset }. 1249store("scratch", [1], [ALIGN_MUL, ALIGN_OFFSET, WRITE_MASK]) 1250 1251# Intrinsic to load/store from the call stack. 1252# BASE is the offset relative to the current position of the stack 1253# src[] = { }. 1254intrinsic("load_stack", [], dest_comp=0, 1255 indices=[BASE, ALIGN_MUL, ALIGN_OFFSET, CALL_IDX, VALUE_ID], 1256 flags=[CAN_ELIMINATE]) 1257# src[] = { value }. 1258intrinsic("store_stack", [0], 1259 indices=[BASE, ALIGN_MUL, ALIGN_OFFSET, WRITE_MASK, CALL_IDX, VALUE_ID]) 1260 1261 1262# A bit field to implement SPIRV FragmentShadingRateKHR 1263# bit | name | description 1264# 0 | Vertical2Pixels | Fragment invocation covers 2 pixels vertically 1265# 1 | Vertical4Pixels | Fragment invocation covers 4 pixels vertically 1266# 2 | Horizontal2Pixels | Fragment invocation covers 2 pixels horizontally 1267# 3 | Horizontal4Pixels | Fragment invocation covers 4 pixels horizontally 1268intrinsic("load_frag_shading_rate", dest_comp=1, bit_sizes=[32], 1269 flags=[CAN_ELIMINATE, CAN_REORDER]) 1270 1271# Whether the rasterized fragment is fully covered by the generating primitive. 1272system_value("fully_covered", dest_comp=1, bit_sizes=[1]) 1273 1274# OpenCL printf instruction 1275# First source is an index to the format string (u_printf_info element of the shader) 1276# Second source is a deref to a struct containing the args 1277# Dest is success or failure 1278intrinsic("printf", src_comp=[1, 1], dest_comp=1, bit_sizes=[32]) 1279# Since most drivers will want to lower to just dumping args 1280# in a buffer, nir_lower_printf will do that, but requires 1281# the driver to at least provide a base location and size 1282system_value("printf_buffer_address", 1, bit_sizes=[32,64]) 1283system_value("printf_buffer_size", 1, bit_sizes=[32]) 1284# If driver wants to have all printfs from various shaders merged into a 1285# single output buffer, it needs each shader to have its own base identifier 1286# from which each printf is indexed. 1287system_value("printf_base_identifier", 1, bit_sizes=[32]) 1288# Abort the program, triggering device fault. The invoking thread halts 1289# immediately. Other threads eventually terminate. 1290# 1291# This does not take a payload, payloads should be specified with a preceding 1292# printf. After lowering, the intrinsic will set an aborted? bit in the printf 1293# buffer. This avoids a separate abort buffer. 1294intrinsic("printf_abort") 1295 1296# Mesh shading MultiView intrinsics 1297system_value("mesh_view_count", 1) 1298load("mesh_view_indices", [1], [BASE, RANGE], [CAN_ELIMINATE, CAN_REORDER]) 1299 1300# Used to pass values from the preamble to the main shader. 1301# This should use something similar to Vulkan push constants and load_preamble 1302# should be relatively cheap. 1303# For now we only support accesses with a constant offset. 1304load("preamble", [], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1305store("preamble", [], indices=[BASE]) 1306 1307# A 64-bit bitfield indexed by I/O location storing 1 in bits corresponding to 1308# varyings that have the flat interpolation specifier in the fragment shader and 1309# 0 otherwise 1310system_value("flat_mask", 1, bit_sizes=[64]) 1311 1312# Whether provoking vertex mode is last 1313system_value("provoking_last", 1) 1314 1315# SPV_KHR_cooperative_matrix. 1316# 1317# Cooperative matrices are referred through derefs to variables, 1318# the destination of the operations appears as the first source, 1319# ordering follows SPIR-V operation. 1320# 1321# Load/Store include an extra source for stride, since that 1322# can be a _dynamically_ uniform value. 1323# 1324# Length takes a type not a value, that's encoded as a MATRIX_DESC. 1325intrinsic("cmat_construct", src_comp=[-1, 1]) 1326intrinsic("cmat_load", src_comp=[-1, -1, 1], indices=[MATRIX_LAYOUT]) 1327intrinsic("cmat_store", src_comp=[-1, -1, 1], indices=[MATRIX_LAYOUT]) 1328intrinsic("cmat_length", src_comp=[], dest_comp=1, indices=[CMAT_DESC], bit_sizes=[32]) 1329intrinsic("cmat_muladd", src_comp=[-1, -1, -1, -1], indices=[SATURATE, CMAT_SIGNED_MASK]) 1330intrinsic("cmat_unary_op", src_comp=[-1, -1], indices=[ALU_OP]) 1331intrinsic("cmat_binary_op", src_comp=[-1, -1, -1], indices=[ALU_OP]) 1332intrinsic("cmat_scalar_op", src_comp=[-1, -1, -1], indices=[ALU_OP]) 1333intrinsic("cmat_bitcast", src_comp=[-1, -1]) 1334intrinsic("cmat_extract", src_comp=[-1, 1], dest_comp=1) 1335intrinsic("cmat_insert", src_comp=[-1, 1, -1, 1]) 1336intrinsic("cmat_copy", src_comp=[-1, -1]) 1337 1338# IR3-specific version of most SSBO intrinsics. The only different 1339# compare to the originals is that they add an extra source to hold 1340# the dword-offset, which is needed by the backend code apart from 1341# the byte-offset already provided by NIR in one of the sources. 1342# 1343# NIR lowering pass 'ir3_nir_lower_io_offset' will replace the 1344# original SSBO intrinsics by these, placing the computed 1345# dword-offset always in the last source. 1346# 1347# The float versions are not handled because those are not supported 1348# by the backend. 1349store("ssbo_ir3", [1, 1, 1], 1350 indices=[BASE, WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1351load("ssbo_ir3", [1, 1, 1], 1352 indices=[BASE, ACCESS, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) 1353intrinsic("ssbo_atomic_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, 1354 indices=[ACCESS, ATOMIC_OP]) 1355intrinsic("ssbo_atomic_swap_ir3", src_comp=[1, 1, 1, 1, 1], dest_comp=1, 1356 indices=[ACCESS, ATOMIC_OP]) 1357 1358# System values for freedreno geometry shaders. 1359system_value("vs_primitive_stride_ir3", 1) 1360system_value("vs_vertex_stride_ir3", 1) 1361system_value("gs_header_ir3", 1) 1362system_value("primitive_location_ir3", 1, indices=[DRIVER_LOCATION]) 1363 1364# System values for freedreno tessellation shaders. 1365system_value("hs_patch_stride_ir3", 1) 1366system_value("tess_factor_base_ir3", 2) 1367system_value("tess_param_base_ir3", 2) 1368system_value("tcs_header_ir3", 1) 1369system_value("rel_patch_id_ir3", 1) 1370 1371# System values for freedreno compute shaders. 1372system_value("subgroup_id_shift_ir3", 1) 1373 1374# System values for freedreno fragment shaders. 1375intrinsic("load_frag_coord_unscaled_ir3", dest_comp=4, 1376 flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[32]) 1377 1378# Per-view gl_FragSizeEXT and gl_FragCoord offset. 1379intrinsic("load_frag_size_ir3", src_comp=[1], dest_comp=2, indices=[RANGE], 1380 flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[32]) 1381intrinsic("load_frag_offset_ir3", src_comp=[1], dest_comp=2, indices=[RANGE], 1382 flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[32]) 1383 1384# IR3-specific load/store intrinsics. These access a buffer used to pass data 1385# between geometry stages - perhaps it's explicit access to the vertex cache. 1386 1387# src[] = { value, offset }. 1388store("shared_ir3", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET]) 1389# src[] = { offset }. 1390load("shared_ir3", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1391 1392# IR3-specific load/store global intrinsics. They take a 64-bit base address 1393# and a 32-bit offset. The hardware will add the base and the offset, which 1394# saves us from doing 64-bit math on the base address. 1395 1396# src[] = { value, address(vec2 of hi+lo uint32_t), offset }. 1397# const_index[] = { write_mask, align_mul, align_offset } 1398store("global_ir3", [2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1399# src[] = { address(vec2 of hi+lo uint32_t), offset }. 1400# const_index[] = { access, align_mul, align_offset } 1401# the alignment applies to the base address 1402load("global_ir3", [2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET, RANGE_BASE, RANGE], flags=[CAN_ELIMINATE]) 1403 1404# Etnaviv-specific load/glboal intrinsics. They take a 32-bit base address and 1405# a 32-bit offset, which doesn't need to be an immediate. 1406# src[] = { value, address, 32-bit offset }. 1407store("global_etna", [1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1408# src[] = { address, 32-bit offset }. 1409load("global_etna", [1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1410 1411# IR3-specific bindless handle specifier. Similar to vulkan_resource_index, but 1412# without the binding because the hardware expects a single flattened index 1413# rather than a (binding, index) pair. We may also want to use this with GL. 1414# Note that this doesn't actually turn into a HW instruction. 1415intrinsic("bindless_resource_ir3", [1], dest_comp=1, indices=[DESC_SET], flags=[CAN_ELIMINATE, CAN_REORDER]) 1416 1417# IR3-specific intrinsics for shader preamble. These are meant to be used like 1418# this: 1419# 1420# if (preamble_start()) { 1421# if (subgroupElect()) { 1422# // preamble 1423# ... 1424# preamble_end(); 1425# } 1426# } 1427# // main shader 1428# ... 1429 1430intrinsic("preamble_start_ir3", [], dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 1431 1432barrier("preamble_end_ir3") 1433 1434# IR3-specific intrinsic to choose any invocation. This is implemented the same 1435# as elect, except that it doesn't require helper invocations. Used by preambles. 1436intrinsic("elect_any_ir3", dest_comp=1, flags=[CAN_ELIMINATE]) 1437 1438# IR3-specific intrinsic for stc. Should be used in the shader preamble. 1439store("const_ir3", [], indices=[BASE]) 1440 1441# IR3-specific intrinsic for loading from a const reg. 1442load("const_ir3", [1], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1443 1444# IR3-specific intrinsic for ldc.k. Copies UBO to constant file. 1445# base is the const file base in components, range is the amount to copy in 1446# vec4's. 1447intrinsic("copy_ubo_to_uniform_ir3", [1, 1], indices=[BASE, RANGE]) 1448 1449# IR3-specific intrinsic for ldg.k. 1450# base is an offset to apply to the address in bytes, range_base is the 1451# const file base in components, range is the amount to copy in vec4's. 1452intrinsic("copy_global_to_uniform_ir3", [2], indices=[BASE, RANGE_BASE, RANGE]) 1453 1454# IR3-specific intrinsic for stsc. Loads from push consts to constant file 1455# Should be used in the shader preamble. 1456intrinsic("copy_push_const_to_uniform_ir3", [1], indices=[BASE, RANGE]) 1457 1458intrinsic("brcst_active_ir3", dest_comp=1, src_comp=[1, 1], bit_sizes=src0, 1459 indices=[CLUSTER_SIZE]) 1460intrinsic("reduce_clusters_ir3", dest_comp=1, src_comp=[1], bit_sizes=src0, 1461 indices=[REDUCTION_OP]) 1462intrinsic("inclusive_scan_clusters_ir3", dest_comp=1, src_comp=[1], 1463 bit_sizes=src0, indices=[REDUCTION_OP]) 1464intrinsic("exclusive_scan_clusters_ir3", dest_comp=1, src_comp=[1, 1], 1465 bit_sizes=src0, indices=[REDUCTION_OP]) 1466 1467# Like shuffle_{xor,up,down} except with a uniform index. Necessary since the 1468# ir3 shfl instruction doesn't work with divergent indices. 1469intrinsic("shuffle_xor_uniform_ir3", src_comp=[0, 1], dest_comp=0, 1470 bit_sizes=src0, flags=[CAN_ELIMINATE]) 1471intrinsic("shuffle_up_uniform_ir3", src_comp=[0, 1], dest_comp=0, 1472 bit_sizes=src0, flags=[CAN_ELIMINATE]) 1473intrinsic("shuffle_down_uniform_ir3", src_comp=[0, 1], dest_comp=0, 1474 bit_sizes=src0, flags=[CAN_ELIMINATE]) 1475 1476# IR3-specific intrinsics for prefetching descriptors in preambles. 1477intrinsic("prefetch_sam_ir3", [1, 1], flags=[CAN_REORDER]) 1478intrinsic("prefetch_tex_ir3", [1], flags=[CAN_REORDER]) 1479intrinsic("prefetch_ubo_ir3", [1], flags=[CAN_REORDER]) 1480 1481# Panfrost-specific intrinsic for loading vertex attributes. Takes explicit 1482# vertex and instance IDs which we need in order to implement vertex attribute 1483# divisor with non-zero base instance on v9+. 1484# src[] = { vertex_id, instance_id, offset } 1485load("attribute_pan", [1, 1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1486 1487# Panfrost-specific intrinsics for accessing the raw vertex ID and the 1488# associated offset such that 1489# vertex_id = raw_vertex_id_pan + raw_vertex_offset_pan 1490# The raw vertex ID differs from the zero-based vertex ID in that, in an index 1491# draw, it is offset by the minimum vertex ID in the index buffer range 1492# covered by the draw 1493system_value("raw_vertex_id_pan", 1) 1494system_value("raw_vertex_offset_pan", 1) 1495 1496# Intrinsics used by the Midgard/Bifrost blend pipeline. These are defined 1497# within a blend shader to read/write the raw value from the tile buffer, 1498# without applying any format conversion in the process. If the shader needs 1499# usable pixel values, it must apply format conversions itself. 1500# 1501# These definitions are generic, but they are explicitly vendored to prevent 1502# other drivers from using them, as their semantics is defined in terms of the 1503# Midgard/Bifrost hardware tile buffer and may not line up with anything sane. 1504# One notable divergence is sRGB, which is asymmetric: raw_input_pan requires 1505# an sRGB->linear conversion, but linear values should be written to 1506# raw_output_pan and the hardware handles linear->sRGB. 1507# 1508# store_raw_output_pan is used only for blend shaders, and writes out only a 1509# single 128-bit chunk. To support multisampling, the BASE index specifies the 1510# bas sample index written out. 1511 1512# src[] = { value } 1513store("raw_output_pan", [], [IO_SEMANTICS, BASE]) 1514store("combined_output_pan", [1, 1, 1, 4], [IO_SEMANTICS, COMPONENT, SRC_TYPE, DEST_TYPE]) 1515load("raw_output_pan", [1], [IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1516 1517# Like the frag_coord_zw intrinsic, but takes a barycentric. This is needed for 1518# noperspective lowering. 1519# src[] = { barycoord } 1520intrinsic("load_frag_coord_zw_pan", [2], dest_comp=1, indices=[COMPONENT], flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[32]) 1521 1522# Loads the sampler paramaters <min_lod, max_lod, lod_bias> 1523# src[] = { sampler_index } 1524load("sampler_lod_parameters_pan", [1], flags=[CAN_ELIMINATE, CAN_REORDER]) 1525 1526# Like load_output but using a specified render target conversion descriptor 1527load("converted_output_pan", [1], indices=[DEST_TYPE, IO_SEMANTICS], flags=[CAN_ELIMINATE]) 1528 1529# Load the render target conversion descriptor for a given render target given 1530# in the BASE index. Converts to a type with size given by the source type. 1531# Valid in fragment and blend stages. 1532system_value("rt_conversion_pan", 1, indices=[BASE, SRC_TYPE], bit_sizes=[32]) 1533 1534# Loads the sample position array on Bifrost, in a packed Arm-specific format 1535system_value("sample_positions_pan", 1, bit_sizes=[64]) 1536 1537# In a fragment shader, is the framebuffer single-sampled? 0/~0 bool 1538system_value("multisampled_pan", 1, bit_sizes=[32]) 1539 1540# In a vertex shader, a bitfield of varying slots that use noperspective 1541# interpolation in the linked fragment shader. Since special slots cannot be 1542# noperspective, this is 32 bits and starts from VARYING_SLOT_VAR0. 1543system_value("noperspective_varyings_pan", 1, bit_sizes=[32]) 1544 1545# R600 specific instrincs 1546# 1547# location where the tesselation data is stored in LDS 1548system_value("tcs_in_param_base_r600", 4) 1549system_value("tcs_out_param_base_r600", 4) 1550system_value("tcs_rel_patch_id_r600", 1) 1551system_value("tcs_tess_factor_base_r600", 1) 1552 1553# load as many components as needed giving per-component addresses 1554intrinsic("load_local_shared_r600", src_comp=[0], dest_comp=0, indices = [], flags = [CAN_ELIMINATE]) 1555 1556store("local_shared_r600", [1], [WRITE_MASK]) 1557store("tf_r600", []) 1558 1559# AMD GCN/RDNA specific intrinsics 1560 1561# This barrier is a hint that prevents moving the instruction that computes 1562# src after this barrier. It's a constraint for the instruction scheduler. 1563# Otherwise it's identical to a move instruction. 1564# The VGPR version forces the src value to be stored in a VGPR, while the SGPR 1565# version enforces an SGPR. 1566intrinsic("optimization_barrier_vgpr_amd", dest_comp=0, src_comp=[0], 1567 flags=[CAN_ELIMINATE]) 1568intrinsic("optimization_barrier_sgpr_amd", dest_comp=0, src_comp=[0], 1569 flags=[CAN_ELIMINATE]) 1570 1571# These are no-op intrinsics used as a simple source and user of SSA defs for testing. 1572intrinsic("unit_test_amd", src_comp=[0], indices=[BASE]) 1573intrinsic("unit_test_uniform_amd", dest_comp=0, indices=[BASE]) 1574intrinsic("unit_test_divergent_amd", dest_comp=0, indices=[BASE]) 1575 1576# Untyped buffer load/store instructions of arbitrary length. 1577# src[] = { descriptor, vector byte offset, scalar byte offset, index offset } 1578# The index offset is multiplied by the stride in the descriptor. 1579# The vector/scalar offsets are in bytes, BASE is a constant byte offset. 1580intrinsic("load_buffer_amd", src_comp=[4, 1, 1, 1], dest_comp=0, indices=[BASE, MEMORY_MODES, ACCESS], flags=[CAN_ELIMINATE]) 1581# src[] = { store value, descriptor, vector byte offset, scalar byte offset, index offset } 1582intrinsic("store_buffer_amd", src_comp=[0, 4, 1, 1, 1], indices=[BASE, WRITE_MASK, MEMORY_MODES, ACCESS]) 1583 1584# Typed buffer load of arbitrary length, using a specified format. 1585# src[] = { descriptor, vector byte offset, scalar byte offset, index offset } 1586# 1587# The compiler backend is responsible for emitting correct HW instructions according to alignment, range etc. 1588# Users of this intrinsic must ensure that the first component being loaded is really the first component 1589# of the specified format, because range analysis assumes this. 1590# The size of the specified format also determines the memory range that this instruction is allowed to access. 1591# 1592# The index offset is multiplied by the stride in the descriptor, if any. 1593# The vector/scalar offsets are in bytes, BASE is a constant byte offset. 1594intrinsic("load_typed_buffer_amd", src_comp=[4, 1, 1, 1], dest_comp=0, indices=[BASE, MEMORY_MODES, ACCESS, FORMAT, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) 1595 1596# src[] = { address, unsigned 32-bit offset }. 1597load("global_amd", [1, 1], indices=[BASE, ACCESS, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) 1598# src[] = { value, address, unsigned 32-bit offset }. 1599store("global_amd", [1, 1], indices=[BASE, ACCESS, ALIGN_MUL, ALIGN_OFFSET, WRITE_MASK]) 1600 1601# Same as shared_atomic_add, but with GDS. src[] = {store_val, gds_addr, m0} 1602intrinsic("gds_atomic_add_amd", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 1603 1604# Optimized shared_atomic_add (1/-1) with constant address 1605# returning the uniform pre-op value for all invocations. 1606intrinsic("shared_append_amd", src_comp=[], dest_comp=1, bit_sizes=[32], indices=[BASE]) 1607intrinsic("shared_consume_amd", src_comp=[], dest_comp=1, bit_sizes=[32], indices=[BASE]) 1608 1609# src[] = { sample_id, num_samples } 1610intrinsic("load_sample_positions_amd", src_comp=[1, 1], dest_comp=2, flags=[CAN_ELIMINATE, CAN_REORDER]) 1611 1612# Descriptor where TCS outputs are stored for TES 1613system_value("ring_tess_offchip_amd", 4) 1614system_value("ring_tess_offchip_offset_amd", 1) 1615# Descriptor where TCS outputs are stored for the HW tessellator 1616system_value("ring_tess_factors_amd", 4) 1617system_value("ring_tess_factors_offset_amd", 1) 1618# Descriptor where ES outputs are stored for GS to read on GFX6-8 1619system_value("ring_esgs_amd", 4) 1620system_value("ring_es2gs_offset_amd", 1) 1621# Address of the task shader draw ring (used for VARYING_SLOT_TASK_COUNT) 1622system_value("ring_task_draw_amd", 4) 1623# Address of the task shader payload ring (used for all other outputs) 1624system_value("ring_task_payload_amd", 4) 1625# Address of the mesh shader scratch ring (used for excess mesh shader outputs) 1626system_value("ring_mesh_scratch_amd", 4) 1627system_value("ring_mesh_scratch_offset_amd", 1) 1628# Pointer into the draw and payload rings 1629system_value("task_ring_entry_amd", 1) 1630# Descriptor where NGG attributes are stored on GFX11. 1631system_value("ring_attr_amd", 4) 1632system_value("ring_attr_offset_amd", 1) 1633 1634# Load provoking vertex info 1635system_value("provoking_vtx_amd", 1) 1636 1637# Load rasterization primitive 1638system_value("rasterization_primitive_amd", 1); 1639 1640# Number of patches processed by each TCS workgroup 1641system_value("tcs_num_patches_amd", 1) 1642# Whether TCS should store tessellation level outputs for TES to read 1643system_value("tcs_tess_levels_to_tes_amd", dest_comp=1, bit_sizes=[1]) 1644# Tessellation primitive mode for TCS 1645system_value("tcs_primitive_mode_amd", 1) 1646# Relative tessellation patch ID within the current workgroup 1647system_value("tess_rel_patch_id_amd", 1) 1648# Vertex offsets used for GS per-vertex inputs 1649system_value("gs_vertex_offset_amd", 1, [BASE]) 1650# Number of rasterization samples 1651system_value("rasterization_samples_amd", 1) 1652 1653# Descriptor where GS outputs are stored for GS copy shader to read on GFX6-9 1654system_value("ring_gsvs_amd", 4, indices=[STREAM_ID]) 1655# Write offset in gsvs ring for legacy GS shader 1656system_value("ring_gs2vs_offset_amd", 1) 1657 1658# Streamout configuration 1659system_value("streamout_config_amd", 1) 1660# Position to write within the streamout buffers 1661system_value("streamout_write_index_amd", 1) 1662# Offset to write within a streamout buffer 1663system_value("streamout_offset_amd", 1, indices=[BASE]) 1664 1665# AMD merged shader intrinsics 1666 1667# Whether the current invocation index in the subgroup is less than the source. The source must be 1668# subgroup uniform and the 8 bits starting at the base bit must be less than or equal to the wave size. 1669intrinsic("is_subgroup_invocation_lt_amd", src_comp=[1], dest_comp=1, bit_sizes=[1], indices=[BASE], flags=[CAN_ELIMINATE]) 1670 1671# AMD NGG intrinsics 1672 1673# Number of initial input vertices in the current workgroup. 1674system_value("workgroup_num_input_vertices_amd", 1) 1675# Number of initial input primitives in the current workgroup. 1676system_value("workgroup_num_input_primitives_amd", 1) 1677# For NGG passthrough mode only. Pre-packed argument for export_primitive_amd. 1678system_value("packed_passthrough_primitive_amd", 1) 1679# Whether NGG should execute shader query for pipeline statistics. 1680system_value("pipeline_stat_query_enabled_amd", dest_comp=1, bit_sizes=[1]) 1681# Whether NGG should execute shader query for primitive generated. 1682system_value("prim_gen_query_enabled_amd", dest_comp=1, bit_sizes=[1]) 1683# Whether NGG should execute shader query for primitive streamouted. 1684system_value("prim_xfb_query_enabled_amd", dest_comp=1, bit_sizes=[1]) 1685# 64-bit memory address to struct {uint32_t ordered_id; uint32_t dwords_written;}[4] 1686system_value("xfb_state_address_gfx12_amd", dest_comp=1, bit_sizes=[64]) 1687# Merged wave info. Bits 0-7 are the ES thread count, 8-15 are the GS thread count, 16-24 is the 1688# GS Wave ID, 24-27 is the wave index in the workgroup, and 28-31 is the workgroup size in waves. 1689system_value("merged_wave_info_amd", dest_comp=1) 1690# Global ID for GS waves on GCN/RDNA legacy GS. 1691system_value("gs_wave_id_amd", dest_comp=1) 1692# Whether the shader should clamp vertex color outputs to [0, 1]. 1693system_value("clamp_vertex_color_amd", dest_comp=1, bit_sizes=[1]) 1694# Whether the shader should cull front facing triangles. 1695intrinsic("load_cull_front_face_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1696# Whether the shader should cull back facing triangles. 1697intrinsic("load_cull_back_face_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1698# True if face culling should use CCW (false if CW). 1699intrinsic("load_cull_ccw_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1700# Whether the shader should cull small triangles that are not visible in a pixel. 1701intrinsic("load_cull_small_triangles_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1702# Whether the shader should cull small lines that are not visible in a pixel. 1703intrinsic("load_cull_small_lines_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1704# Whether any culling setting is enabled in the shader. 1705intrinsic("load_cull_any_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1706# Small triangle culling precision 1707intrinsic("load_cull_small_triangle_precision_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 1708# Small line culling precision 1709intrinsic("load_cull_small_line_precision_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 1710# Initial edge flags in a Vertex Shader, packed into the format the HW needs for primitive export. 1711intrinsic("load_initial_edgeflags_amd", src_comp=[], dest_comp=1, bit_sizes=[32], indices=[]) 1712# Corresponds to s_sendmsg in the GCN/RDNA ISA, src[] = { m0_content }, BASE = imm 1713intrinsic("sendmsg_amd", src_comp=[1], indices=[BASE]) 1714# Overwrites VS input registers, for use with vertex compaction after culling. src = {vertex_id, instance_id}. 1715intrinsic("overwrite_vs_arguments_amd", src_comp=[1, 1], indices=[]) 1716# Overwrites TES input registers, for use with vertex compaction after culling. src = {tes_u, tes_v, rel_patch_id, patch_id}. 1717intrinsic("overwrite_tes_arguments_amd", src_comp=[1, 1, 1, 1], indices=[]) 1718 1719# The address of the sbt descriptors. 1720system_value("sbt_base_amd", 1, bit_sizes=[64]) 1721 1722# 1. HW descriptor 1723# 2. BVH node(64-bit pointer as 2x32 ...) 1724# 3. ray extent 1725# 4. ray origin 1726# 5. ray direction 1727# 6. inverse ray direction (componentwise 1.0/ray direction) 1728intrinsic("bvh64_intersect_ray_amd", [4, 2, 1, 3, 3, 3], 4, flags=[CAN_ELIMINATE, CAN_REORDER]) 1729 1730# Return of a callable in raytracing pipelines 1731intrinsic("rt_return_amd") 1732 1733# offset into scratch for the input callable data in a raytracing pipeline. 1734system_value("rt_arg_scratch_offset_amd", 1) 1735 1736# Whether to call the anyhit shader for an intersection in an intersection shader. 1737system_value("intersection_opaque_amd", 1, bit_sizes=[1]) 1738 1739# pointer to the next resume shader 1740system_value("resume_shader_address_amd", 1, bit_sizes=[64], indices=[CALL_IDX]) 1741 1742# Ray Tracing Traversal inputs 1743system_value("sbt_offset_amd", 1) 1744system_value("sbt_stride_amd", 1) 1745system_value("accel_struct_amd", 1, bit_sizes=[64]) 1746system_value("cull_mask_and_flags_amd", 1) 1747 1748# 0. SBT Index 1749# 1. Ray Tmax 1750# 2. Primitive Id 1751# 3. Instance Addr 1752# 4. Geometry Id and Flags 1753# 5. Hit Kind 1754intrinsic("execute_closest_hit_amd", src_comp=[1, 1, 1, 1, 1, 1]) 1755 1756# 0. Ray Tmax 1757intrinsic("execute_miss_amd", src_comp=[1]) 1758 1759# Used for saving and restoring hit attribute variables. 1760# BASE=dword index 1761intrinsic("load_hit_attrib_amd", dest_comp=1, bit_sizes=[32], indices=[BASE]) 1762intrinsic("store_hit_attrib_amd", src_comp=[1], indices=[BASE]) 1763 1764# Load forced VRS rates. 1765intrinsic("load_force_vrs_rates_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 1766 1767intrinsic("load_scalar_arg_amd", dest_comp=0, bit_sizes=[32], 1768 indices=[BASE, ARG_UPPER_BOUND_U32_AMD], 1769 flags=[CAN_ELIMINATE, CAN_REORDER]) 1770intrinsic("load_vector_arg_amd", dest_comp=0, bit_sizes=[32], 1771 indices=[BASE, ARG_UPPER_BOUND_U32_AMD, FLAGS], 1772 flags=[CAN_ELIMINATE, CAN_REORDER]) 1773store("scalar_arg_amd", [], [BASE]) 1774store("vector_arg_amd", [], [BASE]) 1775 1776# src[] = { 32/64-bit base address, 32-bit offset }. 1777# 1778# Similar to load_global_constant, the memory accessed must be read-only. This 1779# restriction justifies the CAN_REORDER flag. Additionally, the base/offset must 1780# be subgroup uniform. 1781intrinsic("load_smem_amd", src_comp=[1, 1], dest_comp=0, bit_sizes=[32], 1782 indices=[ALIGN_MUL, ALIGN_OFFSET], 1783 flags=[CAN_ELIMINATE, CAN_REORDER]) 1784 1785# src[] = { offset }. 1786intrinsic("load_shared2_amd", [1], dest_comp=2, indices=[OFFSET0, OFFSET1, ST64], flags=[CAN_ELIMINATE]) 1787 1788# src[] = { value, offset }. 1789intrinsic("store_shared2_amd", [2, 1], indices=[OFFSET0, OFFSET1, ST64]) 1790 1791# Vertex stride in LS-HS buffer 1792system_value("lshs_vertex_stride_amd", 1) 1793 1794# Vertex stride in ES-GS buffer 1795system_value("esgs_vertex_stride_amd", 1) 1796 1797# Per patch data offset in HS VRAM output buffer 1798system_value("hs_out_patch_data_offset_amd", 1) 1799 1800# line_width * 0.5 / abs(viewport_scale[2]) 1801system_value("clip_half_line_width_amd", 2) 1802 1803# Number of vertices in a primitive 1804system_value("num_vertices_per_primitive_amd", 1) 1805 1806# Load streamout buffer desc 1807# BASE = buffer index 1808intrinsic("load_streamout_buffer_amd", dest_comp=4, indices=[BASE], bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 1809 1810# An ID for each workgroup ordered by primitve sequence 1811system_value("ordered_id_amd", 1) 1812 1813# Add src1 to global streamout buffer offsets in the specified order. 1814# Only 1 lane must be active. 1815# src[] = { ordered_id, counter } 1816# WRITE_MASK = mask for counter channel to update 1817intrinsic("ordered_xfb_counter_add_gfx11_amd", dest_comp=0, src_comp=[1, 0], indices=[WRITE_MASK], bit_sizes=[32]) 1818 1819# Execute the atomic ordered add loop. This does what ds_ordered_count did in previous generations. 1820# This is implemented with inline assembly to get the most optimal code. 1821# 1822# Inputs: 1823# exec = one lane per counter (use nir_push_if, streamout should always enable 4 lanes) 1824# src[0] = 64-bit SGPR atomic base address (streamout should use nir_load_xfb_state_address_gfx12_amd) 1825# src[1] = 32-bit VGPR voffset (streamout should set local_invocation_index * 8) 1826# src[2] = 32-bit SGPR ordered_id (use nir_load_ordered_id_amd for streamout, compute shaders 1827# should generated it manually) 1828# src[3] = 64-bit VGPR atomic src, use pack_64_2x32_split(ordered_id, value), streamout should do: 1829# pack_64_2x32_split(ordered_id, "dwords written per workgroup" for each buffer) 1830# 1831# dst = 32-bit VGPR of the previous value of 32-bit value in memory, returned for all enabled lanes 1832 1833# Example - streamout: It's used to add dwords_written[] to global streamout offsets. 1834# * Exactly 4 lanes must be active, one for each buffer binding. 1835# * Disabled buffers must set dwords_written=0 for their lane, but the lane 1836# must be enabled. 1837# 1838intrinsic("ordered_add_loop_gfx12_amd", dest_comp=1, src_comp=[1, 1, 1, 1], bit_sizes=[32]) 1839 1840# Subtract from global streamout buffer offsets. Used to fix up the offsets 1841# when we overflow streamout buffers. 1842# src[] = { offsets } 1843# WRITE_MASK = mask of offsets to subtract 1844intrinsic("xfb_counter_sub_gfx11_amd", src_comp=[0], indices=[WRITE_MASK], bit_sizes=[32]) 1845 1846# Provoking vertex index in a primitive 1847system_value("provoking_vtx_in_prim_amd", 1) 1848 1849# Atomically add current wave's primitive count to query result 1850# * GS emitted primitive is primitive emitted by any GS stream 1851# * generated primitive is primitive that has been produced for that stream by VS/TES/GS 1852# * streamout primitve is primitve that has been written to xfb buffer, may be different 1853# than generated primitive when xfb buffer is too small to hold more primitives 1854# src[] = { primitive_count }. 1855intrinsic("atomic_add_gs_emit_prim_count_amd", [1]) 1856intrinsic("atomic_add_gen_prim_count_amd", [1], indices=[STREAM_ID]) 1857intrinsic("atomic_add_xfb_prim_count_amd", [1], indices=[STREAM_ID]) 1858 1859# Atomically add current shader's invocation count to query result 1860# src[] = { invocation_count }. 1861intrinsic("atomic_add_shader_invocation_count_amd", [1]) 1862 1863# LDS offset for scratch section in NGG shader 1864system_value("lds_ngg_scratch_base_amd", 1) 1865# LDS offset for NGG GS shader vertex emit 1866system_value("lds_ngg_gs_out_vertex_base_amd", 1) 1867 1868# AMD GPU shader output export instruction 1869# src[] = { export_value, row } 1870# BASE = export target 1871# FLAGS = AC_EXP_FLAG_* 1872intrinsic("export_amd", [0], indices=[BASE, WRITE_MASK, FLAGS]) 1873intrinsic("export_row_amd", [0, 1], indices=[BASE, WRITE_MASK, FLAGS]) 1874 1875# Export dual source blend outputs with swizzle operation 1876# src[] = { mrt0, mrt1 } 1877intrinsic("export_dual_src_blend_amd", [0, 0], indices=[WRITE_MASK]) 1878 1879# Alpha test reference value 1880system_value("alpha_reference_amd", 1) 1881 1882# Whether to enable barycentric optimization 1883system_value("barycentric_optimize_amd", dest_comp=1, bit_sizes=[1]) 1884 1885# Copy the input into a register which will remain valid for entire quads, even in control flow. 1886# This should only be used directly for texture sources. 1887intrinsic("strict_wqm_coord_amd", src_comp=[0], dest_comp=0, bit_sizes=[32], indices=[BASE], 1888 flags=[CAN_ELIMINATE]) 1889 1890intrinsic("cmat_muladd_amd", src_comp=[16, 16, 0], dest_comp=0, bit_sizes=src2, 1891 indices=[SATURATE, CMAT_SIGNED_MASK], flags=[CAN_ELIMINATE]) 1892 1893# Get the debug log buffer descriptor. 1894intrinsic("load_debug_log_desc_amd", bit_sizes=[32], dest_comp=4, flags=[CAN_ELIMINATE, CAN_REORDER]) 1895 1896# s_sleep BASE (sleep for 64*BASE cycles). BASE must be in [0, 0xffff]. 1897# BASE=0 is valid but isn't useful. 1898# GFX12+: If BASE & 0x8000, sleep forever (until wakeup, trap, or kill). 1899intrinsic("sleep_amd", indices=[BASE]) 1900 1901# s_nop BASE (sleep for BASE+1 cycles, BASE must be in [0, 15]). 1902intrinsic("nop_amd", indices=[BASE]) 1903 1904system_value("ray_tracing_stack_base_lvp", 1) 1905 1906system_value("shader_call_data_offset_lvp", 1) 1907 1908# Broadcom-specific instrinc for tile buffer color reads. 1909# 1910# The hardware requires that we read the samples and components of a pixel 1911# in order, so we cannot eliminate or remove any loads in a sequence. 1912# 1913# src[] = { render_target } 1914# BASE = sample index 1915load("tlb_color_brcm", [1], [BASE, COMPONENT], []) 1916 1917# V3D-specific instrinc for per-sample tile buffer color writes. 1918# 1919# The driver backend needs to identify per-sample color writes and emit 1920# specific code for them. 1921# 1922# src[] = { value, render_target } 1923# BASE = sample index 1924store("tlb_sample_color_v3d", [1], [BASE, COMPONENT, SRC_TYPE], []) 1925 1926# V3D-specific intrinsic to load the number of layers attached to 1927# the target framebuffer 1928intrinsic("load_fb_layers_v3d", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 1929 1930# V3D-specific intrinsic to load W coordinate from the fragment shader payload 1931intrinsic("load_fep_w_v3d", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 1932 1933# Active invocation index within the subgroup. 1934# Equivalent to popcount(ballot(true) & ((1 << subgroup_invocation) - 1)) 1935intrinsic("load_active_subgroup_invocation_agx", dest_comp=1, flags=[CAN_ELIMINATE]) 1936 1937# Total active invocations within the subgroup. 1938# Equivalent to popcount(ballot(true)) 1939intrinsic("load_active_subgroup_count_agx", dest_comp=1, flags=[CAN_ELIMINATE]) 1940 1941# Like ballot() but only within a quad. 1942intrinsic("quad_ballot_agx", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 1943 1944# With [0, 1] clipping, no transform is needed on the output z' = z. But with [-1, 1945# 1] clipping, we need to transform z' = (z + w) / 2. We express both cases as a 1946# lerp between z and w, where this is the lerp coefficient: 0 for [0, 1] and 0.5 1947# for [-1, 1]. 1948system_value("clip_z_coeff_agx", 1) 1949 1950# True if drawing triangle fans with first vertex provoking, false otherwise. 1951# This affects flatshading, which is defined weirdly for fans with first. 1952system_value("is_first_fan_agx", 1, bit_sizes=[1]) 1953 1954# mesa_prim for the input topology (in a geometry shader) 1955system_value("input_topology_agx", 1) 1956 1957# Load a bindless sampler handle mapping a binding table sampler. 1958intrinsic("load_sampler_handle_agx", [1], 1, [], 1959 flags=[CAN_ELIMINATE, CAN_REORDER], 1960 bit_sizes=[16]) 1961 1962# Load a bindless texture handle mapping a binding table texture. 1963intrinsic("load_texture_handle_agx", [1], 2, [], 1964 flags=[CAN_ELIMINATE, CAN_REORDER], 1965 bit_sizes=[32]) 1966 1967# Given a vec2 bindless texture handle, load the address of the texture 1968# descriptor described by that vec2. This allows inspecting the descriptor from 1969# the shader. This does not actually load the content of the descriptor, only 1970# the content of the handle (which is the address of the descriptor). 1971intrinsic("load_from_texture_handle_agx", [2], 1, [], 1972 flags=[CAN_ELIMINATE, CAN_REORDER], 1973 bit_sizes=[64]) 1974 1975# Load the coefficient register corresponding to a given fragment shader input. 1976# Coefficient registers are vec3s that are dotted with <x, y, 1> to interpolate 1977# the input, where x and y are relative to the 32x32 supertile. 1978intrinsic("load_coefficients_agx", [1], 1979 bit_sizes = [32], 1980 dest_comp = 3, 1981 indices=[COMPONENT, IO_SEMANTICS, INTERP_MODE], 1982 flags=[CAN_ELIMINATE, CAN_REORDER]) 1983 1984# src[] = { value, index } 1985# Store a vertex shader output to the Unified Vertex Store (UVS). Indexed by UVS 1986# index, which must be assigned by the driver based on the linked fragment 1987# shader's interpolation qualifiers. This corresponds to the native instruction. 1988store("uvs_agx", [1], [], [CAN_REORDER]) 1989 1990# Driver intrinsic to map a location to a UVS index. This is generated when 1991# lowering store_output to store_uvs_agx, and must be lowered by the driver. 1992intrinsic("load_uvs_index_agx", dest_comp = 1, bit_sizes=[16], 1993 indices=[IO_SEMANTICS], flags=[CAN_ELIMINATE, CAN_REORDER]) 1994 1995# Load/store a pixel in local memory. This operation is formatted, with 1996# conversion between the specified format and the implied register format of the 1997# source/destination (for store/loads respectively). This mostly matters for 1998# converting between floating-point registers and normalized memory formats. 1999# 2000# The format is the pipe_format of the local memory (the source), see 2001# ail for the supported list. 2002# 2003# Logically, this loads/stores a single sample. The sample to load is 2004# specified by the bitfield sample mask source. However, for stores multiple 2005# bits of the sample mask may be set, which will replicate the value. For 2006# pixel rate shading, use 0xFF as the mask to store to all samples regardless of 2007# the sample count. 2008# 2009# All calculations are relative to an immediate byte offset into local 2010# memory, which acts relative to the start of the sample. These instructions 2011# logically access: 2012# 2013# (((((y * tile_width) + x) * nr_samples) + sample) * sample_stride) + offset 2014# 2015# src[] = { sample mask } 2016# base = offset 2017load("local_pixel_agx", [1], [BASE, FORMAT], [CAN_REORDER, CAN_ELIMINATE]) 2018# src[] = { value, sample mask, coordinates } 2019# base = offset 2020store("local_pixel_agx", [1, -1], [BASE, WRITE_MASK, FORMAT, EXPLICIT_COORD], [CAN_REORDER]) 2021 2022# Combined depth/stencil emit, applying to a mask of samples. base indicates 2023# which to write (1 = depth, 2 = stencil, 3 = both). 2024# 2025# src[] = { sample mask, depth, stencil } 2026intrinsic("store_zs_agx", [1, 1, 1], indices=[BASE], flags=[]) 2027 2028# Store a block from local memory into a bound image. Used to write out render 2029# targets within the end-of-tile shader, although it is valid in general compute 2030# kernels. 2031# 2032# The format is the pipe_format of the local memory (the source), see 2033# ail for the supported list. The image format is 2034# specified in the PBE descriptor. 2035# 2036# The image dimension is used to distinguish multisampled images from 2037# non-multisampled images. It must be 2D or MS. 2038# 2039# extra src[] = { logical offset within shared memory, coordinates/layer } 2040image("store_block_agx", [1, -1], extra_indices=[EXPLICIT_COORD]) 2041 2042# Formatted load/store. The format is the pipe_format in memory (see ail for the 2043# supported list). This accesses: 2044# 2045# address + extend(index) << (format shift + shift) 2046# 2047# The nir_intrinsic_base() index encodes the shift. The sign_extend index 2048# determines whether sign- or zero-extension is used for the index. 2049# 2050# All loads and stores on AGX uses these hardware instructions, so while these are 2051# logically load_global_agx/load_global_constant_agx/store_global_agx, the 2052# _global is omitted as it adds nothing. 2053# 2054# src[] = { address, index }. 2055load("agx", [1, 1], [ACCESS, BASE, FORMAT, SIGN_EXTEND], [CAN_ELIMINATE]) 2056load("constant_agx", [1, 1], [ACCESS, BASE, FORMAT, SIGN_EXTEND], 2057 [CAN_ELIMINATE, CAN_REORDER]) 2058# src[] = { value, address, index }. 2059store("agx", [1, 1], [ACCESS, BASE, FORMAT, SIGN_EXTEND]) 2060 2061# Logical complement of load_front_face, mapping to an AGX system value 2062system_value("back_face_agx", 1, bit_sizes=[1, 32]) 2063 2064# Load the base address of an indexed vertex attribute (for lowering). 2065intrinsic("load_vbo_base_agx", src_comp=[1], dest_comp=1, bit_sizes=[64], 2066 flags=[CAN_ELIMINATE, CAN_REORDER]) 2067 2068# When vertex robustness is enabled, loads the maximum valid attribute index for 2069# a given attribute. This is unsigned: the driver ensures that at least one 2070# vertex is always valid to load, directing loads to a zero sink if necessary. 2071intrinsic("load_attrib_clamp_agx", src_comp=[1], dest_comp=1, 2072 bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 2073 2074# Load a driver-internal system value from a given system value set at a given 2075# binding within the set. This is used for correctness when lowering things like 2076# UBOs with merged shaders. 2077# 2078# The FLAGS are used internally for loading the index of the uniform itself, 2079# rather than the contents, used for lowering bindless handles (which encode 2080# uniform indices as immediates in the NIR for technical reasons). 2081load("sysval_agx", [], [DESC_SET, BINDING, FLAGS], [CAN_REORDER, CAN_ELIMINATE]) 2082 2083# Write out a sample mask for a targeted subset of samples, specified in the two 2084# masks. Maps to the corresponding AGX instruction, the actual workings are 2085# documented elsewhere as they are too complicated for this comment. 2086intrinsic("sample_mask_agx", src_comp=[1, 1]) 2087 2088# Discard a subset of samples given by a specified sample mask. This acts like a 2089# per-sample discard, or an inverted accumulating gl_SampleMask write. The 2090# compiler will lower to sample_mask_agx, but that lowering is nontrivial as 2091# sample_mask_agx also triggers depth/stencil testing. 2092intrinsic("discard_agx", src_comp=[1]) 2093 2094# For a given row of the polygon stipple given as an integer source in [0, 31], 2095# load the 32-bit stipple pattern for that row. 2096intrinsic("load_polygon_stipple_agx", src_comp=[1], dest_comp=1, bit_sizes=[32], 2097 flags=[CAN_ELIMINATE, CAN_ELIMINATE]) 2098 2099# The fixed-function sample mask specified in the API (e.g. glSampleMask) 2100system_value("api_sample_mask_agx", 1, bit_sizes=[16]) 2101 2102# Bit mask of samples currently being shaded. For API-level sample shading, this 2103# will usually equal (1 << sample_id). Multiple bits can be set when sample 2104# shading is only enabled due to framebuffer fetch, and the framebuffer has 2105# multiple samples with the same value. 2106# 2107# Used as a loop variable with dynamic sample shading. 2108system_value("active_samples_agx", 1, bit_sizes=[16]) 2109 2110# Loads the sample position array as fixed point packed into a 32-bit word 2111system_value("sample_positions_agx", 1, bit_sizes=[32]) 2112 2113# In a non-monolithic fragment shader part, returns whether this shader part is 2114# responsible for Z/S testing after its final discard. ~0/0 boolean. 2115system_value("shader_part_tests_zs_agx", 1, bit_sizes=[16]) 2116 2117# Returns whether the API depth test is NEVER. We emulate this in shader when 2118# fragment side effects are used to ensure the fragment shader executes. 2119system_value("depth_never_agx", 1, bit_sizes=[16]) 2120 2121# In a fragment shader, returns the log2 of the number of samples in the 2122# tilebuffer. This is the unprocessed value written in the corresponding USC 2123# word. Used to determine whether sample mask writes have any effect when sample 2124# count is dynamic. 2125system_value("samples_log2_agx", 1, bit_sizes=[16]) 2126 2127# Loads the fixed-function glPointSize() value, or zero if the 2128# shader-supplied value should be used. 2129system_value("fixed_point_size_agx", 1, bit_sizes=[32]) 2130 2131# Bit mask of TEX locations that are replaced with point sprites 2132system_value("tex_sprite_mask_agx", 1, bit_sizes=[16]) 2133 2134# Image loads go through the texture cache, which is not coherent with the PBE 2135# or memory access, so fencing is necessary for writes to become visible. 2136 2137# Make writes via main memory (image atomics) visible for texturing. 2138barrier("fence_pbe_to_tex_agx") 2139 2140# Make writes from global memory instructions (atomics) visible for texturing. 2141barrier("fence_mem_to_tex_agx") 2142 2143# Variant of fence_pbe_to_tex_agx specialized to stores in pixel shaders that 2144# act like render target writes, in conjunction with fragment interlock. 2145barrier("fence_pbe_to_tex_pixel_agx") 2146 2147# Unknown fence used in the helper program on exit. 2148barrier("fence_helper_exit_agx") 2149 2150# Pointer to the buffer passing outputs VS->TCS, VS->GS, or TES->GS linkage. 2151system_value("vs_output_buffer_agx", 1, bit_sizes=[64]) 2152 2153# Mask of VS->TCS, VS->GS, or TES->GS outputs. This is modelled as a sysval 2154# directly so it can be dynamic with shader objects or constant folded with 2155# pipelines (including GPL) 2156system_value("vs_outputs_agx", 1, bit_sizes=[64]) 2157 2158# Address of state for AGX input assembly lowering for geometry/tessellation 2159system_value("input_assembly_buffer_agx", 1, bit_sizes=[64]) 2160 2161# Address of the parameter buffer for AGX geometry shaders 2162system_value("geometry_param_buffer_agx", 1, bit_sizes=[64]) 2163 2164# Address of the parameter buffer for AGX tessellation shaders 2165system_value("tess_param_buffer_agx", 1, bit_sizes=[64]) 2166 2167# Address of the pipeline statistic query result indexed by BASE 2168system_value("stat_query_address_agx", 1, bit_sizes=[64], indices=[BASE]) 2169 2170# Helper shader intrinsics 2171# src[] = { value }. 2172intrinsic("doorbell_agx", src_comp=[1]) 2173 2174# src[] = { index, stack_address }. 2175intrinsic("stack_map_agx", src_comp=[1, 1]) 2176 2177# src[] = { index }. 2178# dst[] = { stack_address }. 2179intrinsic("stack_unmap_agx", src_comp=[1], dest_comp=1, bit_sizes=[32]) 2180 2181# dst[] = { GPU core ID }. 2182system_value("core_id_agx", 1, bit_sizes=[32]) 2183 2184# dst[] = { Helper operation type }. 2185load("helper_op_id_agx", [], [], [CAN_ELIMINATE]) 2186 2187# dst[] = { Helper argument low 32 bits }. 2188load("helper_arg_lo_agx", [], [], [CAN_ELIMINATE]) 2189 2190# dst[] = { Helper argument high 32 bits }. 2191load("helper_arg_hi_agx", [], [], [CAN_ELIMINATE]) 2192 2193# Export a vector. At the end of the shader part, the source is copied to the 2194# indexed GPRs starting at BASE. Exports must not overlap within a shader part. 2195# Must only appear in the last block of the shader part. 2196intrinsic("export_agx", [0], indices=[BASE]) 2197 2198# Load an exported vector at the beginning of the shader part from GPRs starting 2199# at BASE. Must only appear in the first block of the shader part. 2200load("exported_agx", [], [BASE], [CAN_ELIMINATE]) 2201 2202# Intel-specific query for loading from the isl_image_param struct passed 2203# into the shader as a uniform. The variable is a deref to the image 2204# variable. The const index specifies which of the six parameters to load. 2205intrinsic("image_deref_load_param_intel", src_comp=[1], dest_comp=0, 2206 indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) 2207image("load_raw_intel", src_comp=[1], dest_comp=0, 2208 flags=[CAN_ELIMINATE]) 2209image("store_raw_intel", src_comp=[1, 0]) 2210 2211# Number of data items being operated on for a SIMD program. 2212system_value("simd_width_intel", 1) 2213 2214# Load a relocatable 32-bit value 2215intrinsic("load_reloc_const_intel", dest_comp=1, bit_sizes=[32], 2216 indices=[PARAM_IDX, BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) 2217 2218# 1 component 32bit surface index that can be used for bindless or BTI heaps 2219# 2220# This intrinsic is used to figure out what UBOs accesses could be promoted to 2221# push constants. To allow promoting a load_ubo to push constants, we need to 2222# know that the surface & offset are constants. If we want to use the bindless 2223# heap for this we have to build the surface index with a pushed constant for 2224# the descriptor set which prevents us from doing a nir_src_is_const() check. 2225# With this intrinsic, we can just check the surface_index src with 2226# nir_src_is_const() and ignore set_offset. 2227# 2228# src[] = { set_offset, surface_index, array_index, bindless_base_offset } 2229intrinsic("resource_intel", dest_comp=1, bit_sizes=[32], 2230 src_comp=[1, 1, 1, 1], 2231 indices=[DESC_SET, BINDING, RESOURCE_ACCESS_INTEL, RESOURCE_BLOCK_INTEL], 2232 flags=[CAN_ELIMINATE, CAN_REORDER]) 2233 2234# OpSubgroupBlockReadINTEL and OpSubgroupBlockWriteINTEL from SPV_INTEL_subgroups. 2235intrinsic("load_deref_block_intel", dest_comp=0, src_comp=[-1], 2236 indices=[ACCESS], flags=[CAN_ELIMINATE]) 2237intrinsic("store_deref_block_intel", src_comp=[-1, 0], indices=[WRITE_MASK, ACCESS]) 2238 2239# src[] = { address }. 2240load("global_block_intel", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 2241 2242# src[] = { buffer_index, offset }. 2243load("ssbo_block_intel", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 2244 2245# src[] = { offset }. 2246load("shared_block_intel", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 2247 2248# src[] = { value, address }. 2249store("global_block_intel", [1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 2250 2251# src[] = { value, block_index, offset } 2252store("ssbo_block_intel", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 2253 2254# src[] = { value, offset }. 2255store("shared_block_intel", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) 2256 2257# src[] = { address }. 2258load("global_constant_uniform_block_intel", [1], 2259 [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE, CAN_REORDER]) 2260 2261# Similar to load_global_const_block_intel but for UBOs 2262# offset should be uniform 2263# src[] = { buffer_index, offset }. 2264load("ubo_uniform_block_intel", [-1, 1], 2265 [ACCESS, ALIGN_MUL, ALIGN_OFFSET, RANGE_BASE, RANGE], [CAN_ELIMINATE, CAN_REORDER]) 2266 2267# Similar to load_global_const_block_intel but for SSBOs 2268# offset should be uniform 2269# src[] = { buffer_index, offset }. 2270load("ssbo_uniform_block_intel", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 2271 2272# Similar to load_global_const_block_intel but for shared memory 2273# src[] = { offset }. 2274load("shared_uniform_block_intel", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 2275 2276# Inline register delivery (available on Gfx12.5+ for CS/Mesh/Task stages) 2277intrinsic("load_inline_data_intel", [], dest_comp=0, 2278 indices=[BASE], 2279 flags=[CAN_ELIMINATE, CAN_REORDER]) 2280 2281# Intrinsics for Intel bindless thread dispatch 2282# BASE=brw_topoloy_id 2283system_value("topology_id_intel", 1, indices=[BASE]) 2284system_value("btd_stack_id_intel", 1) 2285system_value("btd_global_arg_addr_intel", 1, bit_sizes=[64]) 2286system_value("btd_local_arg_addr_intel", 1, bit_sizes=[64]) 2287system_value("btd_resume_sbt_addr_intel", 1, bit_sizes=[64]) 2288# src[] = { global_arg_addr, btd_record } 2289intrinsic("btd_spawn_intel", src_comp=[1, 1]) 2290# RANGE=stack_size 2291intrinsic("btd_stack_push_intel", indices=[STACK_SIZE]) 2292# src[] = { } 2293intrinsic("btd_retire_intel") 2294 2295# Intel-specific ray-tracing intrinsic 2296# src[] = { globals, level, operation } SYNCHRONOUS=synchronous 2297intrinsic("trace_ray_intel", src_comp=[1, 1, 1], indices=[SYNCHRONOUS]) 2298 2299# System values used for ray-tracing on Intel 2300system_value("ray_base_mem_addr_intel", 1, bit_sizes=[64]) 2301system_value("ray_hw_stack_size_intel", 1) 2302system_value("ray_sw_stack_size_intel", 1) 2303system_value("ray_num_dss_rt_stacks_intel", 1) 2304system_value("ray_hit_sbt_addr_intel", 1, bit_sizes=[64]) 2305system_value("ray_hit_sbt_stride_intel", 1, bit_sizes=[16]) 2306system_value("ray_miss_sbt_addr_intel", 1, bit_sizes=[64]) 2307system_value("ray_miss_sbt_stride_intel", 1, bit_sizes=[16]) 2308system_value("callable_sbt_addr_intel", 1, bit_sizes=[64]) 2309system_value("callable_sbt_stride_intel", 1, bit_sizes=[16]) 2310system_value("leaf_opaque_intel", 1, bit_sizes=[1]) 2311system_value("leaf_procedural_intel", 1, bit_sizes=[1]) 2312# Values : 2313# 0: AnyHit 2314# 1: ClosestHit 2315# 2: Miss 2316# 3: Intersection 2317system_value("btd_shader_type_intel", 1) 2318system_value("ray_query_global_intel", 1, bit_sizes=[64]) 2319 2320# Source 0: Accumulator matrix (type specified by DEST_TYPE) 2321# Source 1: A matrix (type specified by SRC_TYPE) 2322# Source 2: B matrix (type specified by SRC_TYPE) 2323# 2324# The matrix parameters are the slices owned by the invocation. 2325# 2326# The accumulator is source 0 because that is the source the intrinsic 2327# infrastructure in NIR uses to determine the number of components in the 2328# result. 2329# 2330# The number of components for the second source is -1 to avoid validation of 2331# its value. Some supported configurations will have the component count of 2332# that matrix different than the others. 2333intrinsic("dpas_intel", dest_comp=0, src_comp=[0, -1, 0], 2334 indices=[DEST_TYPE, SRC_TYPE, SATURATE, SYSTOLIC_DEPTH, REPEAT_COUNT], 2335 flags=[CAN_ELIMINATE]) 2336 2337# NVIDIA-specific intrinsics 2338# src[] = { index, offset }. 2339intrinsic("ldc_nv", dest_comp=0, src_comp=[1, 1], 2340 indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET], 2341 flags=[CAN_ELIMINATE, CAN_REORDER]) 2342# [Un]pins an LDCX handle around non-uniform control-flow sections 2343# src[] = { handle }. 2344intrinsic("pin_cx_handle_nv", src_comp=[1]) 2345intrinsic("unpin_cx_handle_nv", src_comp=[1]) 2346# src[] = { handle, offset }. 2347intrinsic("ldcx_nv", dest_comp=0, src_comp=[1, 1], 2348 indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET], 2349 flags=[CAN_ELIMINATE, CAN_REORDER]) 2350intrinsic("load_sysval_nv", dest_comp=1, src_comp=[], bit_sizes=[32, 64], 2351 indices=[ACCESS, BASE], flags=[CAN_ELIMINATE]) 2352intrinsic("isberd_nv", dest_comp=1, src_comp=[1], bit_sizes=[32], 2353 flags=[CAN_ELIMINATE, CAN_REORDER]) 2354intrinsic("al2p_nv", dest_comp=1, src_comp=[1], bit_sizes=[32], 2355 indices=[BASE, FLAGS], flags=[CAN_ELIMINATE, CAN_REORDER]) 2356# src[] = { vtx, offset }. 2357# FLAGS is struct nak_nir_attr_io_flags 2358intrinsic("ald_nv", dest_comp=0, src_comp=[1, 1], bit_sizes=[32], 2359 indices=[BASE, RANGE_BASE, RANGE, FLAGS, ACCESS], 2360 flags=[CAN_ELIMINATE]) 2361# src[] = { data, vtx, offset }. 2362# FLAGS is struct nak_nir_attr_io_flags 2363intrinsic("ast_nv", src_comp=[0, 1, 1], 2364 indices=[BASE, RANGE_BASE, RANGE, FLAGS], flags=[]) 2365# src[] = { inv_w, offset }. 2366intrinsic("ipa_nv", dest_comp=1, src_comp=[1, 1], bit_sizes=[32], 2367 indices=[BASE, FLAGS], flags=[CAN_ELIMINATE, CAN_REORDER]) 2368# FLAGS indicate if we load vertex_id == 2 2369intrinsic("ldtram_nv", dest_comp=2, bit_sizes=[32], 2370 indices=[BASE, FLAGS], flags=[CAN_ELIMINATE, CAN_REORDER]) 2371 2372# NVIDIA-specific Geometry Shader intrinsics. 2373# These contain an additional integer source and destination with the primitive handle input/output. 2374intrinsic("emit_vertex_nv", dest_comp=1, src_comp=[1], indices=[STREAM_ID]) 2375intrinsic("end_primitive_nv", dest_comp=1, src_comp=[1], indices=[STREAM_ID]) 2376# Contains the final primitive handle and indicate the end of emission. 2377intrinsic("final_primitive_nv", src_comp=[1]) 2378 2379# src[] = { data }. 2380intrinsic("fs_out_nv", src_comp=[1], indices=[BASE], flags=[]) 2381barrier("copy_fs_outputs_nv") 2382 2383intrinsic("bar_set_nv", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 2384intrinsic("bar_break_nv", dest_comp=1, bit_sizes=[32], src_comp=[1, 1]) 2385# src[] = { bar, bar_set } 2386intrinsic("bar_sync_nv", src_comp=[1, 1]) 2387 2388# Stall until the given SSA value is available 2389intrinsic("ssa_bar_nv", src_comp=[1]) 2390 2391# NVIDIA-specific system values 2392system_value("warps_per_sm_nv", 1, bit_sizes=[32]) 2393system_value("sm_count_nv", 1, bit_sizes=[32]) 2394system_value("warp_id_nv", 1, bit_sizes=[32]) 2395system_value("sm_id_nv", 1, bit_sizes=[32]) 2396 2397# In order to deal with flipped render targets, gl_PointCoord may be flipped 2398# in the shader requiring a shader key or extra instructions or it may be 2399# flipped in hardware based on a state bit. This version of gl_PointCoord 2400# is defined to be whatever thing the hardware can easily give you, so long as 2401# it's in normalized coordinates in the range [0, 1] across the point. 2402# 2403# src0 contains barycentrics for interpolation. 2404intrinsic("load_point_coord_maybe_flipped", dest_comp=2, bit_sizes=[32], src_comp=[2]) 2405 2406 2407# Load texture size values: 2408# 2409# Takes a sampler # and returns width, height and depth. If texture is a array 2410# texture it returns width, height and array size. Used for txs lowering. 2411intrinsic("load_texture_size_etna", src_comp=[1], dest_comp=3, 2412 flags=[CAN_ELIMINATE, CAN_REORDER]) 2413 2414# Zink specific intrinsics 2415 2416# src[] = { field }. 2417load("push_constant_zink", [1], [COMPONENT], [CAN_ELIMINATE, CAN_REORDER]) 2418 2419system_value("shader_index", 1, bit_sizes=[32]) 2420 2421system_value("coalesced_input_count", 1, bit_sizes=[32]) 2422 2423# Initialize a payload array per scope 2424# 2425# 0. Payloads deref 2426# 1. Payload count 2427# 2. Node index 2428intrinsic("initialize_node_payloads", src_comp=[-1, 1, 1], indices=[EXECUTION_SCOPE]) 2429 2430# Optionally enqueue payloads after shader finished writing to them 2431intrinsic("enqueue_node_payloads", src_comp=[-1]) 2432 2433# Returns true if it has been called for every payload. 2434intrinsic("finalize_incoming_node_payload", src_comp=[-1], dest_comp=1) 2435