1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 * Copyright (c) 2024, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef HANDOFF_H 9 #define HANDOFF_H 10 11 #define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */ 12 #define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */ 13 #define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */ 14 #define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */ 15 #define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */ 16 #define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */ 17 #define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */ 18 #define HANDOFF_MAGIC_PERIPHERAL 0x50455249 /* PERIPHERAL */ 19 #define HANDOFF_MAGIC_DDR 0x5344524d /* DDR */ 20 21 #include <socfpga_plat_def.h> 22 23 typedef struct handoff_t { 24 /* header */ 25 uint32_t header_magic; 26 uint32_t header_device; 27 uint32_t _pad_0x08_0x10[2]; 28 29 /* pinmux configuration - select */ 30 uint32_t pinmux_sel_magic; 31 uint32_t pinmux_sel_length; 32 uint32_t _pad_0x18_0x20[2]; 33 uint32_t pinmux_sel_array[96]; /* offset, value */ 34 35 /* pinmux configuration - io control */ 36 uint32_t pinmux_io_magic; 37 uint32_t pinmux_io_length; 38 uint32_t _pad_0x1a8_0x1b0[2]; 39 uint32_t pinmux_io_array[96]; /* offset, value */ 40 41 /* pinmux configuration - use fpga switch */ 42 uint32_t pinmux_fpga_magic; 43 uint32_t pinmux_fpga_length; 44 uint32_t _pad_0x338_0x340[2]; 45 uint32_t pinmux_fpga_array[44]; /* offset, value */ 46 /* TODO: Temp remove due to add in extra handoff data */ 47 // uint32_t _pad_0x3e8_0x3f0[2]; 48 49 /* pinmux configuration - io delay */ 50 uint32_t pinmux_delay_magic; 51 uint32_t pinmux_delay_length; 52 uint32_t _pad_0x3f8_0x400[2]; 53 uint32_t pinmux_iodelay_array[96]; /* offset, value */ 54 55 /* clock configuration */ 56 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 57 uint32_t clock_magic; 58 uint32_t clock_length; 59 uint32_t _pad_0x588_0x590[2]; 60 uint32_t main_pll_mpuclk; 61 uint32_t main_pll_nocclk; 62 uint32_t main_pll_cntr2clk; 63 uint32_t main_pll_cntr3clk; 64 uint32_t main_pll_cntr4clk; 65 uint32_t main_pll_cntr5clk; 66 uint32_t main_pll_cntr6clk; 67 uint32_t main_pll_cntr7clk; 68 uint32_t main_pll_cntr8clk; 69 uint32_t main_pll_cntr9clk; 70 uint32_t main_pll_nocdiv; 71 uint32_t main_pll_pllglob; 72 uint32_t main_pll_fdbck; 73 uint32_t main_pll_pllc0; 74 uint32_t main_pll_pllc1; 75 uint32_t _pad_0x5cc_0x5d0[1]; 76 uint32_t per_pll_cntr2clk; 77 uint32_t per_pll_cntr3clk; 78 uint32_t per_pll_cntr4clk; 79 uint32_t per_pll_cntr5clk; 80 uint32_t per_pll_cntr6clk; 81 uint32_t per_pll_cntr7clk; 82 uint32_t per_pll_cntr8clk; 83 uint32_t per_pll_cntr9clk; 84 uint32_t per_pll_emacctl; 85 uint32_t per_pll_gpiodiv; 86 uint32_t per_pll_pllglob; 87 uint32_t per_pll_fdbck; 88 uint32_t per_pll_pllc0; 89 uint32_t per_pll_pllc1; 90 uint32_t hps_osc_clk_h; 91 uint32_t fpga_clk_hz; 92 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX 93 uint32_t clock_magic; 94 uint32_t clock_length; 95 uint32_t _pad_0x588_0x590[2]; 96 uint32_t main_pll_mpuclk; 97 uint32_t main_pll_nocclk; 98 uint32_t main_pll_nocdiv; 99 uint32_t main_pll_pllglob; 100 uint32_t main_pll_fdbck; 101 uint32_t main_pll_pllc0; 102 uint32_t main_pll_pllc1; 103 uint32_t main_pll_pllc2; 104 uint32_t main_pll_pllc3; 105 uint32_t main_pll_pllm; 106 uint32_t per_pll_emacctl; 107 uint32_t per_pll_gpiodiv; 108 uint32_t per_pll_pllglob; 109 uint32_t per_pll_fdbck; 110 uint32_t per_pll_pllc0; 111 uint32_t per_pll_pllc1; 112 uint32_t per_pll_pllc2; 113 uint32_t per_pll_pllc3; 114 uint32_t per_pll_pllm; 115 uint32_t alt_emacactr; 116 uint32_t alt_emacbctr; 117 uint32_t alt_emacptpctr; 118 uint32_t alt_gpiodbctr; 119 uint32_t alt_sdmmcctr; 120 uint32_t alt_s2fuser0ctr; 121 uint32_t alt_s2fuser1ctr; 122 uint32_t alt_psirefctr; 123 uint32_t hps_osc_clk_h; 124 uint32_t fpga_clk_hz; 125 uint32_t _pad_0x604_0x610[3]; 126 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 127 uint32_t clock_magic; 128 uint32_t clock_length; 129 uint32_t _pad_0x588_0x590[2]; 130 131 /* main group PLL */ 132 uint32_t main_pll_nocclk; 133 uint32_t main_pll_nocdiv; 134 uint32_t main_pll_pllglob; 135 uint32_t main_pll_fdbck; 136 uint32_t main_pll_pllc0; 137 uint32_t main_pll_pllc1; 138 uint32_t main_pll_pllc2; 139 uint32_t main_pll_pllc3; 140 uint32_t main_pll_pllm; 141 142 /* peripheral group PLL */ 143 uint32_t per_pll_emacctl; 144 uint32_t per_pll_gpiodiv; 145 uint32_t per_pll_pllglob; 146 uint32_t per_pll_fdbck; 147 uint32_t per_pll_pllc0; 148 uint32_t per_pll_pllc1; 149 uint32_t per_pll_pllc2; 150 uint32_t per_pll_pllc3; 151 uint32_t per_pll_pllm; 152 153 /* control group */ 154 uint32_t alt_emacactr; 155 uint32_t alt_emacbctr; 156 uint32_t alt_emacptpctr; 157 uint32_t alt_gpiodbctr; 158 uint32_t alt_s2fuser0ctr; 159 uint32_t alt_s2fuser1ctr; 160 uint32_t alt_psirefctr; 161 uint32_t alt_usb31ctr; 162 uint32_t alt_dsuctr; 163 uint32_t alt_core01ctr; 164 uint32_t alt_core23ctr; 165 uint32_t alt_core2ctr; 166 uint32_t alt_core3ctr; 167 uint32_t hps_osc_clk_hz; 168 uint32_t fpga_clk_hz; 169 uint32_t _pad_0x604_0x610[3]; 170 #endif 171 172 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 173 /* peripheral configuration - select */ 174 uint32_t peripheral_pwr_gate_magic; 175 uint32_t peripheral_pwr_gate_length; 176 uint32_t _pad_0x08_0x0C[2]; 177 uint32_t peripheral_pwr_gate_array; /* offset, value */ 178 179 /* ddr configuration - select */ 180 uint32_t ddr_magic; 181 uint32_t ddr_length; 182 uint32_t _pad_0x1C_0x20[2]; 183 uint32_t ddr_config; /* BIT[0]-Dual Port. BIT[1]-Dual EMIF */ 184 #endif 185 } handoff; 186 187 int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr); 188 int socfpga_get_handoff(handoff *hoff_ptr); 189 190 #endif 191