1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 3 #ifndef _SOC_MEDIATEK_MT8195_DDP_H_ 4 #define _SOC_MEDIATEK_MT8195_DDP_H_ 5 6 #include <soc/addressmap.h> 7 #include <soc/ddp_common.h> 8 #include <soc/display.h> 9 #include <types.h> 10 11 #define MAIN_PATH_OVL_NR 2 12 13 struct mmsys_cfg_regs { 14 u32 reserved_0x000[64]; /* 0x000 */ 15 u32 mmsys_cg_con0; /* 0x100 */ 16 u32 mmsys_cg_set0; /* 0x104 */ 17 u32 mmsys_cg_clr0; /* 0x108 */ 18 u32 reserved_0x10c; /* 0x10C */ 19 u32 mmsys_cg_con1; /* 0x110 */ 20 u32 mmsys_cg_set1; /* 0x114 */ 21 u32 mmsys_cg_clr1; /* 0x118 */ 22 u32 reserved_0x11c; /* 0x11C */ 23 u32 mmsys_cg_con2; /* 0x120 */ 24 u32 mmsys_cg_set2; /* 0x124 */ 25 u32 mmsys_cg_clr2; /* 0x128 */ 26 u32 reserved_0x12c[885]; /* 0x12C */ 27 u32 reserved_0xf00; /* 0xF00 */ 28 u32 reserved_0xf04; /* 0xF04 */ 29 u32 reserved_0xf08; /* 0xF08 */ 30 u32 reserved_0xf0c; /* 0xF0C */ 31 u32 reserved_0xf10; /* 0xF10 */ 32 u32 mmsys_ovl_mout_en; /* 0xF14 */ 33 u32 reserved_0xf18; /* 0xF18 */ 34 u32 reserved_0xf1c; /* 0xF1C */ 35 u32 reserved_0xf20; /* 0xF20 */ 36 u32 reserved_0xf24; /* 0xF24 */ 37 u32 reserved_0xf28; /* 0xF28 */ 38 u32 reserved_0xf2c; /* 0xF2C */ 39 u32 reserved_0xf30; /* 0xF30 */ 40 u32 mmsys_sel_in; /* 0xF34 */ 41 u32 mmsys_sel_out; /* 0xF38 */ 42 u32 reserved_0xf3c; /* 0xF3C */ 43 u32 reserved_0xf40; /* 0xF40 */ 44 }; 45 46 check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); 47 check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110); 48 check_member(mmsys_cfg_regs, mmsys_cg_con2, 0x120); 49 check_member(mmsys_cfg_regs, mmsys_ovl_mout_en, 0xF14); 50 static struct mmsys_cfg_regs *const mmsys_cfg = (void *)VDOSYS0_BASE; 51 52 /* DISP_REG_CONFIG_MMSYS_CG_CON0 53 Configures free-run vdo0_clks gating 0 54 0: Enable clock 55 1: Clock gating */ 56 enum { 57 CG_CON0_DISP_OVL0 = BIT(0), 58 CG_CON0_DISP_COLOR0 = BIT(2), 59 CG_CON0_DISP_CCORR0 = BIT(4), 60 CG_CON0_DISP_AAL0 = BIT(6), 61 CG_CON0_DISP_GAMMA0 = BIT(8), 62 CG_CON0_DISP_DITHER0 = BIT(10), 63 CG_CON0_DISP_RDMA0 = BIT(19), 64 CG_CON0_DISP_DSC_WRAP0 = BIT(23), 65 CG_CON0_DISP_VPP_MERGE0 = BIT(24), 66 CG_CON0_DISP_DP_INTF0 = BIT(25), 67 CG_CON0_DISP_MUTEX0 = BIT(26), 68 69 CG_CON0_DISP_ALL = CG_CON0_DISP_MUTEX0 | 70 CG_CON0_DISP_OVL0 | 71 CG_CON0_DISP_RDMA0 | 72 CG_CON0_DISP_COLOR0 | 73 CG_CON0_DISP_CCORR0 | 74 CG_CON0_DISP_AAL0 | 75 CG_CON0_DISP_GAMMA0 | 76 CG_CON0_DISP_DITHER0 | 77 CG_CON0_DISP_DSC_WRAP0 | 78 CG_CON0_DISP_VPP_MERGE0 | 79 CG_CON0_DISP_DP_INTF0, 80 CG_CON0_ALL = 0xffffffff 81 }; 82 83 /* DISP_REG_CONFIG_MMSYS_CG_CON1 84 Configures free-run clock gating 0 85 0: Enable clock 86 1: Clock gating */ 87 enum { 88 CG_CON1_SMI_GALS = BIT(10), 89 CG_CON1_SMI_COMMON = BIT(11), 90 CG_CON1_SMI_EMI = BIT(12), 91 CG_CON1_SMI_IOMMU = BIT(13), 92 CG_CON1_SMI_LARB = BIT(14), 93 CG_CON1_SMI_RSI = BIT(15), 94 95 CG_CON1_DISP_ALL = CG_CON1_SMI_GALS | 96 CG_CON1_SMI_COMMON | 97 CG_CON1_SMI_EMI | 98 CG_CON1_SMI_IOMMU | 99 CG_CON1_SMI_LARB | 100 CG_CON1_SMI_RSI, 101 CG_CON1_ALL = 0xffffffff 102 }; 103 104 /* DISP_REG_CONFIG_MMSYS_CG_CON2 105 Configures free-run clock gating 0 106 0: Enable clock 107 1: Clock gating */ 108 enum { 109 CG_CON2_DSI_DSI0 = BIT(0), 110 CG_CON2_DPI_DPI0 = BIT(8), 111 CG_CON2_DP_INTF0 = BIT(16), 112 CG_CON2_MM_26MHZ = BIT(24), 113 114 CG_CON2_DISP_ALL = CG_CON2_DP_INTF0 | 115 CG_CON2_MM_26MHZ, 116 CG_CON2_ALL = 0xffffffff 117 }; 118 119 enum { 120 DISP_OVL0_GO_BLEND = BIT(0), 121 DISP_OVL0_GO_BG = BIT(1), 122 DISP_OVL0_TO_DISP_RDMA0 = BIT(0), 123 DITHER0_MOUT_DSI0 = BIT(0), 124 }; 125 126 enum { 127 SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT = (0 << 0), 128 SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 = (0 << 4), 129 SEL_IN_DP_INTF0_FROM_VPP_MERGE = (1 << 12), 130 SEL_OUT_DISP_DITHER0_TO_DSC_WRAP0_IN = (0 << 0), 131 SEL_OUT_VPP_MERGE_TO_DP_INTF0 = (1 << 8), 132 SEL_OUT_DSC_WRAP0_OUT_TO_VPP_MERGE = (2 << 12), 133 }; 134 135 struct disp_mutex_regs { 136 u32 inten; 137 u32 intsta; 138 u32 reserved0[6]; 139 struct { 140 u32 en; 141 u32 dummy; 142 u32 rst; 143 u32 ctl; 144 u32 mod; 145 u32 reserved[3]; 146 } mutex[12]; 147 }; 148 149 static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; 150 151 enum { 152 MUTEX_MOD_DISP_OVL0 = BIT(0), 153 MUTEX_MOD_DISP_RDMA0 = BIT(2), 154 MUTEX_MOD_DISP_COLOR0 = BIT(3), 155 MUTEX_MOD_DISP_CCORR0 = BIT(4), 156 MUTEX_MOD_DISP_AAL0 = BIT(5), 157 MUTEX_MOD_DISP_GAMMA0 = BIT(6), 158 MUTEX_MOD_DISP_DITHER0 = BIT(7), 159 MUTEX_MOD_DISP_DSC0 = BIT(9), 160 MUTEX_MOD_DISP_MERGE0 = BIT(20), 161 MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | 162 MUTEX_MOD_DISP_RDMA0 | 163 MUTEX_MOD_DISP_COLOR0 | 164 MUTEX_MOD_DISP_CCORR0 | 165 MUTEX_MOD_DISP_AAL0 | 166 MUTEX_MOD_DISP_GAMMA0 | 167 MUTEX_MOD_DISP_DITHER0 | 168 MUTEX_MOD_DISP_DSC0 | 169 MUTEX_MOD_DISP_MERGE0, 170 }; 171 172 enum { 173 MUTEX_SOF_SINGLE_MODE = 0, 174 MUTEX_SOF_DSI0 = 1, 175 MUTEX_SOF_DPI0 = 2, 176 MUTEX_SOF_DP_INTF0 = 3, 177 }; 178 179 struct disp_ccorr_regs { 180 u32 en; 181 u32 reset; 182 u32 inten; 183 u32 intsta; 184 u32 status; 185 u32 reserved0[3]; 186 u32 cfg; 187 u32 reserved1[3]; 188 u32 size; 189 u32 reserved2[27]; 190 u32 shadow; 191 }; 192 check_member(disp_ccorr_regs, shadow, 0xa0); 193 194 struct disp_gamma_regs { 195 u32 en; 196 u32 reset; 197 u32 inten; 198 u32 intsta; 199 u32 status; 200 u32 reserved0[3]; 201 u32 cfg; 202 u32 reserved1[3]; 203 u32 size; 204 }; 205 check_member(disp_gamma_regs, size, 0x30); 206 207 struct disp_aal_regs { 208 u32 en; 209 u32 reset; 210 u32 inten; 211 u32 intsta; 212 u32 status; 213 u32 reserved0[3]; 214 u32 cfg; 215 u32 reserved1[3]; 216 u32 size; 217 u32 reserved2[47]; 218 u32 shadow; 219 u32 reserved3[249]; 220 u32 output_size; 221 }; 222 check_member(disp_aal_regs, shadow, 0xf0); 223 check_member(disp_aal_regs, output_size, 0x4d8); 224 225 struct disp_dither_regs { 226 u32 en; 227 u32 reset; 228 u32 inten; 229 u32 intsta; 230 u32 status; 231 u32 reserved0[3]; 232 u32 cfg; 233 u32 reserved1[3]; 234 u32 size; 235 u32 reserved2[51]; 236 u32 shadow; 237 }; 238 check_member(disp_dither_regs, shadow, 0x100); 239 240 struct disp_dsc_regs { 241 u32 con; 242 u32 inten; 243 u32 intsta; 244 u32 intack; 245 u32 status; 246 u32 reserved0; 247 u32 pic_w; 248 u32 pic_h; 249 u32 slice_w; 250 u32 slice_h; 251 u32 chunk_size; 252 u32 buf_size; 253 u32 mode; 254 u32 cfg; 255 u32 pad; 256 u32 reserved1[9]; 257 u32 dbg_con; 258 u32 cksm_mon0; 259 u32 cksm_mon1; 260 u32 mute_con; 261 u32 obuf; 262 u32 reserved2[3]; 263 u32 pps[20]; 264 u32 reserved3[12]; 265 u32 dbg[21]; 266 u32 reserved4[3]; 267 u32 enc_dbg[4]; 268 u32 reserved5[36]; 269 u32 shadow; 270 }; 271 check_member(disp_dsc_regs, obuf, 0x70); 272 check_member(disp_dsc_regs, shadow, 0x200); 273 274 struct disp_merge_regs { 275 u32 en; 276 u32 reset; 277 u32 reserved0[2]; 278 u32 cfg0; 279 u32 cfg1; 280 u32 cfg2; 281 u32 cfg3; 282 u32 cfg4; 283 u32 cfg5; 284 u32 cfg6; 285 u32 cfg7; 286 u32 cfg8; 287 u32 cfg9; 288 u32 cfg10; 289 u32 cfg11; 290 u32 cfg12; 291 u32 cfg13; 292 u32 cfg14; 293 u32 cfg15; 294 u32 cfg16; 295 u32 cfg17; 296 u32 cfg18; 297 u32 cfg19; 298 u32 cfg20; 299 u32 cfg21; 300 u32 cfg22; 301 u32 cfg23; 302 u32 cfg24; 303 u32 cfg25; 304 u32 cfg26; 305 u32 cfg27; 306 u32 cfg28; 307 u32 cfg29; 308 u32 cfg30; 309 u32 cfg31; 310 u32 cfg32; 311 u32 cfg33; 312 u32 cfg34; 313 u32 cfg35; 314 u32 cfg36; 315 u32 cfg37; 316 u32 cfg38; 317 u32 cfg39; 318 u32 cfg40; 319 u32 cfg41; 320 u32 cfg42; 321 u32 cfg43; 322 u32 cfg44; 323 u32 cfg45; 324 u32 cfg46; 325 u32 cfg47; 326 u32 cfg48; 327 u32 cfg49; 328 u32 cfg50; 329 u32 cfg51; 330 u32 cfg52; 331 u32 cfg53; 332 u32 cfg54; 333 u32 cfg55; 334 }; 335 check_member(disp_merge_regs, cfg55, 0xec); 336 337 enum { 338 DISP_DSC0_EN = BIT(0), 339 DISP_DSC0_DUAL_INOUT = BIT(2), 340 DISP_DSC0_BYPASS = BIT(4), 341 DISP_DSC0_UFOE_SEL = BIT(16), 342 DISP_DSC0_CON = DISP_DSC0_EN | 343 DISP_DSC0_DUAL_INOUT | 344 DISP_DSC0_BYPASS | 345 DISP_DSC0_UFOE_SEL, 346 }; 347 348 enum { 349 PQ_EN = BIT(0), 350 PQ_RELAY_MODE = BIT(0), 351 PQ_ENGINE_EN = BIT(1), 352 }; 353 354 static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; 355 356 static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE; 357 358 static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; 359 360 static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE; 361 362 static struct disp_dsc_regs *const disp_dsc = (void *)DISP_DSC0_BASE; 363 364 static struct disp_merge_regs *const disp_merge = (void *)DISP_MERGE0_BASE; 365 366 enum { 367 SMI_LARB_PORT_L0_OVL_RDMA0 = 0x388, 368 }; 369 370 #endif 371