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/external/robolectric/shadows/framework/src/main/java/org/robolectric/android/
DDeviceConfig.java6 import android.content.res.Configuration;
17 * Supports device configuration for Robolectric tests.
19 * @see <a href="http://robolectric.org/device-configuration/">Device Configuration</a>
34 small(320, 426, Configuration.SCREENLAYOUT_SIZE_SMALL),
35 normal(320, 470, Configuration.SCREENLAYOUT_SIZE_NORMAL),
36 large(480, 640, Configuration.SCREENLAYOUT_SIZE_LARGE),
37 xlarge(720, 960, Configuration.SCREENLAYOUT_SIZE_XLARGE);
71 case Configuration.SCREENLAYOUT_SIZE_SMALL: in find()
73 case Configuration.SCREENLAYOUT_SIZE_NORMAL: in find()
75 case Configuration.SCREENLAYOUT_SIZE_LARGE: in find()
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DConfigurationV25.java3 import static android.content.res.Configuration.DENSITY_DPI_ANY;
4 import static android.content.res.Configuration.DENSITY_DPI_NONE;
5 import static android.content.res.Configuration.DENSITY_DPI_UNDEFINED;
7 import android.content.res.Configuration;
19 …e.com/platform/frameworks/base/+/android-9.0.0_r12/core/java/android/content/res/Configuration.java
65 Configuration config, DisplayMetrics displayMetrics) { in resourceQualifierString()
83 switch (config.screenLayout & Configuration.SCREENLAYOUT_LAYOUTDIR_MASK) { in resourceQualifierString()
84 case Configuration.SCREENLAYOUT_LAYOUTDIR_LTR: in resourceQualifierString()
87 case Configuration.SCREENLAYOUT_LAYOUTDIR_RTL: in resourceQualifierString()
106 switch (config.screenLayout & Configuration.SCREENLAYOUT_SIZE_MASK) { in resourceQualifierString()
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/external/robolectric/robolectric/src/test/java/org/robolectric/android/
DBootstrapTest.java3 import static android.content.res.Configuration.COLOR_MODE_HDR_MASK;
4 import static android.content.res.Configuration.COLOR_MODE_HDR_NO;
5 import static android.content.res.Configuration.COLOR_MODE_WIDE_COLOR_GAMUT_MASK;
6 import static android.content.res.Configuration.COLOR_MODE_WIDE_COLOR_GAMUT_NO;
7 import static android.content.res.Configuration.KEYBOARDHIDDEN_SOFT;
8 import static android.content.res.Configuration.KEYBOARDHIDDEN_YES;
9 import static android.content.res.Configuration.KEYBOARD_12KEY;
10 import static android.content.res.Configuration.KEYBOARD_NOKEYS;
11 import static android.content.res.Configuration.NAVIGATIONHIDDEN_YES;
12 import static android.content.res.Configuration.NAVIGATION_DPAD;
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/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/
DPciLib.h2 Provides services to access PCI Configuration Space.
4 These functions perform PCI configuration cycles using the default PCI configuration
5 access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
7 alternate access method. Modules will typically use the PCI Library for its PCI configuration
38 Registers a PCI device so PCI configuration registers may be accessed after
41 Registers the PCI device specified by Address so all the PCI configuration registers
65 Reads an 8-bit PCI configuration register.
67 Reads and returns the 8-bit PCI configuration register specified by Address.
76 @return The read value from the PCI configuration register.
86 Writes an 8-bit PCI configuration register.
[all …]
DPciSegmentLib.h2 Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
4 The PCI Segment Library function provide services to read, write, and modify the PCI configuration
20 These functions perform PCI configuration cycles using the default PCI configuration access
21 method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
23 access method. Modules will typically use the PCI Segment Library for its PCI configuration
67 Register a PCI device so PCI configuration registers may be accessed after
91 Reads an 8-bit PCI configuration register.
93 Reads and returns the 8-bit PCI configuration register specified by Address.
100 @return The 8-bit PCI configuration register specified by Address.
110 Writes an 8-bit PCI configuration register.
[all …]
DPciExpressLib.h2 Provides services to access PCI Configuration Space using the MMIO PCI Express window.
5 configuration cycles must be through the PCI Express MMIO window whose base address
38 Registers a PCI device so PCI configuration registers may be accessed after
41 Registers the PCI device specified by Address so all the PCI configuration
66 Reads an 8-bit PCI configuration register.
68 Reads and returns the 8-bit PCI configuration register specified by Address.
77 @return The read value from the PCI configuration register.
87 Writes an 8-bit PCI configuration register.
89 Writes the 8-bit PCI configuration register specified by Address with the
99 @return The value written to the PCI configuration register.
[all …]
DPciCf8Lib.h2 Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
5 configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows
36 Registers a PCI device so PCI configuration registers may be accessed after
39 Registers the PCI device specified by Address so all the PCI configuration registers
64 Reads an 8-bit PCI configuration register.
66 Reads and returns the 8-bit PCI configuration register specified by Address.
76 @return The read value from the PCI configuration register.
86 Writes an 8-bit PCI configuration register.
88 Writes the 8-bit PCI configuration register specified by Address with the
99 @return The value written to the PCI configuration register.
[all …]
/external/coreboot/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/
DPciLib.h2 Provides services to access PCI Configuration Space.
4 These functions perform PCI configuration cycles using the default PCI configuration
5 access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
7 alternate access method. Modules will typically use the PCI Library for its PCI configuration
44 Registers a PCI device so PCI configuration registers may be accessed after
47 Registers the PCI device specified by Address so all the PCI configuration registers
71 Reads an 8-bit PCI configuration register.
73 Reads and returns the 8-bit PCI configuration register specified by Address.
82 @return The read value from the PCI configuration register.
92 Writes an 8-bit PCI configuration register.
[all …]
DPciExpressLib.h2 Provides services to access PCI Configuration Space using the MMIO PCI Express window.
5 configuration cycles must be through the 256 MB PCI Express MMIO window whose base address
43 Registers a PCI device so PCI configuration registers may be accessed after
46 Registers the PCI device specified by Address so all the PCI configuration
71 Reads an 8-bit PCI configuration register.
73 Reads and returns the 8-bit PCI configuration register specified by Address.
82 @return The read value from the PCI configuration register.
92 Writes an 8-bit PCI configuration register.
94 Writes the 8-bit PCI configuration register specified by Address with the
104 @return The value written to the PCI configuration register.
[all …]
DPciSegmentLib.h2 Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
4 The PCI Segment Library function provide services to read, write, and modify the PCI configuration
20 These functions perform PCI configuration cycles using the default PCI configuration access
21 method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
23 access method. Modules will typically use the PCI Segment Library for its PCI configuration
74 Register a PCI device so PCI configuration registers may be accessed after
98 Reads an 8-bit PCI configuration register.
100 Reads and returns the 8-bit PCI configuration register specified by Address.
107 @return The 8-bit PCI configuration register specified by Address.
117 Writes an 8-bit PCI configuration register.
[all …]
DPciCf8Lib.h2 Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
5 configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows
43 Registers a PCI device so PCI configuration registers may be accessed after
46 Registers the PCI device specified by Address so all the PCI configuration registers
71 Reads an 8-bit PCI configuration register.
73 Reads and returns the 8-bit PCI configuration register specified by Address.
83 @return The read value from the PCI configuration register.
93 Writes an 8-bit PCI configuration register.
95 Writes the 8-bit PCI configuration register specified by Address with the
106 @return The value written to the PCI configuration register.
[all …]
/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/
DPciLib.h2 Provides services to access PCI Configuration Space.
4 These functions perform PCI configuration cycles using the default PCI configuration
5 access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
7 alternate access method. Modules will typically use the PCI Library for its PCI configuration
38 Registers a PCI device so PCI configuration registers may be accessed after
41 Registers the PCI device specified by Address so all the PCI configuration registers
65 Reads an 8-bit PCI configuration register.
67 Reads and returns the 8-bit PCI configuration register specified by Address.
76 @return The read value from the PCI configuration register.
86 Writes an 8-bit PCI configuration register.
[all …]
DPciSegmentLib.h2 Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
4 The PCI Segment Library function provide services to read, write, and modify the PCI configuration
20 These functions perform PCI configuration cycles using the default PCI configuration access
21 method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
23 access method. Modules will typically use the PCI Segment Library for its PCI configuration
68 Register a PCI device so PCI configuration registers may be accessed after
92 Reads an 8-bit PCI configuration register.
94 Reads and returns the 8-bit PCI configuration register specified by Address.
101 @return The 8-bit PCI configuration register specified by Address.
111 Writes an 8-bit PCI configuration register.
[all …]
DPciExpressLib.h2 Provides services to access PCI Configuration Space using the MMIO PCI Express window.
5 configuration cycles must be through the PCI Express MMIO window whose base address
38 Registers a PCI device so PCI configuration registers may be accessed after
41 Registers the PCI device specified by Address so all the PCI configuration
66 Reads an 8-bit PCI configuration register.
68 Reads and returns the 8-bit PCI configuration register specified by Address.
77 @return The read value from the PCI configuration register.
87 Writes an 8-bit PCI configuration register.
89 Writes the 8-bit PCI configuration register specified by Address with the
99 @return The value written to the PCI configuration register.
[all …]
DPciCf8Lib.h2 Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
5 configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows
37 Registers a PCI device so PCI configuration registers may be accessed after
40 Registers the PCI device specified by Address so all the PCI configuration registers
65 Reads an 8-bit PCI configuration register.
67 Reads and returns the 8-bit PCI configuration register specified by Address.
77 @return The read value from the PCI configuration register.
87 Writes an 8-bit PCI configuration register.
89 Writes the 8-bit PCI configuration register specified by Address with the
100 @return The value written to the PCI configuration register.
[all …]
/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/
DPciLib.h2 Provides services to access PCI Configuration Space.
4 These functions perform PCI configuration cycles using the default PCI configuration
5 access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
7 alternate access method. Modules will typically use the PCI Library for its PCI configuration
38 Registers a PCI device so PCI configuration registers may be accessed after
41 Registers the PCI device specified by Address so all the PCI configuration registers
65 Reads an 8-bit PCI configuration register.
67 Reads and returns the 8-bit PCI configuration register specified by Address.
76 @return The read value from the PCI configuration register.
86 Writes an 8-bit PCI configuration register.
[all …]
DPciSegmentLib.h2 Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
4 The PCI Segment Library function provide services to read, write, and modify the PCI configuration
20 These functions perform PCI configuration cycles using the default PCI configuration access
21 method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
23 access method. Modules will typically use the PCI Segment Library for its PCI configuration
68 Register a PCI device so PCI configuration registers may be accessed after
92 Reads an 8-bit PCI configuration register.
94 Reads and returns the 8-bit PCI configuration register specified by Address.
101 @return The 8-bit PCI configuration register specified by Address.
111 Writes an 8-bit PCI configuration register.
[all …]
DPciExpressLib.h2 Provides services to access PCI Configuration Space using the MMIO PCI Express window.
5 configuration cycles must be through the 256 MB PCI Express MMIO window whose base address
37 Registers a PCI device so PCI configuration registers may be accessed after
40 Registers the PCI device specified by Address so all the PCI configuration
65 Reads an 8-bit PCI configuration register.
67 Reads and returns the 8-bit PCI configuration register specified by Address.
76 @return The read value from the PCI configuration register.
86 Writes an 8-bit PCI configuration register.
88 Writes the 8-bit PCI configuration register specified by Address with the
98 @return The value written to the PCI configuration register.
[all …]
DPciCf8Lib.h2 Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
5 configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows
37 Registers a PCI device so PCI configuration registers may be accessed after
40 Registers the PCI device specified by Address so all the PCI configuration registers
65 Reads an 8-bit PCI configuration register.
67 Reads and returns the 8-bit PCI configuration register specified by Address.
77 @return The read value from the PCI configuration register.
87 Writes an 8-bit PCI configuration register.
89 Writes the 8-bit PCI configuration register specified by Address with the
100 @return The value written to the PCI configuration register.
[all …]
DS3PciSegmentLib.h2 The multiple segments PCI configuration Library Services that carry out
3 PCI configuration and enable the PCI operations to be replayed during an
48 Reads an 8-bit PCI configuration register, and saves the value in the S3 script to
51 Reads and returns the 8-bit PCI configuration register specified by Address.
58 @return The 8-bit PCI configuration register specified by Address.
68 Writes an 8-bit PCI configuration register, and saves the value in the S3 script to
71 …Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
79 @return The value written to the PCI configuration register.
90 Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves
93 Reads the 8-bit PCI configuration register specified by Address,
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/external/libusb/msvc/
DProjectConfigurations.Base.props5 <Configuration>Debug</Configuration>
9 <Configuration>Debug</Configuration>
13 <Configuration>Debug</Configuration>
17 <Configuration>Debug</Configuration>
21 <Configuration>Release</Configuration>
25 <Configuration>Release</Configuration>
29 <Configuration>Release</Configuration>
33 <Configuration>Release</Configuration>
37 <Configuration>Debug-MT</Configuration>
41 <Configuration>Debug-MT</Configuration>
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/external/ms-tpm-20-ref/TPMCmd/Platform/
Dplatform.vcxproj5 <Configuration>Debug</Configuration>
9 <Configuration>Debug</Configuration>
13 <Configuration>Release</Configuration>
17 <Configuration>Release</Configuration>
21 <Configuration>Static</Configuration>
25 <Configuration>Static</Configuration>
29 <Configuration>WolfDebug</Configuration>
33 <Configuration>WolfDebug</Configuration>
37 <Configuration>WolfRelease</Configuration>
41 <Configuration>WolfRelease</Configuration>
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/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/
DIp4Config2.h2 This file provides a definition of the EFI IPv4 Configuration II
31 /// IPv4 Configuration II Protocol instance manages. This type of
37 /// The general configuration policy for the EFI IPv4 network stack
39 /// Configuration II Protocol instance manages. The policy will
40 /// affect other configuration settings. The corresponding Data is of
49 /// is 0 and Data is NULL, the existing configuration is cleared
50 /// from the EFI IPv4 Configuration II Protocol instance.
56 /// Configuration II Protocol manages. It is not configurable when
60 /// When DataSize is 0 and Data is NULL, the existing configuration
61 /// is cleared from the EFI IPv4 Configuration II Protocol instance.
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/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/
DIp4Config2.h2 This file provides a definition of the EFI IPv4 Configuration II
31 /// IPv4 Configuration II Protocol instance manages. This type of
37 /// The general configuration policy for the EFI IPv4 network stack
39 /// Configuration II Protocol instance manages. The policy will
40 /// affect other configuration settings. The corresponding Data is of
49 /// is 0 and Data is NULL, the existing configuration is cleared
50 /// from the EFI IPv4 Configuration II Protocol instance.
56 /// Configuration II Protocol manages. It is not configurable when
60 /// When DataSize is 0 and Data is NULL, the existing configuration
61 /// is cleared from the EFI IPv4 Configuration II Protocol instance.
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/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/
DIp4Config2.h2 This file provides a definition of the EFI IPv4 Configuration II
31 /// IPv4 Configuration II Protocol instance manages. This type of
37 /// The general configuration policy for the EFI IPv4 network stack
39 /// Configuration II Protocol instance manages. The policy will
40 /// affect other configuration settings. The corresponding Data is of
49 /// is 0 and Data is NULL, the existing configuration is cleared
50 /// from the EFI IPv4 Configuration II Protocol instance.
56 /// Configuration II Protocol manages. It is not configurable when
60 /// When DataSize is 0 and Data is NULL, the existing configuration
61 /// is cleared from the EFI IPv4 Configuration II Protocol instance.
[all …]

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