| /external/elfutils/tests/ |
| D | run-show-die-info.sh | 28 Offset : 11
29 CU offset : 11
38 Offset : 104
39 CU offset : 104
45 Offset : 127
46 CU offset : 127
52 Offset : 146
53 CU offset : 11
62 Offset : 239
63 CU offset : 104
[all …]
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| D | run-show-abbrev.sh | 25 abbrev[0]: attr[0]: code = 16, form = 6, offset = 0
26 abbrev[0]: attr[1]: code = 18, form = 1, offset = 2
27 abbrev[0]: attr[2]: code = 17, form = 1, offset = 4
28 abbrev[0]: attr[3]: code = 3, form = 8, offset = 6
29 abbrev[0]: attr[4]: code = 27, form = 8, offset = 8
30 abbrev[0]: attr[5]: code = 37, form = 8, offset = 10
31 abbrev[0]: attr[6]: code = 19, form = 11, offset = 12
33 abbrev[19]: attr[0]: code = 1, form = 19, offset = 19
34 abbrev[19]: attr[1]: code = 63, form = 12, offset = 21
35 abbrev[19]: attr[2]: code = 3, form = 8, offset = 23
[all …]
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| /external/mesa3d/src/intel/vulkan/grl/gpu/libs/ |
| D | lsc_intrinsics_fallback.cl | 10 uint load_uchar_to_uint_L1UC_L3UC(global uchar* it, int offset)
12 return (uint)(it[offset]);
15 uint load_uchar_to_uint_L1UC_L3C(global uchar* it, int offset)
17 return (uint)(it[offset]);
20 uint load_uchar_to_uint_L1C_L3UC(global uchar* it, int offset)
22 return (uint)(it[offset]);
25 uint load_uchar_to_uint_L1C_L3C(global uchar* it, int offset)
27 return (uint)(it[offset]);
30 uint load_uchar_to_uint_L1S_L3UC(global uchar* it, int offset)
32 return (uint)(it[offset]);
[all …]
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| D | lsc_intrinsics.h | 9 uint load_uchar_to_uint_L1UC_L3UC(global uchar* it, int offset);
10 uint load_uchar_to_uint_L1UC_L3C(global uchar* it, int offset);
11 uint load_uchar_to_uint_L1C_L3UC(global uchar* it, int offset);
12 uint load_uchar_to_uint_L1C_L3C(global uchar* it, int offset);
13 uint load_uchar_to_uint_L1S_L3UC(global uchar* it, int offset);
14 uint load_uchar_to_uint_L1S_L3C(global uchar* it, int offset);
15 uint load_uchar_to_uint_L1IAR_L3C(global uchar* it, int offset);
17 uint load_ushort_to_uint_L1UC_L3UC(global ushort* it, int offset);
18 uint load_ushort_to_uint_L1UC_L3C(global ushort* it, int offset);
19 uint load_ushort_to_uint_L1C_L3UC(global ushort* it, int offset);
[all …]
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| D | lsc_intrinsics.cl | 143 uint load_uchar_to_uint_L1UC_L3UC(global uchar* it, int offset)
145 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1UC_L3UC);
148 uint load_uchar_to_uint_L1UC_L3C(global uchar* it, int offset)
150 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1UC_L3C);
153 uint load_uchar_to_uint_L1C_L3UC(global uchar* it, int offset)
155 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1C_L3UC);
158 uint load_uchar_to_uint_L1C_L3C(global uchar* it, int offset)
160 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1C_L3C);
163 uint load_uchar_to_uint_L1S_L3UC(global uchar* it, int offset)
165 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1S_L3UC);
[all …]
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| /external/mesa3d/src/freedreno/fdl/ |
| D | fd6_layout_test.c | 26 {.offset = 0, .pitch = 256},
27 {.offset = 8192, .pitch = 256},
28 {.offset = 12288, .pitch = 256},
29 {.offset = 14336, .pitch = 256},
30 {.offset = 15360, .pitch = 256},
31 {.offset = 15872, .pitch = 256},
49 {.offset = 0, .pitch = 4096},
50 {.offset = 65536, .pitch = 2048},
51 {.offset = 98304, .pitch = 1024},
52 {.offset = 114688, .pitch = 512},
[all …]
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| /external/mesa3d/src/freedreno/registers/adreno/ |
| D | a6xx_gmu.xml | 43 <reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
44 <reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
45 <reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/>
46 <reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/>
47 <reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/>
48 <reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/>
49 <reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/>
50 <reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/>
51 <reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/>
52 <reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>
[all …]
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| D | a5xx.xml | 862 <reg32 offset="0x0800" name="CP_RB_BASE"/>
863 <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
864 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
865 <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
866 <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
867 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
868 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
869 <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/>
870 <reg32 offset="0x0809" name="CP_PFP_STAT_DATA"/>
871 <reg32 offset="0x080b" name="CP_DRAW_STATE_ADDR"/>
[all …]
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| D | adreno_control_regs.xml | 20 <reg32 name="PREEMPT_INSTR" offset="0x04"/>
23 <reg32 name="SP" offset="0x05"/>
26 <reg32 name="STACK0" offset="0x08" type="hex"/>
27 <reg32 name="STACK1" offset="0x09" type="hex"/>
28 <reg32 name="STACK2" offset="0x0a" type="hex"/>
29 <reg32 name="STACK3" offset="0x0b" type="hex"/>
30 <reg32 name="STACK4" offset="0x0c" type="hex"/>
31 <reg32 name="STACK5" offset="0x0d" type="hex"/>
32 <reg32 name="STACK6" offset="0x0e" type="hex"/>
33 <reg32 name="STACK7" offset="0x0f" type="hex"/>
[all …]
|
| /external/coreboot/src/vendorcode/amd/fsp/cezanne/ |
| D | FspmUpd.h | 19 /** Offset 0x0040**/ uint32_t bert_size;
20 /** Offset 0x0044**/ uint32_t tseg_size;
21 /** Offset 0x0048**/ uint32_t pci_express_base_addr;
22 /** Offset 0x004C**/ uint8_t misc_reserved[32];
23 /** Offset 0x006C**/ uint32_t serial_port_base;
24 /** Offset 0x0070**/ uint32_t serial_port_use_mmio;
25 /** Offset 0x0074**/ uint32_t serial_port_baudrate;
26 /** Offset 0x0078**/ uint32_t serial_port_refclk;
27 /** Offset 0x007C**/ uint32_t serial_reserved;
28 …/** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][5…
[all …]
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| /external/coreboot/src/vendorcode/amd/fsp/mendocino/ |
| D | FspmUpd.h | 19 /** Offset 0x0040**/ uint32_t bert_size;
20 /** Offset 0x0044**/ uint32_t tseg_size;
21 /** Offset 0x0048**/ uint32_t pci_express_base_addr;
22 /** Offset 0x004C**/ uint8_t misc_reserved[32];
23 /** Offset 0x006C**/ uint32_t serial_port_base;
24 /** Offset 0x0070**/ uint32_t serial_port_use_mmio;
25 /** Offset 0x0074**/ uint32_t serial_port_baudrate;
26 /** Offset 0x0078**/ uint32_t serial_port_refclk;
27 /** Offset 0x007C**/ uint32_t serial_reserved;
28 …/** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][5…
[all …]
|
| /external/tpm2-tss/include/tss2/ |
| D | tss2_mu.h | 28 size_t *offset);
34 size_t *offset,
42 size_t *offset);
48 size_t *offset,
56 size_t *offset);
62 size_t *offset,
70 size_t *offset);
76 size_t *offset,
84 size_t *offset);
90 size_t *offset,
[all …]
|
| /external/coreboot/src/vendorcode/amd/fsp/glinda/ |
| D | FspmUpd.h | 21 /** Offset 0x0040**/ uint32_t bert_size;
22 /** Offset 0x0044**/ uint32_t tseg_size;
23 /** Offset 0x0048**/ uint32_t pci_express_base_addr;
24 /** Offset 0x004C**/ uint8_t misc_reserved[32];
25 /** Offset 0x006C**/ uint32_t serial_port_base;
26 /** Offset 0x0070**/ uint32_t serial_port_use_mmio;
27 /** Offset 0x0074**/ uint32_t serial_port_baudrate;
28 /** Offset 0x0078**/ uint32_t serial_port_refclk;
29 /** Offset 0x007C**/ uint32_t serial_reserved;
30 …/** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][5…
[all …]
|
| /external/coreboot/src/vendorcode/amd/fsp/phoenix/ |
| D | FspmUpd.h | 21 /** Offset 0x0040**/ uint32_t bert_size;
22 /** Offset 0x0044**/ uint32_t tseg_size;
23 /** Offset 0x0048**/ uint32_t pci_express_base_addr;
24 /** Offset 0x004C**/ uint8_t misc_reserved[32];
25 /** Offset 0x006C**/ uint32_t serial_port_base;
26 /** Offset 0x0070**/ uint32_t serial_port_use_mmio;
27 /** Offset 0x0074**/ uint32_t serial_port_baudrate;
28 /** Offset 0x0078**/ uint32_t serial_port_refclk;
29 /** Offset 0x007C**/ uint32_t serial_reserved;
30 …/** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][5…
[all …]
|
| /external/coreboot/src/vendorcode/intel/fsp/fsp1_1/braswell/ |
| D | FspUpdVpd.h | 122 /** Offset 0x0020
125 /** Offset 0x0028
128 /** Offset 0x0029
131 /** Offset 0x0030
136 /** Offset 0x0032
141 /** Offset 0x0034
146 /** Offset 0x0035
151 /** Offset 0x0036
154 /** Offset 0x0037
157 /** Offset 0x0038
[all …]
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| /external/coreboot/src/drivers/intel/gma/ |
| D | opregion.h | 18 u8 signature[16]; /* Offset 0 OpRegion signature */
19 u32 size; /* Offset 16 OpRegion size */
25 } opver; /* Offset 20 OpRegion version structure */
26 u8 sbios_version[32]; /* Offset 24 System BIOS build version */
27 u8 vbios_version[16]; /* Offset 56 Video BIOS build version */
28 u8 driver_version[16]; /* Offset 72 Graphic drvr build version */
29 u32 mailboxes; /* Offset 88 Mailboxes supported */
30 u32 dmod; /* Offset 92 Driver Model */
31 u32 pcon; /* Offset 96 Platform Capabilities */
32 u16 dver[16]; /* Offset 100 GOP Version */
[all …]
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| /external/coreboot/src/vendorcode/amd/fsp/picasso/ |
| D | FspmUpd.h | 15 /** Offset 0x0040**/ uint32_t pci_express_base_addr;
16 /** Offset 0x0044**/ uint32_t serial_port_base;
17 /** Offset 0x0048**/ uint32_t serial_port_use_mmio;
18 /** Offset 0x004C**/ uint32_t serial_port_stride;
19 /** Offset 0x0050**/ uint32_t serial_port_baudrate;
20 /** Offset 0x0054**/ uint32_t serial_port_refclk;
21 /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope_mA;
22 /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2_mA;
23 /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3_mA;
24 /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4_mA;
[all …]
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| D | FspsUpd.h | 18 /** Offset 0x0020**/ uint32_t emmc0_mode;
19 /** Offset 0x0024**/ uint16_t emmc0_init_khz_preset;
20 /** Offset 0x0026**/ uint8_t emmc0_sdr104_hs400_driver_strength;
21 /** Offset 0x0027**/ uint8_t emmc0_ddr50_driver_strength;
22 /** Offset 0x0028**/ uint8_t emmc0_sdr50_driver_strength;
23 /** Offset 0x0029**/ uint8_t unused0[7];
24 …/** Offset 0x0030**/ uint8_t dxio_descriptor[FSPS_UPD_DXIO_DESCRIPTOR_COUNT][1…
25 /** Offset 0x00B0**/ uint8_t unused1[16];
26 /** Offset 0x00C0**/ uint32_t ddi_descriptor[FSPS_UPD_DDI_DESCRIPTOR_COUNT];
27 /** Offset 0x00D0**/ uint8_t unused2[16];
[all …]
|
| /external/trusty/arm-trusted-firmware/drivers/st/ddr/phy/firmware/include/ |
| D | mnpmusrammsgblock_ddr4.h | 17 * Byte offset 0x00, CSR Addr 0x54000, Direction=In
48 * Byte offset 0x01, CSR Addr 0x54000, Direction=In
116 * Byte offset 0x02, CSR Addr 0x54001, Direction=Out
124 * Byte offset 0x04, CSR Addr 0x54002, Direction=In
133 * Byte offset 0x05, CSR Addr 0x54002, Direction=In
140 * Byte offset 0x06, CSR Addr 0x54003, Direction=In
145 * Byte offset 0x08, CSR Addr 0x54004, Direction=In
152 * Byte offset 0x09, CSR Addr 0x54004, Direction=In
163 * Byte offset 0x0a, CSR Addr 0x54005, Direction=In
177 * Byte offset 0x0b, CSR Addr 0x54005, Direction=In
[all …]
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| /external/flatbuffers/ts/ |
| D | byte-buffer.ts | 3 import { Offset, Table, IGeneratedObject, IUnpackableObject } from "./types.js";
54 readInt8(offset: number): number {
55 return this.readUint8(offset) << 24 >> 24;
58 readUint8(offset: number): number {
59 return this.bytes_[offset];
62 readInt16(offset: number): number {
63 return this.readUint16(offset) << 16 >> 16;
66 readUint16(offset: number): number {
67 return this.bytes_[offset] | this.bytes_[offset + 1] << 8;
70 readInt32(offset: number): number {
[all …]
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| /external/llvm/unittests/Support/ |
| D | DataExtractorTest.cpp | 28 uint32_t offset = 0; in TEST() local
30 EXPECT_EQ(0x80U, DE.getU8(&offset)); in TEST()
31 EXPECT_EQ(1U, offset); in TEST()
32 offset = 0; in TEST()
33 EXPECT_EQ(0x8090U, DE.getU16(&offset)); in TEST()
34 EXPECT_EQ(2U, offset); in TEST()
35 offset = 0; in TEST()
36 EXPECT_EQ(0x8090FFFFU, DE.getU32(&offset)); in TEST()
37 EXPECT_EQ(4U, offset); in TEST()
38 offset = 0; in TEST()
[all …]
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| /external/libnetfilter_conntrack/src/expect/ |
| D | snprintf_xml.c | 57 unsigned int size = 0, offset = 0; in snprintf_expect_meta_xml() local
60 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
63 ret = snprintf(buf+offset, len, in snprintf_expect_meta_xml()
66 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
69 ret = snprintf(buf+offset, len, "<timeout>%u</timeout>", in snprintf_expect_meta_xml()
71 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
74 ret = snprintf(buf+offset, len, "<class>%u</class>", in snprintf_expect_meta_xml()
76 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
79 ret = snprintf(buf+offset, len, "<zone>%u</zone>", exp->zone); in snprintf_expect_meta_xml()
80 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
[all …]
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| /external/flatbuffers/tests/ts/no_import_ext/optional-scalars/ |
| D | scalar-stuff.js | 26 const offset = this.bb.__offset(this.bb_pos, 4);
27 return offset ? this.bb.readInt8(this.bb_pos + offset) : 0;
30 const offset = this.bb.__offset(this.bb_pos, 6);
31 return offset ? this.bb.readInt8(this.bb_pos + offset) : null;
34 const offset = this.bb.__offset(this.bb_pos, 8);
35 return offset ? this.bb.readInt8(this.bb_pos + offset) : 42;
38 const offset = this.bb.__offset(this.bb_pos, 10);
39 return offset ? this.bb.readUint8(this.bb_pos + offset) : 0;
42 const offset = this.bb.__offset(this.bb_pos, 12);
43 return offset ? this.bb.readUint8(this.bb_pos + offset) : null;
[all …]
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-memop-immediate-512-a32.cc | 73 int32_t offset; member
100 const TestData kTests[] = {{{pl, r13, r0, plus, 0, Offset},
103 "pl r13 r0 plus 0 Offset",
105 {{ge, r5, r3, plus, 0, Offset},
108 "ge r5 r3 plus 0 Offset",
110 {{cc, r0, r4, plus, 0, Offset},
113 "cc r0 r4 plus 0 Offset",
115 {{ge, r0, r0, plus, 0, Offset},
118 "ge r0 r0 plus 0 Offset",
120 {{eq, r12, r3, plus, 0, Offset},
[all …]
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| D | test-assembler-cond-rd-memop-immediate-8192-a32.cc | 73 int32_t offset; member
100 const TestData kTests[] = {{{pl, r13, r0, plus, 0, Offset},
103 "pl r13 r0 plus 0 Offset",
105 {{ge, r5, r3, plus, 0, Offset},
108 "ge r5 r3 plus 0 Offset",
110 {{cc, r0, r4, plus, 0, Offset},
113 "cc r0 r4 plus 0 Offset",
115 {{ge, r0, r0, plus, 0, Offset},
118 "ge r0 r0 plus 0 Offset",
120 {{eq, r12, r3, plus, 0, Offset},
[all …]
|