1FLASH 16M { 2 SI_ALL 3712K { 3 SI_DESC 4K 4 SI_ME 5 } 6 SI_BIOS 12672K { 7 RW_SECTION_A 3700K { 8 VBLOCK_A 8K 9 FW_MAIN_A(CBFS) 10 RW_FWID_A 64 11 } 12 RW_LEGACY(CBFS) 1M 13 RW_MISC 152K { 14 UNIFIED_MRC_CACHE(PRESERVE) 128K { 15 RECOVERY_MRC_CACHE 64K 16 RW_MRC_CACHE 64K 17 } 18 RW_ELOG(PRESERVE) 4K 19 RW_SHARED 4K { 20 SHARED_DATA 4K 21 } 22 RW_VPD(PRESERVE) 8K 23 RW_NVRAM(PRESERVE) 8K 24 } 25 RW_SECTION_B 3700K { 26 VBLOCK_B 8K 27 FW_MAIN_B(CBFS) 28 RW_FWID_B 64 29 } 30 # Make WP_RO region align with SPI vendor 31 # memory protected range specification. 32 WP_RO 4M { 33 RO_VPD(PRESERVE) 16K 34 RO_GSCVD 8K 35 RO_SECTION { 36 FMAP 2K 37 RO_FRID 64 38 GBB@4K 12K 39 COREBOOT(CBFS) 40 } 41 } 42 } 43} 44