1FLASH@0xff000000 0x1000000 { 2 SI_ALL@0x0 0x381000 { 3 SI_DESC@0x0 0x1000 4 SI_EC@0x1000 0x80000 5 SI_ME@0x81000 0x300000 6 } 7 SI_BIOS@0x381000 0xc7f000 { 8 RW_LEGACY(CBFS)@0x0 0x100000 9 RW_SECTION_A@0x100000 0x3a4800 { 10 VBLOCK_A@0x0 0x2000 11 FW_MAIN_A(CBFS)@0x2000 0x3a27c0 12 RW_FWID_A@0x3a47c0 0x40 13 } 14 RW_SECTION_B@0x4a4800 0x3a4800 { 15 VBLOCK_B@0x0 0x2000 16 FW_MAIN_B(CBFS)@0x2000 0x3a27c0 17 RW_FWID_B@0x3a47c0 0x40 18 } 19 RW_MISC@0x849000 0x36000 { 20 UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { 21 RECOVERY_MRC_CACHE@0x0 0x10000 22 RW_MRC_CACHE@0x10000 0x20000 23 } 24 RW_ELOG(PRESERVE)@0x30000 0x1000 25 RW_SHARED@0x31000 0x1000 { 26 SHARED_DATA@0x0 0x1000 27 } 28 RW_VPD(PRESERVE)@0x32000 0x2000 29 RW_NVRAM(PRESERVE)@0x34000 0x2000 30 } 31 # Make WP_RO region align with SPI vendor 32 # memory protected range specification. 33 WP_RO@0x87f000 0x400000 { 34 RO_VPD(PRESERVE)@0x0 0x4000 35 RO_SECTION@0x4000 0x3fc000 { 36 FMAP@0x0 0x800 37 RO_FRID@0x800 0x40 38 RO_FRID_PAD@0x840 0x7c0 39 GBB@0x1000 0x3000 40 COREBOOT(CBFS)@0x4000 0x3f8000 41 } 42 } 43 } 44} 45