1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <bootblock_common.h>
4 #include <device/pnp_ops.h>
5 #include <superio/nuvoton/common/nuvoton.h>
6 #include <superio/nuvoton/nct6687d/nct6687d.h>
7
8 #define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1)
9 #define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR)
10
bootblock_mainboard_early_init(void)11 void bootblock_mainboard_early_init(void)
12 {
13 /* Replicate vendor settings for multi-function pins in global config LDN */
14 nuvoton_pnp_enter_conf_state(SERIAL_DEV);
15 pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low
16 pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low
17
18 /* Below are multi-pin function */
19 pnp_write_config(SERIAL_DEV, 0x15, 0xaa);
20 pnp_write_config(SERIAL_DEV, 0x1a, 0x02);
21 pnp_write_config(SERIAL_DEV, 0x1b, 0x02);
22 pnp_write_config(SERIAL_DEV, 0x1d, 0x00);
23 pnp_write_config(SERIAL_DEV, 0x1e, 0xaa);
24 pnp_write_config(SERIAL_DEV, 0x1f, 0xb2);
25 pnp_write_config(SERIAL_DEV, 0x22, 0xbd);
26 pnp_write_config(SERIAL_DEV, 0x23, 0xdf);
27 pnp_write_config(SERIAL_DEV, 0x24, 0x39);
28 pnp_write_config(SERIAL_DEV, 0x25, 0xfe);
29 pnp_write_config(SERIAL_DEV, 0x26, 0x40);
30 pnp_write_config(SERIAL_DEV, 0x27, 0x77);
31 pnp_write_config(SERIAL_DEV, 0x28, 0x00);
32 pnp_write_config(SERIAL_DEV, 0x29, 0xfb);
33 pnp_write_config(SERIAL_DEV, 0x2a, 0x80);
34 pnp_write_config(SERIAL_DEV, 0x2b, 0x20);
35 pnp_write_config(SERIAL_DEV, 0x2c, 0x8a);
36 pnp_write_config(SERIAL_DEV, 0x2d, 0xaa);
37
38 pnp_set_logical_device(POWER_DEV);
39 /* Configure pin for PECI */
40 pnp_write_config(POWER_DEV, 0xf3, 0x80);
41
42 nuvoton_pnp_exit_conf_state(POWER_DEV);
43
44 if (CONFIG(CONSOLE_SERIAL))
45 nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
46 }
47