1# SPDX-License-Identifier: GPL-2.0-only 2 3chip soc/intel/cannonlake 4 register "common_soc_config" = "{ 5 // Touchpad I2C bus 6 .i2c[0] = { 7 .speed = I2C_SPEED_FAST, 8 .rise_time_ns = 80, 9 .fall_time_ns = 110, 10 }, 11 }" 12 13# CPU (soc/intel/cannonlake/cpu.c) 14 # Power limit 15 register "power_limits_config" = "{ 16 .tdp_pl1_override = 125, 17 .tdp_pl2_override = 160, 18 }" 19 20 # Enable Enhanced Intel SpeedStep 21 register "eist_enable" = "1" 22 23# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) 24 register "enable_c6dram" = "1" 25 26# FSP Silicon (soc/intel/cannonlake/fsp_params.c) 27 # Serial I/O 28 register "SerialIoDevMode" = "{ 29 [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus 30 [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console 31 }" 32 33 # Misc 34 register "AcousticNoiseMitigation" = "1" 35 36 # Power 37 register "PchPmSlpS3MinAssert" = "3" # 50ms 38 register "PchPmSlpS4MinAssert" = "1" # 1s 39 register "PchPmSlpSusMinAssert" = "4" # 4s 40 register "PchPmSlpAMinAssert" = "4" # 2s 41 42 # Thermal 43 register "tcc_offset" = "13" 44 45# PM Util (soc/intel/cannonlake/pmutil.c) 46 # GPE configuration 47 # Note that GPE events called out in ASL code rely on this 48 # route. i.e. If this route changes then the affected GPE 49 # offset bits also need to be changed. 50 register "gpe0_dw0" = "PMC_GPP_K" 51 register "gpe0_dw1" = "PMC_GPP_G" 52 register "gpe0_dw2" = "PMC_GPP_E" 53 54# Actual device tree 55 device domain 0 on 56 subsystemid 0x1558 0x7714 inherit 57 device ref peg0 on 58 # PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU) 59 register "PcieClkSrcUsage[7]" = "0x40" 60 register "PcieClkSrcClkReq[7]" = "7" 61 62 device pci 00.0 on end # VGA controller 63 device pci 00.1 on end # Audio device 64 device pci 00.2 on end # USB xHCI Host controller 65 device pci 00.3 on end # USB Type-C UCSI controller 66 end 67 device ref dptf on end 68 device ref thermal on end 69 device ref xhci on 70 register "usb2_ports" = "{ 71 [0] = USB2_PORT_MID(OC_SKIP), /* USB 3_2 */ 72 [1] = USB2_PORT_MID(OC_SKIP), /* USB 3_1 */ 73 [2] = USB2_PORT_MID(OC_SKIP), /* USB 3_4 */ 74 [3] = USB2_PORT_MID(OC_SKIP), /* USB 3_3 */ 75 [4] = USB2_PORT_MID(OC_SKIP), /* Per-key RGB */ 76 [5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C */ 77 [6] = USB2_PORT_MID(OC_SKIP), /* XFI */ 78 [7] = USB2_PORT_MID(OC_SKIP), /* Camera */ 79 [8] = USB2_PORT_MID(OC_SKIP), /* Light guide */ 80 [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */ 81 [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ 82 }" 83 register "usb3_ports" = "{ 84 [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_2 */ 85 [1] = USB3_PORT_DEFAULT(OC_SKIP), /* ANX7440 */ 86 [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_4 */ 87 [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_3 */ 88 }" 89 end 90 device ref shared_sram on end 91 device ref cnvi_wifi on 92 chip drivers/wifi/generic 93 register "wake" = "PME_B0_EN_BIT" 94 device generic 0 on end 95 end 96 end 97 device ref i2c0 on 98 chip drivers/i2c/hid 99 register "generic.hid" = ""SYNA1202"" 100 register "generic.desc" = ""Synaptics Touchpad"" 101 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" 102 register "generic.detect" = "1" 103 register "hid_desc_reg_offset" = "0x20" 104 device i2c 2c on end 105 end 106 end 107 device ref sata on 108 register "SataPortsEnable" = "{ 109 [1] = 1, /* SATA1A (SSD) */ 110 [3] = 1, /* SATA3 (M.2_SATA3) */ 111 [4] = 1, /* SATA4 (SSD2) */ 112 }" 113 end 114 device ref pcie_rp17 on 115 # PCI Express root port #17 x4, Clock 14 (SSD2) 116 register "PcieRpEnable[16]" = "1" 117 register "PcieRpLtrEnable[16]" = "1" 118 register "PcieClkSrcUsage[14]" = "16" 119 register "PcieClkSrcClkReq[14]" = "14" 120 end 121 device ref pcie_rp21 on 122 # PCI Express root port #21 x4, Clock 15 (SSD3) 123 register "PcieRpEnable[20]" = "1" 124 register "PcieRpLtrEnable[20]" = "1" 125 register "PcieClkSrcUsage[15]" = "20" 126 register "PcieClkSrcClkReq[15]" = "15" 127 end 128 device ref pcie_rp1 on 129 # PCI Express root port #1 x4, Clock 6 (Thunderbolt) 130 register "PcieRpEnable[0]" = "1" 131 register "PcieRpLtrEnable[0]" = "1" 132 register "PcieRpHotPlug[0]" = "1" 133 register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED 134 register "PcieClkSrcClkReq[6]" = "6" 135 end 136 device ref pcie_rp5 on 137 # PCI Express root port #5 x4, Clock 10 (USB 3.2) 138 register "PcieRpEnable[4]" = "1" 139 register "PcieRpLtrEnable[4]" = "1" 140 register "PcieClkSrcUsage[10]" = "4" 141 register "PcieClkSrcClkReq[10]" = "10" 142 end 143 device ref pcie_rp9 on 144 # PCI Express root port #9 x4, Clock 8 (SSD) 145 register "PcieRpEnable[8]" = "1" 146 register "PcieRpLtrEnable[8]" = "1" 147 register "PcieClkSrcUsage[8]" = "8" 148 register "PcieClkSrcClkReq[8]" = "8" 149 end 150 device ref pcie_rp13 on 151 # PCI Express root port #13 x1, Clock 0 (WLAN) 152 register "PcieRpEnable[12]" = "1" 153 register "PcieRpLtrEnable[12]" = "1" 154 register "PcieClkSrcUsage[0]" = "12" 155 register "PcieClkSrcClkReq[0]" = "0" 156 end 157 device ref pcie_rp14 on 158 # PCI Express root port #14 x1, Clock 1 (GLAN) 159 register "PcieRpEnable[13]" = "1" 160 register "PcieRpLtrEnable[13]" = "1" 161 register "PcieClkSrcUsage[1]" = "13" 162 register "PcieClkSrcClkReq[1]" = "1" 163 end 164 device ref pcie_rp15 on 165 # PCI Express root port #15 x1, Clock 4 (Card Reader) 166 register "PcieRpEnable[14]" = "1" 167 register "PcieRpLtrEnable[14]" = "1" 168 register "PcieClkSrcUsage[4]" = "14" 169 register "PcieClkSrcClkReq[4]" = "4" 170 end 171 device ref lpc_espi on 172 register "gen1_dec" = "0x00040069" 173 register "gen2_dec" = "0x00fc0e01" 174 register "gen3_dec" = "0x00fc0f01" 175 chip drivers/pc80/tpm 176 device pnp 0c31.0 on end 177 end 178 end 179 device ref hda on 180 register "PchHdaAudioLinkHda" = "1" 181 end 182 device ref smbus on end 183 end 184end 185