1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3#include <memlayout.h> 4 5#include <arch/header.ld> 6 7/* 8 * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. 9 * It will be returned before starting the ramstage. 10 * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. 11 */ 12#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) 13#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) 14#define DRAM_INIT_CODE(addr, size) \ 15 REGION(dram_init_code, addr, size, 4) 16 17#define DRAM_DMA(addr, size) \ 18 REGION(dram_dma, addr, size, 4K) \ 19 _ = ASSERT(size % 4K == 0, \ 20 "DRAM DMA buffer should be multiple of smallest page size (4K)!"); 21 22SECTIONS 23{ 24 SRAM_START(0x00100000) 25 VBOOT2_WORK(0x00100000, 12K) 26 TPM_LOG(0x00103000, 2K) 27 FMAP_CACHE(0x00103800, 2K) 28 WATCHDOG_TOMBSTONE(0x00104000, 4) 29 PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) 30 TIMESTAMP(0x00113c00, 1K) 31 STACK(0x00114000, 16K) 32 TTB(0x00118000, 28K) 33 DMA_COHERENT(0x0011f000, 4K) 34 SRAM_END(0x00120000) 35 36 SRAM_L2C_START(0x00200000) 37 OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) 38 BOOTBLOCK(0x00230000, 56K) 39 CBFS_MCACHE(0x0023e000, 8K) 40 DRAM_INIT_CODE(0x00240000, 208K) 41 PRERAM_CBFS_CACHE(0x00274000, 48K) 42 SRAM_L2C_END(0x00280000) 43 44 DRAM_START(0x40000000) 45 DRAM_DMA(0x40000000, 1M) 46 POSTRAM_CBFS_CACHE(0x40100000, 1M) 47 RAMSTAGE(0x40200000, 2M) 48 49 BL31(0x54600000, 0x60000) 50} 51