1 #include <stdint.h> 2 3 #include <cpuinfo.h> 4 #include <x86/api.h> 5 6 /* Intel vendor string: "GenuineIntel" */ 7 #define Genu UINT32_C(0x756E6547) 8 #define ineI UINT32_C(0x49656E69) 9 #define ntel UINT32_C(0x6C65746E) 10 11 /* AMD vendor strings: "AuthenticAMD", "AMDisbetter!", "AMD ISBETTER" */ 12 #define Auth UINT32_C(0x68747541) 13 #define enti UINT32_C(0x69746E65) 14 #define cAMD UINT32_C(0x444D4163) 15 #define AMDi UINT32_C(0x69444D41) 16 #define sbet UINT32_C(0x74656273) 17 #define ter UINT32_C(0x21726574) 18 #define AMD UINT32_C(0x20444D41) 19 #define ISBE UINT32_C(0x45425349) 20 #define TTER UINT32_C(0x52455454) 21 22 /* VIA (Centaur) vendor strings: "CentaurHauls", "VIA VIA VIA " */ 23 #define Cent UINT32_C(0x746E6543) 24 #define aurH UINT32_C(0x48727561) 25 #define auls UINT32_C(0x736C7561) 26 #define VIA UINT32_C(0x20414956) 27 28 /* Hygon vendor string: "HygonGenuine" */ 29 #define Hygo UINT32_C(0x6F677948) 30 #define nGen UINT32_C(0x6E65476E) 31 #define uine UINT32_C(0x656E6975) 32 33 /* Transmeta vendor strings: "GenuineTMx86", "TransmetaCPU" */ 34 #define ineT UINT32_C(0x54656E69) 35 #define Mx86 UINT32_C(0x3638784D) 36 #define Tran UINT32_C(0x6E617254) 37 #define smet UINT32_C(0x74656D73) 38 #define aCPU UINT32_C(0x55504361) 39 40 /* Cyrix vendor string: "CyrixInstead" */ 41 #define Cyri UINT32_C(0x69727943) 42 #define xIns UINT32_C(0x736E4978) 43 #define tead UINT32_C(0x64616574) 44 45 /* Rise vendor string: "RiseRiseRise" */ 46 #define Rise UINT32_C(0x65736952) 47 48 /* NSC vendor string: "Geode by NSC" */ 49 #define Geod UINT32_C(0x646F6547) 50 #define e_by UINT32_C(0x79622065) 51 #define NSC UINT32_C(0x43534E20) 52 53 /* SiS vendor string: "SiS SiS SiS " */ 54 #define SiS UINT32_C(0x20536953) 55 56 /* NexGen vendor string: "NexGenDriven" */ 57 #define NexG UINT32_C(0x4778654E) 58 #define enDr UINT32_C(0x72446E65) 59 #define iven UINT32_C(0x6E657669) 60 61 /* UMC vendor string: "UMC UMC UMC " */ 62 #define UMC UINT32_C(0x20434D55) 63 64 /* RDC vendor string: "Genuine RDC" */ 65 #define ine UINT32_C(0x20656E69) 66 #define RDC UINT32_C(0x43445220) 67 68 /* D&MP vendor string: "Vortex86 SoC" */ 69 #define Vort UINT32_C(0x74726F56) 70 #define ex86 UINT32_C(0x36387865) 71 #define SoC UINT32_C(0x436F5320) 72 cpuinfo_x86_decode_vendor(uint32_t ebx,uint32_t ecx,uint32_t edx)73enum cpuinfo_vendor cpuinfo_x86_decode_vendor(uint32_t ebx, uint32_t ecx, uint32_t edx) { 74 switch (ebx) { 75 case Genu: 76 switch (edx) { 77 case ineI: 78 if (ecx == ntel) { 79 /* "GenuineIntel" */ 80 return cpuinfo_vendor_intel; 81 } 82 break; 83 #if CPUINFO_ARCH_X86 84 case ineT: 85 if (ecx == Mx86) { 86 /* "GenuineTMx86" */ 87 return cpuinfo_vendor_transmeta; 88 } 89 break; 90 case ine: 91 if (ecx == RDC) { 92 /* "Genuine RDC" */ 93 return cpuinfo_vendor_rdc; 94 } 95 break; 96 #endif 97 } 98 break; 99 case Auth: 100 if (edx == enti && ecx == cAMD) { 101 /* "AuthenticAMD" */ 102 return cpuinfo_vendor_amd; 103 } 104 break; 105 case Cent: 106 if (edx == aurH && ecx == auls) { 107 /* "CentaurHauls" */ 108 return cpuinfo_vendor_via; 109 } 110 break; 111 case Hygo: 112 if (edx == nGen && ecx == uine) { 113 /* "HygonGenuine" */ 114 return cpuinfo_vendor_hygon; 115 } 116 break; 117 #if CPUINFO_ARCH_X86 118 case AMDi: 119 if (edx == sbet && ecx == ter) { 120 /* "AMDisbetter!" */ 121 return cpuinfo_vendor_amd; 122 } 123 break; 124 case AMD: 125 if (edx == ISBE && ecx == TTER) { 126 /* "AMD ISBETTER" */ 127 return cpuinfo_vendor_amd; 128 } 129 break; 130 case VIA: 131 if (edx == VIA && ecx == VIA) { 132 /* "VIA VIA VIA " */ 133 return cpuinfo_vendor_via; 134 } 135 break; 136 case Tran: 137 if (edx == smet && ecx == aCPU) { 138 /* "TransmetaCPU" */ 139 return cpuinfo_vendor_transmeta; 140 } 141 break; 142 case Cyri: 143 if (edx == xIns && ecx == tead) { 144 /* "CyrixInstead" */ 145 return cpuinfo_vendor_cyrix; 146 } 147 break; 148 case Rise: 149 if (edx == Rise && ecx == Rise) { 150 /* "RiseRiseRise" */ 151 return cpuinfo_vendor_rise; 152 } 153 break; 154 case Geod: 155 if (edx == e_by && ecx == NSC) { 156 /* "Geode by NSC" */ 157 return cpuinfo_vendor_nsc; 158 } 159 break; 160 case SiS: 161 if (edx == SiS && ecx == SiS) { 162 /* "SiS SiS SiS " */ 163 return cpuinfo_vendor_sis; 164 } 165 break; 166 case NexG: 167 if (edx == enDr && ecx == iven) { 168 /* "NexGenDriven" */ 169 return cpuinfo_vendor_nexgen; 170 } 171 break; 172 case UMC: 173 if (edx == UMC && ecx == UMC) { 174 /* "UMC UMC UMC " */ 175 return cpuinfo_vendor_umc; 176 } 177 break; 178 case Vort: 179 if (edx == ex86 && ecx == SoC) { 180 /* "Vortex86 SoC" */ 181 return cpuinfo_vendor_dmp; 182 } 183 break; 184 #endif 185 } 186 return cpuinfo_vendor_unknown; 187 } 188