• Home
Name Date Size #Lines LOC

..--

AsmParser/04-Jul-2025-1,3741,111

Disassembler/04-Jul-2025-688557

MCTargetDesc/04-Jul-2025-1,8671,368

TargetInfo/04-Jul-2025-8456

CMakeLists.txtD04-Jul-20251 KiB3530

DelaySlotFiller.cppD04-Jul-202514.9 KiB512346

LLVMBuild.txtD04-Jul-20251 KiB3632

LeonFeatures.tdD04-Jul-20252.1 KiB6453

LeonPasses.cppD04-Jul-20255.8 KiB15884

LeonPasses.hD04-Jul-20252.6 KiB8857

README.txtD04-Jul-20251.5 KiB5947

Sparc.hD04-Jul-20255.3 KiB167138

Sparc.tdD04-Jul-20257.3 KiB184154

SparcAsmPrinter.cppD04-Jul-202516.2 KiB447363

SparcCallingConv.tdD04-Jul-20255.7 KiB144129

SparcFrameLowering.cppD04-Jul-202513.8 KiB387252

SparcFrameLowering.hD04-Jul-20252.4 KiB6832

SparcISelDAGToDAG.cppD04-Jul-202514.2 KiB401277

SparcISelLowering.cppD04-Jul-2025133.4 KiB3,4202,543

SparcISelLowering.hD04-Jul-20259.5 KiB217152

SparcInstr64Bit.tdD04-Jul-202521.6 KiB539449

SparcInstrAliases.tdD04-Jul-202521.2 KiB524411

SparcInstrFormats.tdD04-Jul-202510.4 KiB369302

SparcInstrInfo.cppD04-Jul-202518.9 KiB510401

SparcInstrInfo.hD04-Jul-20254.1 KiB10857

SparcInstrInfo.tdD04-Jul-202568.4 KiB1,7161,480

SparcInstrVIS.tdD04-Jul-202511.1 KiB263219

SparcMCInstLower.cppD04-Jul-20253.3 KiB10875

SparcMachineFunctionInfo.cppD04-Jul-2025476 143

SparcMachineFunctionInfo.hD04-Jul-20251.9 KiB5629

SparcRegisterInfo.cppD04-Jul-20258.2 KiB241155

SparcRegisterInfo.hD04-Jul-20251.7 KiB5023

SparcRegisterInfo.tdD04-Jul-202514 KiB379344

SparcSchedule.tdD04-Jul-20256.4 KiB124117

SparcSubtarget.cppD04-Jul-20253.2 KiB10358

SparcSubtarget.hD04-Jul-20254.1 KiB12686

SparcTargetMachine.cppD04-Jul-20257.7 KiB219152

SparcTargetMachine.hD04-Jul-20252.8 KiB7950

SparcTargetObjectFile.cppD04-Jul-20251.9 KiB4829

SparcTargetObjectFile.hD04-Jul-20251.1 KiB3720

README.txt

1To-do
2-----
3
4* Keep the address of the constant pool in a register instead of forming its
5  address all of the time.
6* We can fold small constant offsets into the %hi/%lo references to constant
7  pool addresses as well.
8* When in V9 mode, register allocate %icc[0-3].
9* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
10* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
11  not clear how to write a pattern for this though:
12
13float %t1(int %a, int* %p) {
14        %C = seteq int %a, 0
15        br bool %C, label %T, label %F
16T:
17        store int 123, int* %p
18        br label %F
19F:
20        ret float undef
21}
22
23codegens to this:
24
25t1:
26        save -96, %o6, %o6
271)      subcc %i0, 0, %l0
281)      bne .LBBt1_2    ! F
29        nop
30.LBBt1_1:       ! T
31        or %g0, 123, %l0
32        st %l0, [%i1]
33.LBBt1_2:       ! F
34        restore %g0, %g0, %g0
35        retl
36        nop
37
381) should be replaced with a brz in V9 mode.
39
40* Same as above, but emit conditional move on register zero (p192) in V9
41  mode.  Testcase:
42
43int %t1(int %a, int %b) {
44        %C = seteq int %a, 0
45        %D = select bool %C, int %a, int %b
46        ret int %D
47}
48
49* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
50  with the Y register, if they are faster.
51
52* Codegen bswap(load)/store(bswap) -> load/store ASI
53
54* Implement frame pointer elimination, e.g. eliminate save/restore for
55  leaf fns.
56* Fill delay slots
57
58* Use %g0 directly to materialize 0. No instruction is required.
59