Lines Matching refs:RS
733 #define RS RBS + 1 macro
734 #define RT RS
740 #define RSQ RS + 1
2146 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
2147 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
2148 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
2149 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
2150 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2151 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2152 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2153 { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2160 { "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2161 { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2162 { "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2163 { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2164 { "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2165 { "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2166 { "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2167 { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2168 { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2169 { "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2170 { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2171 { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2172 { "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2173 { "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2174 { "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2333 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2334 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2335 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2336 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2337 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2338 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2339 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2340 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2341 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2342 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2343 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2344 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2345 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2347 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2349 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2350 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2351 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2352 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2353 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2354 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2355 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2356 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2357 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2358 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2360 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2361 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2362 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2363 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2364 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2365 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2366 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2367 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2368 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2369 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2370 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2371 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2372 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2373 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2380 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2382 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2383 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2384 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2385 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2386 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2387 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2388 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2389 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2390 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2391 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2392 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2393 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2394 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2395 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2396 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2397 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2398 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2399 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2400 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2401 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2402 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2403 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2405 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2406 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2407 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2408 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2409 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2410 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2411 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2412 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2413 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2414 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2415 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2416 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2417 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2418 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2420 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2421 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2422 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2423 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2424 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2425 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2426 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2433 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2434 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2435 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2436 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2437 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2438 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2439 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2440 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2441 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2442 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2444 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2445 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2446 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2447 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2448 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2449 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2450 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2457 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2458 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2459 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2460 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2461 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2462 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2463 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2464 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2465 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2466 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2468 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2469 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2470 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2471 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2472 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2473 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2474 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2475 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2476 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2477 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2478 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2479 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2480 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2481 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2482 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2483 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2485 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2486 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2487 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2488 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2489 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2490 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2491 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2492 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2493 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2494 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2495 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2496 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2498 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2499 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2500 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2501 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2502 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2503 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2504 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2505 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2506 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2507 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2508 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2509 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2511 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2512 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2513 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2514 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2515 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2516 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2518 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2519 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2520 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2521 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2522 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2523 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2525 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2526 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2527 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2528 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2529 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2530 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2531 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2532 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2534 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2535 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2537 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2538 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2539 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2540 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2542 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2543 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2544 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2545 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2547 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2548 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2549 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2550 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2551 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2552 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2553 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2554 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2556 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2557 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2558 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2559 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2561 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2562 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2563 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2564 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2566 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2567 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2568 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2569 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2571 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2572 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2573 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2574 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2576 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2578 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2579 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
3319 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3320 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3322 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3323 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3325 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3326 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3327 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3328 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3329 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3330 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3331 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3332 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3334 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3335 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3342 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3343 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3344 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3345 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3346 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3347 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3350 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3351 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3353 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3354 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3356 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3357 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3359 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3360 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3362 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3363 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3365 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3366 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3368 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3369 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3370 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3371 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3372 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3373 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3375 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3376 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3378 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3379 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3381 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3382 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3384 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3385 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3386 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3387 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3389 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3390 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3476 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3477 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3478 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3479 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3481 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3482 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3483 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3484 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3486 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3487 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3489 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3490 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3492 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3493 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3524 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3525 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3527 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3528 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3552 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3553 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3555 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3580 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3586 { "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
3588 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3589 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3590 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3591 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3597 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3621 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3622 { "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
3623 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3625 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3627 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3629 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3631 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3632 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3634 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3636 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3638 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3639 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3641 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3642 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3644 { "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
3651 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } },
3653 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3655 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3656 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3658 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3659 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3661 { "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
3663 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3683 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3685 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3687 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3689 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3690 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3692 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3693 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3695 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3732 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3733 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3737 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3739 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3740 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3744 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3746 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3773 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3774 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3787 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3788 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
4056 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
4068 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
4070 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
4072 { "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
4086 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
4087 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
4089 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
4090 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
4092 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
4098 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
4100 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
4109 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
4110 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
4111 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
4112 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
4114 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
4115 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
4116 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
4117 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
4118 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
4119 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
4120 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
4121 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
4122 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
4123 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
4124 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
4125 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
4126 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
4127 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
4128 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
4129 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
4130 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
4131 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
4132 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
4133 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
4134 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
4135 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
4136 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
4137 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
4138 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
4139 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
4140 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
4141 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
4142 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
4143 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
4144 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
4145 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
4146 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
4147 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
4148 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
4166 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
4167 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
4168 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
4169 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
4170 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
4171 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
4172 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
4173 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
4174 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
4175 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
4176 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
4177 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
4178 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
4179 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
4180 { "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
4181 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
4182 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
4183 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
4184 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
4185 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
4186 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
4187 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
4188 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
4189 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
4190 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
4191 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
4192 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
4193 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
4194 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
4195 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
4196 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
4197 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
4198 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
4199 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
4200 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
4201 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
4202 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
4203 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
4204 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
4205 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
4206 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
4207 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
4208 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
4209 { "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
4210 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
4211 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
4212 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
4213 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
4214 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
4215 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
4216 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
4217 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
4218 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
4219 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
4220 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
4221 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
4222 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
4223 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
4224 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
4225 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
4226 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
4227 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
4228 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
4229 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
4230 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
4231 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
4232 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
4233 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
4234 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
4235 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
4236 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
4237 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
4238 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
4239 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
4240 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
4241 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
4242 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
4243 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
4244 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
4245 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
4246 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
4247 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
4248 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
4249 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4250 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4251 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4252 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4253 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4254 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4255 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4256 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4257 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4258 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4259 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4260 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4261 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4262 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4263 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4264 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4265 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4266 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4267 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4268 { "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4269 { "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4270 { "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
4271 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4272 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4273 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4274 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4275 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4276 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4277 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4278 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4279 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4280 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4281 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4282 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4283 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4284 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4285 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4286 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4287 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4288 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4289 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4290 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4291 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4292 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4293 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4294 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4295 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4296 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4297 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4298 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4299 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4300 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4301 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4302 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4303 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4304 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4305 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4306 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4307 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4308 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4309 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4310 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4311 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4312 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4313 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4314 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4315 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4316 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4317 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4318 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4322 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4323 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4329 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4359 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4378 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4379 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4380 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4381 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4383 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4384 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4386 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4387 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4389 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4390 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4423 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4431 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4433 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4434 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4436 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4437 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4441 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4442 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4444 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4445 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4447 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4453 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4454 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4458 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4459 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4463 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4464 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4466 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4467 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4477 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4478 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4491 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4492 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4493 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4494 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4496 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4497 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4511 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4512 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4513 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4514 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4534 { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4536 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4538 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4539 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4541 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4542 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4544 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4545 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4546 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4547 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4549 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4551 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4557 { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4559 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4560 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4562 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4563 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4565 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4574 { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4580 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4581 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4590 { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4631 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4632 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4634 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4635 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4637 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4639 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4649 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4651 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4656 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4657 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4691 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4692 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4693 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4694 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4695 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4696 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4816 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4817 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4823 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
4825 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },