Lines Matching refs:sii
42 static uint _sb_coreidx(si_info_t *sii, uint32 sba);
43 static uint _sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba,
45 static uint32 _sb_coresba(si_info_t *sii);
46 static void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
48 #define SET_SBREG(sii, r, mask, val) \ argument
49 W_SBREG((sii), (r), ((R_SBREG((sii), (r)) & ~(mask)) | (val)))
56 #define R_SBREG(sii, sbr) sb_read_sbreg((sii), (sbr)) argument
57 #define W_SBREG(sii, sbr, v) sb_write_sbreg((sii), (sbr), (v)) argument
58 #define AND_SBREG(sii, sbr, v) W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) & (v))) argument
59 #define OR_SBREG(sii, sbr, v) W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) | (v))) argument
62 sb_read_sbreg(si_info_t *sii, volatile uint32 *sbr) in sb_read_sbreg() argument
74 if (PCMCIA(sii)) { in sb_read_sbreg()
75 INTR_OFF(sii, intr_val); in sb_read_sbreg()
77 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1); in sb_read_sbreg()
81 val = R_REG(sii->osh, sbr); in sb_read_sbreg()
83 if (PCMCIA(sii)) { in sb_read_sbreg()
85 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1); in sb_read_sbreg()
86 INTR_RESTORE(sii, intr_val); in sb_read_sbreg()
93 sb_write_sbreg(si_info_t *sii, volatile uint32 *sbr, uint32 v) in sb_write_sbreg() argument
106 if (PCMCIA(sii)) { in sb_write_sbreg()
107 INTR_OFF(sii, intr_val); in sb_write_sbreg()
109 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1); in sb_write_sbreg()
113 if (BUSTYPE(sii->pub.bustype) == PCMCIA_BUS) { in sb_write_sbreg()
115 dummy = R_REG(sii->osh, sbr); in sb_write_sbreg()
116 W_REG(sii->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff)); in sb_write_sbreg()
117 dummy = R_REG(sii->osh, sbr); in sb_write_sbreg()
118 W_REG(sii->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff)); in sb_write_sbreg()
120 dummy = R_REG(sii->osh, sbr); in sb_write_sbreg()
121 W_REG(sii->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff)); in sb_write_sbreg()
122 dummy = R_REG(sii->osh, sbr); in sb_write_sbreg()
123 W_REG(sii->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff)); in sb_write_sbreg()
126 W_REG(sii->osh, sbr, v); in sb_write_sbreg()
128 if (PCMCIA(sii)) { in sb_write_sbreg()
130 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1); in sb_write_sbreg()
131 INTR_RESTORE(sii, intr_val); in sb_write_sbreg()
138 si_info_t *sii; in sb_coreid() local
141 sii = SI_INFO(sih); in sb_coreid()
142 sb = REGS2SB(sii->curmap); in sb_coreid()
144 return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT); in sb_coreid()
150 si_info_t *sii; in sb_flag() local
153 sii = SI_INFO(sih); in sb_flag()
154 sb = REGS2SB(sii->curmap); in sb_flag()
156 return R_SBREG(sii, &sb->sbtpsflag) & SBTPS_NUM0_MASK; in sb_flag()
162 si_info_t *sii; in sb_setint() local
166 sii = SI_INFO(sih); in sb_setint()
167 sb = REGS2SB(sii->curmap); in sb_setint()
173 W_SBREG(sii, &sb->sbintvec, vec); in sb_setint()
178 _sb_coreidx(si_info_t *sii, uint32 sba) in _sb_coreidx() argument
182 for (i = 0; i < sii->numcores; i ++) in _sb_coreidx()
183 if (sba == sii->common_info->coresba[i]) in _sb_coreidx()
190 _sb_coresba(si_info_t *sii) in _sb_coresba() argument
195 switch (BUSTYPE(sii->pub.bustype)) { in _sb_coresba()
197 sbconfig_t *sb = REGS2SB(sii->curmap); in _sb_coresba()
198 sbaddr = sb_base(R_SBREG(sii, &sb->sbadmatch0)); in _sb_coresba()
203 sbaddr = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32)); in _sb_coresba()
208 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1); in _sb_coresba()
210 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1); in _sb_coresba()
212 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1); in _sb_coresba()
219 sbaddr = (uint32)(uintptr)sii->curmap; in _sb_coresba()
234 si_info_t *sii; in sb_corevendor() local
237 sii = SI_INFO(sih); in sb_corevendor()
238 sb = REGS2SB(sii->curmap); in sb_corevendor()
240 return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT); in sb_corevendor()
246 si_info_t *sii; in sb_corerev() local
250 sii = SI_INFO(sih); in sb_corerev()
251 sb = REGS2SB(sii->curmap); in sb_corerev()
252 sbidh = R_SBREG(sii, &sb->sbidhigh); in sb_corerev()
261 si_info_t *sii; in sb_core_cflags_wo() local
265 sii = SI_INFO(sih); in sb_core_cflags_wo()
266 sb = REGS2SB(sii->curmap); in sb_core_cflags_wo()
271 w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) | in sb_core_cflags_wo()
273 W_SBREG(sii, &sb->sbtmstatelow, w); in sb_core_cflags_wo()
280 si_info_t *sii; in sb_core_cflags() local
284 sii = SI_INFO(sih); in sb_core_cflags()
285 sb = REGS2SB(sii->curmap); in sb_core_cflags()
291 w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) | in sb_core_cflags()
293 W_SBREG(sii, &sb->sbtmstatelow, w); in sb_core_cflags()
299 return (R_SBREG(sii, &sb->sbtmstatelow) >> SBTML_SICF_SHIFT); in sb_core_cflags()
306 si_info_t *sii; in sb_core_sflags() local
310 sii = SI_INFO(sih); in sb_core_sflags()
311 sb = REGS2SB(sii->curmap); in sb_core_sflags()
318 w = (R_SBREG(sii, &sb->sbtmstatehigh) & ~(mask << SBTMH_SISF_SHIFT)) | in sb_core_sflags()
320 W_SBREG(sii, &sb->sbtmstatehigh, w); in sb_core_sflags()
324 return (R_SBREG(sii, &sb->sbtmstatehigh) >> SBTMH_SISF_SHIFT); in sb_core_sflags()
330 si_info_t *sii; in sb_iscoreup() local
333 sii = SI_INFO(sih); in sb_iscoreup()
334 sb = REGS2SB(sii->curmap); in sb_iscoreup()
336 return ((R_SBREG(sii, &sb->sbtmstatelow) & in sb_iscoreup()
358 si_info_t *sii; in sb_corereg() local
360 sii = SI_INFO(sih); in sb_corereg()
369 if (BUSTYPE(sii->pub.bustype) == SI_BUS) { in sb_corereg()
373 if (!sii->common_info->regs[coreidx]) { in sb_corereg()
374 sii->common_info->regs[coreidx] = in sb_corereg()
375 REG_MAP(sii->common_info->coresba[coreidx], SI_CORE_SIZE); in sb_corereg()
376 ASSERT(GOODREGS(sii->common_info->regs[coreidx])); in sb_corereg()
378 r = (uint32 *)((uchar *)sii->common_info->regs[coreidx] + regoff); in sb_corereg()
379 } else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) { in sb_corereg()
382 if ((sii->common_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) { in sb_corereg()
386 r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff); in sb_corereg()
387 } else if (sii->pub.buscoreidx == coreidx) { in sb_corereg()
392 if (SI_FAST(sii)) in sb_corereg()
393 r = (uint32 *)((char *)sii->curmap + in sb_corereg()
396 r = (uint32 *)((char *)sii->curmap + in sb_corereg()
404 INTR_OFF(sii, intr_val); in sb_corereg()
407 origidx = si_coreidx(&sii->pub); in sb_corereg()
410 r = (uint32*) ((uchar*)sb_setcoreidx(&sii->pub, coreidx) + regoff); in sb_corereg()
417 w = (R_SBREG(sii, r) & ~mask) | val; in sb_corereg()
418 W_SBREG(sii, r, w); in sb_corereg()
420 w = (R_REG(sii->osh, r) & ~mask) | val; in sb_corereg()
421 W_REG(sii->osh, r, w); in sb_corereg()
427 w = R_SBREG(sii, r); in sb_corereg()
429 if ((CHIPID(sii->pub.chip) == BCM5354_CHIP_ID) && in sb_corereg()
434 w = R_REG(sii->osh, r); in sb_corereg()
440 sb_setcoreidx(&sii->pub, origidx); in sb_corereg()
442 INTR_RESTORE(sii, intr_val); in sb_corereg()
457 _sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba, uint numcores) in _sb_scan() argument
472 for (i = 0, next = sii->numcores; i < numcores && next < SB_BUS_MAXCORES; i++, next++) { in _sb_scan()
473 sii->common_info->coresba[next] = sbba + (i * SI_CORE_SIZE); in _sb_scan()
476 if ((BUSTYPE(sii->pub.bustype) == SI_BUS) && in _sb_scan()
477 (sii->common_info->coresba[next] == sba)) { in _sb_scan()
479 sii->common_info->regs[next] = regs; in _sb_scan()
483 sii->curmap = _sb_setcoreidx(sii, next); in _sb_scan()
484 sii->curidx = next; in _sb_scan()
486 sii->common_info->coreid[next] = sb_coreid(&sii->pub); in _sb_scan()
490 if (sii->common_info->coreid[next] == CC_CORE_ID) { in _sb_scan()
491 chipcregs_t *cc = (chipcregs_t *)sii->curmap; in _sb_scan()
492 uint32 ccrev = sb_corerev(&sii->pub); in _sb_scan()
496 numcores = (R_REG(sii->osh, &cc->chipid) & CID_CC_MASK) >> in _sb_scan()
500 uint chip = sii->pub.chip; in _sb_scan()
516 sii->pub.issim ? "QT" : "")); in _sb_scan()
519 else if (sii->common_info->coreid[next] == OCP_CORE_ID) { in _sb_scan()
520 sbconfig_t *sb = REGS2SB(sii->curmap); in _sb_scan()
521 uint32 nsbba = R_SBREG(sii, &sb->sbadmatch1); in _sb_scan()
524 sii->numcores = next + 1; in _sb_scan()
529 if (_sb_coreidx(sii, nsbba) != BADIDX) in _sb_scan()
532 nsbcc = (R_SBREG(sii, &sb->sbtmstatehigh) & 0x000f0000) >> 16; in _sb_scan()
533 nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc); in _sb_scan()
542 sii->numcores = i + ncc; in _sb_scan()
543 return sii->numcores; in _sb_scan()
550 si_info_t *sii; in sb_scan() local
553 sii = SI_INFO(sih); in sb_scan()
558 origsba = _sb_coresba(sii); in sb_scan()
561 sii->numcores = _sb_scan(sii, origsba, regs, 0, SI_ENUM_BASE, 1); in sb_scan()
572 si_info_t *sii; in sb_setcoreidx() local
574 sii = SI_INFO(sih); in sb_setcoreidx()
576 if (coreidx >= sii->numcores) in sb_setcoreidx()
583 ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg)); in sb_setcoreidx()
585 sii->curmap = _sb_setcoreidx(sii, coreidx); in sb_setcoreidx()
586 sii->curidx = coreidx; in sb_setcoreidx()
588 return (sii->curmap); in sb_setcoreidx()
595 _sb_setcoreidx(si_info_t *sii, uint coreidx) in _sb_setcoreidx() argument
597 uint32 sbaddr = sii->common_info->coresba[coreidx]; in _sb_setcoreidx()
600 switch (BUSTYPE(sii->pub.bustype)) { in _sb_setcoreidx()
603 if (!sii->common_info->regs[coreidx]) { in _sb_setcoreidx()
604 sii->common_info->regs[coreidx] = REG_MAP(sbaddr, SI_CORE_SIZE); in _sb_setcoreidx()
605 ASSERT(GOODREGS(sii->common_info->regs[coreidx])); in _sb_setcoreidx()
607 regs = sii->common_info->regs[coreidx]; in _sb_setcoreidx()
612 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, sbaddr); in _sb_setcoreidx()
613 regs = sii->curmap; in _sb_setcoreidx()
618 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1); in _sb_setcoreidx()
620 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1); in _sb_setcoreidx()
622 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1); in _sb_setcoreidx()
623 regs = sii->curmap; in _sb_setcoreidx()
629 if (!sii->common_info->regs[coreidx]) { in _sb_setcoreidx()
630 sii->common_info->regs[coreidx] = (void *)(uintptr)sbaddr; in _sb_setcoreidx()
631 ASSERT(GOODREGS(sii->common_info->regs[coreidx])); in _sb_setcoreidx()
633 regs = sii->common_info->regs[coreidx]; in _sb_setcoreidx()
648 sb_admatch(si_info_t *sii, uint asidx) in sb_admatch() argument
653 sb = REGS2SB(sii->curmap); in sb_admatch()
684 si_info_t *sii; in sb_numaddrspaces() local
687 sii = SI_INFO(sih); in sb_numaddrspaces()
688 sb = REGS2SB(sii->curmap); in sb_numaddrspaces()
691 return ((R_SBREG(sii, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT) + 1; in sb_numaddrspaces()
698 si_info_t *sii; in sb_addrspace() local
700 sii = SI_INFO(sih); in sb_addrspace()
702 return (sb_base(R_SBREG(sii, sb_admatch(sii, asidx)))); in sb_addrspace()
709 si_info_t *sii; in sb_addrspacesize() local
711 sii = SI_INFO(sih); in sb_addrspacesize()
713 return (sb_size(R_SBREG(sii, sb_admatch(sii, asidx)))); in sb_addrspacesize()
721 si_info_t *sii; in sb_commit() local
725 sii = SI_INFO(sih); in sb_commit()
727 origidx = sii->curidx; in sb_commit()
730 INTR_OFF(sii, intr_val); in sb_commit()
733 if (sii->pub.ccrev != NOREV) { in sb_commit()
737 W_REG(sii->osh, &ccregs->broadcastaddress, SB_COMMIT); in sb_commit()
738 W_REG(sii->osh, &ccregs->broadcastdata, 0x0); in sb_commit()
744 INTR_RESTORE(sii, intr_val); in sb_commit()
750 si_info_t *sii; in sb_core_disable() local
754 sii = SI_INFO(sih); in sb_core_disable()
756 ASSERT(GOODREGS(sii->curmap)); in sb_core_disable()
757 sb = REGS2SB(sii->curmap); in sb_core_disable()
760 if (R_SBREG(sii, &sb->sbtmstatelow) & SBTML_RESET) in sb_core_disable()
764 if ((R_SBREG(sii, &sb->sbtmstatelow) & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) == 0) in sb_core_disable()
768 OR_SBREG(sii, &sb->sbtmstatelow, SBTML_REJ); in sb_core_disable()
769 dummy = R_SBREG(sii, &sb->sbtmstatelow); in sb_core_disable()
771 SPINWAIT((R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000); in sb_core_disable()
772 if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY) in sb_core_disable()
775 if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) { in sb_core_disable()
776 OR_SBREG(sii, &sb->sbimstate, SBIM_RJ); in sb_core_disable()
777 dummy = R_SBREG(sii, &sb->sbimstate); in sb_core_disable()
779 SPINWAIT((R_SBREG(sii, &sb->sbimstate) & SBIM_BY), 100000); in sb_core_disable()
783 W_SBREG(sii, &sb->sbtmstatelow, in sb_core_disable()
786 dummy = R_SBREG(sii, &sb->sbtmstatelow); in sb_core_disable()
790 if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) in sb_core_disable()
791 AND_SBREG(sii, &sb->sbimstate, ~SBIM_RJ); in sb_core_disable()
795 W_SBREG(sii, &sb->sbtmstatelow, ((bits << SBTML_SICF_SHIFT) | SBTML_REJ | SBTML_RESET)); in sb_core_disable()
807 si_info_t *sii; in sb_core_reset() local
811 sii = SI_INFO(sih); in sb_core_reset()
812 ASSERT(GOODREGS(sii->curmap)); in sb_core_reset()
813 sb = REGS2SB(sii->curmap); in sb_core_reset()
825 W_SBREG(sii, &sb->sbtmstatelow, in sb_core_reset()
828 dummy = R_SBREG(sii, &sb->sbtmstatelow); in sb_core_reset()
831 if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_SERR) { in sb_core_reset()
832 W_SBREG(sii, &sb->sbtmstatehigh, 0); in sb_core_reset()
834 if ((dummy = R_SBREG(sii, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) { in sb_core_reset()
835 AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO)); in sb_core_reset()
839 W_SBREG(sii, &sb->sbtmstatelow, in sb_core_reset()
841 dummy = R_SBREG(sii, &sb->sbtmstatelow); in sb_core_reset()
845 W_SBREG(sii, &sb->sbtmstatelow, ((bits | SICF_CLOCK_EN) << SBTML_SICF_SHIFT)); in sb_core_reset()
846 dummy = R_SBREG(sii, &sb->sbtmstatelow); in sb_core_reset()
853 si_info_t *sii; in sb_core_tofixup() local
856 sii = SI_INFO(sih); in sb_core_tofixup()
858 if ((BUSTYPE(sii->pub.bustype) != PCI_BUS) || PCIE(sii) || in sb_core_tofixup()
859 (PCI(sii) && (sii->pub.buscorerev >= 5))) in sb_core_tofixup()
862 ASSERT(GOODREGS(sii->curmap)); in sb_core_tofixup()
863 sb = REGS2SB(sii->curmap); in sb_core_tofixup()
865 if (BUSTYPE(sii->pub.bustype) == SI_BUS) { in sb_core_tofixup()
866 SET_SBREG(sii, &sb->sbimconfiglow, in sb_core_tofixup()
871 SET_SBREG(sii, &sb->sbimconfiglow, in sb_core_tofixup()
875 SET_SBREG(sii, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0); in sb_core_tofixup()
909 si_info_t *sii; in sb_set_initiator_to() local
915 sii = SI_INFO(sih); in sb_set_initiator_to()
922 switch (BUSTYPE(sii->pub.bustype)) { in sb_set_initiator_to()
924 idx = sii->pub.buscoreidx; in sb_set_initiator_to()
943 INTR_OFF(sii, intr_val); in sb_set_initiator_to()
948 tmp = R_SBREG(sii, &sb->sbimconfiglow); in sb_set_initiator_to()
950 W_SBREG(sii, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to); in sb_set_initiator_to()
954 INTR_RESTORE(sii, intr_val); in sb_set_initiator_to()