1 /****************************************************************************
2 **+-----------------------------------------------------------------------+**
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4 **| Copyright(c) 1998 - 2008 Texas Instruments. All rights reserved. |**
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33 **+-----------------------------------------------------------------------+**
34 ****************************************************************************/
35
36 /****************************************************************************
37 *
38 * MODULE: hwAccess.c
39 * PURPOSE: Support access to the wlan hardware registers and memory
40 *
41 * Direct Slave mode:
42 * -----------------
43 *
44 * 1. 08 bit function
45 * - access 16 bit (WA100 has no access to 8 bits)
46 * - set/get the relevant byte according to the address (odd or even)
47 * + ((char *)&DataShort)[Addr&0x1]
48 * - no endian handle
49 * 2. 16 bit function
50 * - access 16 bit
51 * - short endian handle
52 * 3. 32 bit function
53 * - access 32 bit
54 * - long endian handle
55 * 4. buffers copy to (stream of bytes)
56 * - addresses must be even
57 * - copy buffer as stream of 16 bits (in case of src/dst address ends with 0x2)
58 * - handle case of more bytes to copy
59 * * TempWord = (*shortDest & 0x00ff) | (*shortSrc & 0xff00);
60 * - no endian handle
61 * 5. registers
62 * - access 32 bit
63 * - long endian handle
64 * - no use of wlan hardware capability to swap endian
65 *
66 * Indirect Slave mode:
67 * -------------------
68 *
69 * 1. 08 bit function
70 * - access 16 bit (WA100 has no access to 8 bits)
71 * - set/get the relevant byte according to the address (odd or even)
72 * + ((char *)&DataLong)[Addr&0x3]
73 * - no endian handle
74 * 2. 16 bit function
75 * - access 32 bit (set addr reg , get data reg)
76 * - set/get the relevant short according to the address (00 or 02)
77 * + ((short *)&DataLong)[(Addr>>1)&0x1])
78 * - short endian handle
79 * 3. 32 bit function
80 * - access 32 bit (set addr reg , get data reg)
81 * - long endian handle
82 * 4. buffers copy to (stream of bytes)
83 * - addresses must be even
84 * - handle case of dest(wlan hardware) address ends with 0x2 - read 32 from 0x0, set only high short
85 * - now the dest(wlan hardware) address is long address
86 * - use Auto Increment Mode
87 * - copy buffer as stream of 16 bits (in case of source address ends with 0x2)
88 * - handle case of more bytes to copy
89 * * i=0..Len&3 ==> ((char *)&DataLong)[i] = ((char *)shortSrc)[i]
90 * - no endian handle
91 * 5. buffers copy from (stream of bytes)
92 * - addresses must be even
93 * - handle case of source(wlan hardware) address ends with 0x2 - read 32 from 0x0, set only high short
94 * - now the source(wlan hardware) address is long address
95 * - use Auto Increment Mode
96 * - copy buffer as stream of 16 bits (in case of dest address ends with 0x2)
97 * - handle case of more bytes to copy
98 * * i=0..Len&3 ==> ((char *)shortDest)[i] = ((char *)&DataLong)[i]
99 * - no endian handle
100 * 6. registers
101 * - access 32 bit
102 * - long endian handle
103 * - no use of wlan hardware capability to swap endian
104 *
105 ****************************************************************************/
106 #include "osTIType.h"
107 #include "osApi.h"
108 #include "whalCommon.h"
109 #include "whalHwDefs.h"
110 #ifdef HW_ACCESS_SDIO
111
112 #ifndef _WINDOWS /*Linux, Symbian, RVCT */
113
114 #include "mmc_omap_api.h"
115 #include "mmc_tnetw1150_api.h"
116
117 #else /* ifdef _WINDOWS */
118 #endif /* ifdef _WINDOWS */
119
120 #elif defined(HW_ACCESS_WSPI)
121
122 #include "wspi.h"
123
124 #endif
125 #include "TNETWIF.h"
126 #include "whalHwAccess.h"
127
128 /* #define __HWACCESS_DEBUG__ */
129
130 /*
131 * Define this flag to support SDIO asynchronous mode
132 */
133 #undef HW_ACCESS_SDIO_ASYNC_SUPPORT
134
135
136 /************************************************************************
137 * Types
138 ************************************************************************/
139 typedef struct _HWAccess_CB_T
140 {
141 HwAccess_callback_t CBFunc;
142 void* CBArg;
143 } HWAccess_CB_T;
144
145 typedef void (*HwAccessErrorHandle)(TI_HANDLE theObjectHandle,char* Report , UINT32 strLen);
146
147 typedef struct _partition_t
148 {
149 UINT32 size;
150 UINT32 start;
151 } partition_t;
152
153
154 /* HwAccess context */
155 typedef struct _HwAccess_T_new
156 {
157 void *hProtect;
158
159 TI_HANDLE hOs;
160 TI_HANDLE hReport;
161
162 #if (defined(HW_ACCESS_SDIO)|defined(HW_ACCESS_WSPI))
163 TI_HANDLE hDriver;
164 UINT32 MemRegionAddr;
165 UINT32 RegisterRegionAddr;
166 UINT32 workingPartUpperLimit;
167 UINT32 registerPartUpperLimit;
168 #else /* HW_ACCESS_CARDBUS */
169 UINT32 RegBaseAddr;
170 UINT32 MemBaseAddr;
171 #endif
172
173 HWAccess_CB_T CB;
174
175 UINT8 AsyncMode;
176
177 UINT32 uBusError;
178 HwAccessErrorHandle hwAccesserror_Cb;
179 TI_HANDLE hBackReference;
180
181 PADDING (partition_t partition [2])
182
183 } HwAccess_T_new;
184
185
186 /************************************************************************
187 * Defines
188 ************************************************************************/
189
190 #ifdef HW_ACCESS_WSPI
191
192 /*
193 * Converts status from WSPI into TI_STATUS
194 */
195 #define WSPI2TNETWIF(pHwAccess,status,addr) \
196 switch(status) { \
197 case WSPI_TXN_PENDING: status = TNETWIF_PENDING; break; \
198 case WSPI_TXN_COMPLETE: status = TNETWIF_COMPLETE; break; \
199 default: \
200 WLAN_REPORT_ERROR (pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG, \
201 ("whal_hwAccess: Error in read/write async, addr=0x%08x status=%d\n", \
202 addr, status)); \
203 status = TNETWIF_ERROR; break; \
204 }
205
206 /*
207 * Indicate the index position at which we should check if the HW is up -
208 * i.e. (buf[HW_ACCESS_WSPI_FIXED_BUSY_LEN] & 0x1 == TRUE)
209 */
210 #ifdef TNETW1251
211 #define HW_ACCESS_WSPI_FIXED_BUSY_LEN ((TNETWIF_READ_OFFSET_BYTES - 4 ) / sizeof(UINT32))
212 #else
213 #define HW_ACCESS_WSPI_FIXED_BUSY_LEN 0
214 #endif
215
216 #endif /* HW_ACCESS_WSPI */
217
218 #define HW_ACCESS_WSPI_INIT_CMD_MASK 0
219
220 #define HW_ACCESS_WSPI_ALIGNED_SIZE 4
221 #define HW_ACCESS_NUM_OF_BIT_IN_BYTE 8
222
223 #define HW_ACCESS_REGISTER_SIZE 4
224
225
226 /* ELP CTRL register */
227 #define HW_ACCESS_ELP_CTRL_REG_ADDR 0x1FFFC
228
229
230 #define HW_ACCESS_1_BYTE_REMINDE_MASK 0x000000FF
231 #define HW_ACCESS_2_BYTE_REMINDE_MASK 0x0000FFFF
232 #define HW_ACCESS_3_BYTE_REMINDE_MASK 0x00FFFFFF
233
234 /* translation registers */
235 #define HW_ACCESS_PART0_SIZE_ADDR 0x1FFC0
236 #define HW_ACCESS_PART0_START_ADDR 0x1FFC4
237 #define HW_ACCESS_PART1_SIZE_ADDR 0x1FFC8
238 #define HW_ACCESS_PART1_START_ADDR 0x1FFCC
239
240
241 /************************************************************************
242 * Macros
243 ************************************************************************/
244 #define EXTRACT_BYTE_FROM_WORD(DataShort, Addr) (((char *)&DataShort)[((int)Addr)&0x1])
245 #define EXTRACT_BYTE_FROM_LONG(DataLong, Addr) (((char *)&DataLong )[((int)Addr)&0x3])
246 #define EXTRACT_WORD_FROM_LONG(DataLong, Addr) (((short *)&DataLong)[(((int)Addr>>1))&0x1])
247 #define EXTRACT_BYTE_LONG(DataLong, i) (((char *)&DataLong)[i])
248
249 #define HW_MEM_SHORT(pHwAccess, Addr) (*(volatile UINT16 *)(pHwAccess->MemBaseAddr + (UINT32)(Addr)))
250 #define HW_MEM_LONG(pHwAccess, Addr) (*(volatile UINT32 *)(pHwAccess->MemBaseAddr + (UINT32)(Addr)))
251
252 #define TRANSLATE_ADDRESS_MEM(addr) ((addr) - pHwAccess->MemRegionAddr)
253 #define TRANSLATE_ADDRESS_REG(addr) ((addr) + pHwAccess->RegisterRegionAddr)
254
255 #if 1 /* 0 */
256 #if (defined(HW_ACCESS_SDIO)|defined(HW_ACCESS_WSPI)) /* 1 */
257 void HW_REG_LONG_WRITE(HwAccess_T_new *pHwAccess, UINT32 RegAddr, UINT32 BitVal);
258 void HW_REG_LONG_READ(HwAccess_T_new *pHwAccess, UINT32 RegAddr, UINT32 *Val);
259 #else /* 1 */
260 #define HW_REG_SHORT_WRITE(pHwAccess, Addr, Data) ((*(volatile UINT16 *)(pHwAccess->RegBaseAddr + (UINT32)(Addr))) = (UINT16)(Data))
261 #define HW_REG_SHORT_READ(pHwAccess, Addr, Data) ((*(Data)) = (*(volatile UINT16 *)(pHwAccess->RegBaseAddr + (UINT32)(Addr))) )
262 #ifdef NOT_SUPPORT_32_BIT_ACCESS_COMMAND /* for example: iPAQ model 38xx */ /* 2 */
263 #define HW_REG_LONG_WRITE(pHwAccess, Addr, Data) HW_REG_SHORT_WRITE(pHwAccess, Addr, Data); HW_REG_SHORT_WRITE(pHwAccess, Addr+2, ((UINT16)(Data>>16)))
264 #define HW_REG_LONG_READ(pHwAccess, Addr, pData) HW_REG_SHORT_READ(pHwAccess, Addr, pData); HW_REG_SHORT_READ(pHwAccess, Addr+2, ((UINT16 *)pData+1))
265 #else /* 2 */
266 #define HW_REG_LONG_WRITE(pHwAccess, Addr, Data) ((*(volatile UINT32 *)(pHwAccess->RegBaseAddr + (UINT32)(Addr))) = (UINT32)(Data))
267 #define HW_REG_LONG_READ(pHwAccess, Addr, Data) ((*(Data)) = (*(volatile UINT32 *)(pHwAccess->RegBaseAddr + (UINT32)(Addr))) )
268 #endif /* 2 */
269 #endif /* 1 */
270 #else /* 0 */
271 #endif /* 0 */
272
273
274
275 /************************************************************************
276 * Functions
277 ************************************************************************/
278
279 #if !defined(HW_ACCESS_SDIO) && !defined(HW_ACCESS_WSPI)
280 static void whal_hwAccess_DirectCopy_new(HwAccess_T_new *pHwAccess, UINT8* Dest, UINT8* Src, UINT32 Len);
281 #endif
282 #ifdef HW_ACCESS_SDIO
283 static void sdio_transaction_notify_read(struct SDIO_Request *req, int status);
284 static void sdio_transaction_notify_write(struct SDIO_Request *req, int status);
285 static void sdio_transaction_error(struct SDIO_Request *req, int stat);
286 #ifdef CONFIG_ASYNC_API
287 static void sdio_async_transaction_notify(struct SDIO_Request *req, int status);
288 static void sdio_async_transaction_error(struct SDIO_Request *req, int status);
289 #endif
290 #endif
291
292 /*
293 ** Read/Write interface
294 **----------------------------
295 **
296 ** the memory space shell be divided to 2 Partions: Memory, and Registers.
297 ** 1. The memory Region will be set at init to point to the FW Ram,
298 ** and after FW init complete, the Memory Region will be set to point the Packet Ram.
299 ** 2. Registry Region.
300 **
301 **
302 */
303
304
305
306 /************************************************************************
307 * new API
308 ************************************************************************/
309
310
311
312 /****************************************************************************
313 * whal_hwAccess_Create
314 ****************************************************************************
315 * DESCRIPTION: create the HwAccess module. allocate the module context and create the sublayers
316 *
317 * INPUTS: hOs - handle to the OS module
318 *
319 * OUTPUT: TI_HANDLE - the handle to the context that was created
320 *
321 * RETURNS: NULL = failure.
322 * otherwise = success
323 ****************************************************************************/
whal_hwAccess_Create(TI_HANDLE hOs)324 TI_HANDLE whal_hwAccess_Create(TI_HANDLE hOs)
325 {
326 HwAccess_T_new *pHwAccess;
327 int status = OK;
328 #ifdef HW_ACCESS_SDIO
329 SDIO_ConfigParams configParams;
330 #endif
331 pHwAccess = os_memoryAlloc(hOs, sizeof(HwAccess_T_new));
332 if (pHwAccess == NULL)
333 return NULL;
334
335 os_memoryZero(hOs, pHwAccess, sizeof(HwAccess_T_new));
336
337 pHwAccess->hOs = hOs;
338
339 pHwAccess->hProtect = os_protectCreate(pHwAccess->hOs);
340 if (pHwAccess->hProtect == NULL)
341 {
342 whal_hwAccess_Destroy(pHwAccess);
343 return NULL;
344 }
345
346 #ifdef HW_ACCESS_SDIO
347
348 pHwAccess->AsyncMode = FALSE;
349
350 os_memoryZero(hOs, &configParams, sizeof(SDIO_ConfigParams));
351 configParams.fnotify_read = sdio_transaction_notify_read;
352 configParams.fnotify_write = sdio_transaction_notify_write;
353 configParams.ferror = sdio_transaction_error;
354 configParams.fconfig_peripheral = SDIO_TNETWConfig;
355 configParams.fconvert = NULL;
356 configParams.owner = pHwAccess;
357
358 status = SDIO_Init(&configParams, &pHwAccess->hDriver);
359
360 #elif defined(HW_ACCESS_WSPI)
361
362 pHwAccess->AsyncMode = TRUE;
363
364 pHwAccess->hDriver = WSPI_Open (pHwAccess->hOs);
365 status = pHwAccess->hDriver == NULL;
366
367 #else
368
369 pHwAccess->AsyncMode = FALSE;
370
371 #endif
372
373 if (status != 0)
374 {
375 if (pHwAccess->hProtect)
376 os_protectDestroy(pHwAccess->hOs, pHwAccess->hProtect);
377 os_memoryFree(pHwAccess->hOs, pHwAccess, sizeof(HwAccess_T_new));
378 return NULL;
379 }
380
381 return pHwAccess;
382 }
383
384 /****************************************************************************
385 * whal_hwAccess_Destroy
386 ****************************************************************************
387 * DESCRIPTION: destroy the module. deallocate the cmodule context.
388 *
389 * INPUTS: hHwAccess - handle to the module context
390 *
391 * OUTPUT: none.
392 *
393 * RETURNS: one of the error codes (0 => OK)
394 ****************************************************************************/
whal_hwAccess_Destroy(TI_HANDLE hHwAccess)395 int whal_hwAccess_Destroy(TI_HANDLE hHwAccess)
396 {
397 HwAccess_T_new *pHwAccess = (HwAccess_T_new*)hHwAccess;
398
399 if (pHwAccess)
400 {
401 #ifdef HW_ACCESS_SDIO
402
403 SDIO_Stop(pHwAccess->hDriver, 0);
404 SDIO_Shutdown(pHwAccess->hDriver);
405
406 #elif defined(HW_ACCESS_WSPI)
407
408 WSPI_Close(pHwAccess->hDriver);
409
410 #endif
411
412
413 if (pHwAccess->hProtect)
414 os_protectDestroy(pHwAccess->hOs, pHwAccess->hProtect);
415 os_memoryFree(pHwAccess->hOs, pHwAccess, sizeof(HwAccess_T_new));
416 }
417 return OK;
418 }
419
420
421 /****************************************************************************
422 * whal_hwAccess_Config
423 ****************************************************************************
424 * DESCRIPTION: config the module.
425 *
426 * INPUTS: hHwAccess - handle to the module context
427 * hReport - handle to report module context that is used when we output debug messages
428 *
429 * OUTPUT: none.
430 *
431 * RETURNS: one of the error codes (0 => OK)
432 ****************************************************************************/
whal_hwAccess_Config(TI_HANDLE hHwAccess,TI_HANDLE hReport,UINT32 RegBaseAddr,UINT32 MemBaseAddr,HwAccess_callback_t CBFunc,void * CBArg)433 int whal_hwAccess_Config(TI_HANDLE hHwAccess, TI_HANDLE hReport,UINT32 RegBaseAddr, UINT32 MemBaseAddr, HwAccess_callback_t CBFunc,void* CBArg)
434 {
435 HwAccess_T_new *pHwAccess = (HwAccess_T_new*) hHwAccess;
436 int status = OK;
437
438 #ifdef HW_ACCESS_WSPI
439 WSPIConfig_t wspi_config;
440 #endif
441
442 pHwAccess->hReport = hReport;
443
444 #ifdef GWSI_SPI_TEST
445 /* For GWSI_API_TEST this parameter should be maximum allowed because we don't use setPartition */
446 pHwAccess->workingPartUpperLimit = 0xFFFFFFFF;
447 #endif /* GWSI_API_TEST */
448 /*
449 Wait 200 usec for memory repair process to finish and device is ready.
450 */
451 os_StalluSec(pHwAccess->hOs, 200);
452
453 pHwAccess->CB.CBFunc = CBFunc;
454 pHwAccess->CB.CBArg = CBArg;
455
456 #ifdef HW_ACCESS_SDIO
457
458 pHwAccess->RegisterRegionAddr = HW_ACCESS_DOWN_PART0_SIZE;
459 pHwAccess->MemRegionAddr = HW_ACCESS_DOWN_PART0_ADDR;
460 pHwAccess->uBusError = 0;
461
462 status = SDIO_Start (pHwAccess->hDriver);
463
464 status = (status == SDIO_SUCCESS) ? TNETWIF_COMPLETE : TNETWIF_ERROR;
465
466 #elif defined(HW_ACCESS_WSPI)
467
468 wspi_config.isFixedAddress = FALSE;
469 wspi_config.fixedBusyLength = HW_ACCESS_WSPI_FIXED_BUSY_LEN;
470 wspi_config.mask = HW_ACCESS_WSPI_INIT_CMD_MASK;
471
472 status = WSPI_Configure (pHwAccess->hDriver,
473 pHwAccess->hReport,
474 &wspi_config,
475 (WSPI_CB_T*)&pHwAccess->CB);
476
477 WSPI_SetErrLog(pHwAccess->hDriver, TNETWIF_printErrorLog);
478
479 WSPI2TNETWIF (pHwAccess, status, 0x0);
480
481 #else /* HW_ACCESS_CARDBUS */
482 pHwAccess->RegBaseAddr = RegBaseAddr;
483 pHwAccess->MemBaseAddr = MemBaseAddr;
484 #endif
485
486 return status;
487 }
488
489 /****************************************************************************
490 * whal_hwAccess_ReConfig()
491 ****************************************************************************
492 * DESCRIPTION:
493 *
494 * INPUTS: None
495 *
496 * OUTPUT: None
497 *
498 * RETURNS:
499 ****************************************************************************/
whal_hwAccess_ReConfig(TI_HANDLE hHwAccess)500 int whal_hwAccess_ReConfig(TI_HANDLE hHwAccess)
501 {
502 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
503
504 #ifdef _WINDOWS
505 #else /* _WINDOWS */
506 /* unbclock the access to the bus */
507 pHwAccess->uBusError = 0;
508
509 #ifdef HW_ACCESS_SDIO
510 SDIO_Stop (pHwAccess->hDriver, 0);
511 SDIO_Start (pHwAccess->hDriver);
512 #elif defined(HW_ACCESS_WSPI)
513 /* TODO*/
514 #endif
515 #endif /* _WINDOWS */
516 return OK;
517 }
518
519
520 #ifdef USE_SYNC_API
521 /****************************************************************************
522 * whal_hwAccess_WriteELP
523 ****************************************************************************
524 * DESCRIPTION: write data synchronously to the TNET ELP register (1byte)
525 *
526 * INPUTS: pHwAccess - TI_HANDLE * - the HwAccess context
527 * data - UINT8 - the data to write
528 *
529 * OUTPUT: none
530 *
531 * RETURNS: one of the error codes (0 => OK)
532 ****************************************************************************/
whal_hwAccess_WriteELP(TI_HANDLE hHwAccess,UINT32 data)533 int whal_hwAccess_WriteELP (TI_HANDLE hHwAccess, UINT32 data)
534 {
535 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
536 int status = OK;
537
538 os_profile (pHwAccess->hOs, 2, 0);
539
540 #ifdef HW_ACCESS_SDIO
541 status = SDIO_TNETW_Set_ELP_Reg(pHwAccess->hDriver, HW_ACCESS_ELP_CTRL_REG_ADDR, data);
542 #elif defined(HW_ACCESS_WSPI)
543 status = WSPI_WriteSync (pHwAccess->hDriver, HW_ACCESS_ELP_CTRL_REG_ADDR, (UINT8*)&data, HW_ACCESS_REGISTER_SIZE);
544 #endif
545
546 os_profile (pHwAccess->hOs, 3, 0);
547
548 if (status != OK)
549 {
550 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
551 ("whal_hwAccess_WriteReg_ELP: Error in ELP reg write status=%d\n",
552 status));
553 return NOK;
554 }
555
556 return OK;
557 }
558 #endif /* USE_SYNC_API */
559
560 /****************************************************************************
561 * whal_hwAccess_WriteELPAsync
562 ****************************************************************************
563 * DESCRIPTION: write data synchronously from the TNET using the defined access (WSPI/SDIO).
564 * the length of data is always 4bytes cause this is the size of the TNET registers
565 * the function is passed a call-back function that will be called after the read request ends.
566 *
567 * INPUTS: pHwAccess - TI_HANDLE * - the HwAccess context
568 * addr - UINT32 - the address offset inside the TNET
569 * data - UINT8* - a pointer to the buffer that holds the data to write
570 * bMore - indicate whether more txn on the bus are about to happen (FALSE only when setting
571 * the HW to sleep).
572 *
573 * OUTPUT: none
574 *
575 * RETURNS: one of the error codes (0 => OK)
576 ****************************************************************************/
whal_hwAccess_WriteELPAsync(TI_HANDLE hHwAccess,UINT32 data,BOOL bCb,BOOL bMore)577 int whal_hwAccess_WriteELPAsync (TI_HANDLE hHwAccess, UINT32 data, BOOL bCb, BOOL bMore)
578 {
579 #if defined(HW_ACCESS_SDIO)
580
581 #if defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
582
583 #error "SDIO asynchronous mode is not supported"
584
585 /* Not implemented yet */
586 return OK;
587
588 #else
589
590 /* Just call to synchronous API */
591 return (whal_hwAccess_WriteELP (hHwAccess, data) == OK) ?
592 TNETWIF_COMPLETE :
593 TNETWIF_ERROR;
594
595
596 #endif
597
598 #else /* HW_ACCESS_WSPI */
599
600 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
601 WSPI_CB_T Cb = { NULL, NULL }, *pCb;
602 int status;
603
604 pCb = (bCb) ? ((WSPI_CB_T*)&pHwAccess->CB) : &Cb;
605
606 os_profile (pHwAccess->hOs, 2, 0);
607
608 /* since we are writing a register - no extra space is needed */
609 status = WSPI_WriteAsync (pHwAccess->hDriver,
610 HW_ACCESS_ELP_CTRL_REG_ADDR,
611 (UINT8*)&data,
612 HW_ACCESS_REGISTER_SIZE,
613 pCb,
614 bMore,
615 FALSE);
616
617 os_profile (pHwAccess->hOs, 3, 0);
618
619 WSPI2TNETWIF (pHwAccess, status, HW_ACCESS_ELP_CTRL_REG_ADDR);
620
621 return status;
622
623 #endif
624 }
625
626 /****************************************************************************
627 * whal_hwAccess_ReadELPAsync
628 ****************************************************************************
629 * DESCRIPTION: Read the ELP register
630 *
631 * INPUTS: pHwAccess - TI_HANDLE * - the HwAccess context
632 * addr - UINT32 - the address offset inside the TNET
633 * data - UINT8* - a pointer to the buffer to read data into
634 * bMore - indicate whether more txn on the bus are about to happen (FALSE only when setting
635 * the HW to sleep).
636 *
637 * OUTPUT: none
638 *
639 * RETURNS: one of the error codes (0 => OK)
640 ****************************************************************************/
whal_hwAccess_ReadELPAsync(TI_HANDLE hHwAccess,UINT8 * data,BOOL bCb,BOOL bMore)641 int whal_hwAccess_ReadELPAsync (TI_HANDLE hHwAccess, UINT8 *data, BOOL bCb, BOOL bMore)
642 {
643 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
644 int status;
645
646 #ifdef HW_ACCESS_SDIO
647
648 #ifndef _WINDOWS
649 status = SDIO_TNETW_Get_ELP_Reg(pHwAccess->hDriver, HW_ACCESS_ELP_CTRL_REG_ADDR, (UINT32*)data);
650 #else
651 #endif
652
653 if (status != OK)
654 {
655 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
656 ("whal_hwAccess_ReadELPAsync: Error in ELP reg raed status=%d\n",
657 status));
658 return TNETWIF_ERROR;
659 }
660 return TNETWIF_COMPLETE;
661
662 #else /* HW_ACCESS_WSPI */
663
664 os_profile (pHwAccess->hOs, 2, 0);
665
666 /* In registers we don't save place */
667 status = WSPI_ReadAsync (pHwAccess->hDriver,
668 HW_ACCESS_ELP_CTRL_REG_ADDR,
669 (UINT8*)data,
670 HW_ACCESS_REGISTER_SIZE,
671 (WSPI_CB_T*)&pHwAccess->CB,
672 TRUE,
673 FALSE);
674
675 os_profile (pHwAccess->hOs, 3, 0);
676
677 WSPI2TNETWIF (pHwAccess, status, HW_ACCESS_ELP_CTRL_REG_ADDR);
678
679 return status;
680
681 #endif
682 }
683
684
685 #ifdef USE_SYNC_API
686 /****************************************************************************
687 * whal_hwAccess_ReadMem_Align
688 ****************************************************************************
689 * DESCRIPTION: read data synchronously from the TNET using the defined access (WSPI/SDIO).
690 * the length of data specified is rounded up so the length will be multiple of 4 (bytes)
691 *
692 * INPUTS: hHwAccess - the handle of HwAccess module
693 * addr - UINT32 - the address offset inside the TNET
694 * len - int - the length of the data to read
695 *
696 * OUTPUT: data - UINT8* - a pointer to the buffer to fill with the read data
697 *
698 * RETURNS: one of the error codes (0 => OK)
699 ****************************************************************************/
whal_hwAccess_ReadMem_Align(TI_HANDLE hHwAccess,UINT32 addr,UINT8 * data,UINT16 len)700 int whal_hwAccess_ReadMem_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
701 {
702 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
703 int status = OK;
704 #ifdef HW_ACCESS_SDIO
705 struct SDIO_Request request;
706 #endif
707
708 /* round up the length so it will be multiple of 4bytes */
709 if(len&0x3)
710 len = (len&0xFFFFFFFC)+4;
711
712 #ifdef HW_ACCESS_SDIO
713
714 /* check address */
715 if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
716 {
717 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
718 ("whal_hwAccess_ReadMem_Align: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
719 addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
720 return ERROR_HW_ACCEESS_ADDR;
721 }
722
723 request.buffer = data; /* Pointer to the data buffer aligned address. */
724 request.buffer_len = len; /* Data buffer length in bytes */
725 request.status = SDIO_Request_None;
726 request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
727 request.acquire_window = 0; /*Time out value is not set*/
728 request.block_len = 0; /*Block length. Assigned by driver*/
729 request.physical_buffer = 0; /*Physical address of data buffer is not set*/
730 request.owner = (SDIO_Owner) pHwAccess;
731 request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
732 request.access_flag = 1;
733
734 os_profile (pHwAccess->hOs, 2, 0);
735
736 status = SDIO_SyncRead(pHwAccess->hDriver, &request);
737
738 os_profile (pHwAccess->hOs, 3, 0);
739
740
741 #elif defined(HW_ACCESS_WSPI)
742
743 /* check address */
744 if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
745 {
746 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
747 ("whal_hwAccess_ReadMem_Align: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
748 addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
749 return ERROR_HW_ACCEESS_ADDR;
750 }
751
752 os_profile (pHwAccess->hOs, 2, 0);
753
754 status = WSPI_ReadSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr),data,len);
755
756 os_profile (pHwAccess->hOs, 3, 0);
757
758 #else
759 whal_hwAccess_DirectCopy_new(pHwAccess, data, (UINT8*)addr, len);
760 #endif
761
762 if (status != OK)
763 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
764 ("whal_hwAccess_ReadMem_Align: Error in read, addr=0x%08x status=%d\n",
765 addr, status));
766
767 #ifdef HW_ACCESS_SDIO
768 if (pHwAccess->uBusError)
769 {
770 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
771 ("whal_hwAccess_ReadMem_Align: SDIO Error status=%d\n",
772 request.status));
773 if (pHwAccess->hwAccesserror_Cb)
774 {
775 UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
776 pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,(char*)&failure_reason,2);
777 }
778 else
779 pHwAccess->uBusError = 0;
780 }
781 #endif
782
783 return status;
784 }
785
786 /****************************************************************************
787 * whal_hwAccess_WriteMem_Align
788 ****************************************************************************
789 * DESCRIPTION: write data synchronously to the TNET using the defined access (WSPI/SDIO).
790 * the length of data specified is rounded up so the length will be multiple of 4 (bytes)
791 *
792 * INPUTS: hHwAccess - the handle of HwAccess module
793 * addr - UINT32 - the address offset inside the TNET
794 * data - UINT8* - a pointer to the buffer that holds the data to write
795 * len - int - the length of the data to read
796 *
797 * OUTPUT: none
798 *
799 * RETURNS: one of the error codes (0 => OK)
800 ****************************************************************************/
whal_hwAccess_WriteMem_Align(TI_HANDLE hHwAccess,UINT32 addr,UINT8 * data,UINT16 len)801 int whal_hwAccess_WriteMem_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
802 {
803 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
804 int status = OK;
805 #ifdef HW_ACCESS_SDIO
806 struct SDIO_Request request;
807 #endif
808
809 /* round the length so it will be multiple of 4bytes */
810 if(len&0x3)
811 len = (len&0xFFFFFFFC)+4;
812
813 #ifdef HW_ACCESS_SDIO
814
815 /* check address */
816 if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
817 {
818 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
819 ("whal_hwAccess_WriteMem_Align: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
820 addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
821 return ERROR_HW_ACCEESS_ADDR;
822 }
823
824 request.buffer = data; /* Pointer to the data buffer aligned address. */
825 request.buffer_len = len; /* Data buffer length in bytes */
826 request.status = SDIO_Request_None;
827 request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
828 request.acquire_window = 0; /*Time out value is not set*/
829 request.block_len = 0; /*Block length. Assigned by driver*/
830 request.physical_buffer = 0; /*Physical address of data buffer is not set*/
831 request.owner = (SDIO_Owner) pHwAccess;
832 request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
833 request.access_flag = 0;
834
835 os_profile (pHwAccess->hOs, 2, 0);
836
837 status = SDIO_SyncWrite(pHwAccess->hDriver, &request);
838
839 os_profile (pHwAccess->hOs, 3, 0);
840
841
842 #elif defined(HW_ACCESS_WSPI)
843
844 /* check address */
845 if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
846 {
847 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
848 ("whal_hwAccess_WriteMem_Align: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
849 addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
850 return ERROR_HW_ACCEESS_ADDR;
851 }
852
853 os_profile (pHwAccess->hOs, 2, 0);
854
855 status = WSPI_WriteSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr),data,len);
856
857 os_profile (pHwAccess->hOs, 3, 0);
858
859 #else
860 whal_hwAccess_DirectCopy_new(pHwAccess, (UINT8*)addr, data, len);
861 #endif
862
863 if (status != OK)
864 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
865 ("whal_hwAccess_WriteMem_Align: Error in write, addr=0x%08x status=%d\n",
866 addr, status));
867
868 #ifdef HW_ACCESS_SDIO
869 if (pHwAccess->uBusError)
870 {
871 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
872 ("whal_hwAccess_WriteMem_Align: SDIO Error in write status=%d\n",
873 request.status));
874 if (pHwAccess->hwAccesserror_Cb)
875 {
876 UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
877 pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,(char*)&failure_reason,2);
878 }
879 else
880 pHwAccess->uBusError = 0;
881 }
882 #endif
883
884 return status;
885 }
886 #endif /* USE_SYNC_API */
887
888 /****************************************************************************
889 * whal_hwAccess_ReadMemAsync_Align
890 ****************************************************************************
891 * DESCRIPTION: read data asynchronously from the TNET using the defined access (WSPI/SDIO).
892 * the length of data specified is rounded up so the length will be multiple of 4 (bytes)
893 * the function is passed a call-back function that will be called after the read request ends.
894 *
895 * INPUTS: hHwAccess - the handle of HwAccess module
896 * addr - UINT32 - the address offset inside the TNET
897 * len - int - the length of the data to read
898 * CB - HWAccess_CB_T* - a pointer to a structure that holds the CB function and the passed arg.
899 *
900 * OUTPUT: data - UINT8* - a pointer to the buffer to fill with the read data
901 *
902 * RETURNS: one of the error codes (0 => OK)
903 ****************************************************************************/
whal_hwAccess_ReadMemAsync_Align(TI_HANDLE hHwAccess,UINT32 addr,UINT8 * data,UINT16 len)904 int whal_hwAccess_ReadMemAsync_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
905 {
906 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
907
908 /* Round the length so it will be multiple of 4bytes */
909 if ((len & 0x3) != 0)
910 len = (len & ~3) + 4;
911
912 /* Check address */
913 if (addr + len > pHwAccess->workingPartUpperLimit || addr < pHwAccess->MemRegionAddr)
914 {
915 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
916 ("whal_hwAccess_ReadMemAsync_Align: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
917 addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
918 return ERROR_HW_ACCEESS_ADDR;
919 }
920
921 #if defined(HW_ACCESS_SDIO)
922
923 #if defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
924 {
925 struct SDIO_Request request;
926 int status = OK;
927
928 request.buffer = data; /* Pointer to the data buffer aligned address. */
929 request.buffer_len = len; /* Data buffer length in bytes */
930 request.status = SDIO_Request_None;
931 request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
932 request.acquire_window = 0; /*Time out value is not set*/
933 request.block_len = 0; /*Block length. Assigned by driver*/
934 request.physical_buffer = 0; /*Physical address of data buffer is not set*/
935 request.owner = (SDIO_Owner) pHwAccess;
936 request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
937 request.access_flag = 1;
938 request.fnotify = sdio_async_transaction_notify; /* completion notification */
939 request.ferror = sdio_async_transaction_error; /* error notification */
940
941 os_profile (pHwAccess->hOs, 2, 0);
942
943 status = SDIO_AsyncRead (pHwAccess->hDriver, &request);
944
945 os_profile (pHwAccess->hOs, 3, 0);
946
947 if (status != OK)
948 {
949 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
950 ("whal_hwAccess_ReadMemAsync_Align: Error in read async, addr=0x%08x status=%d\n",
951 addr, status));
952 return TNETWIF_ERROR;
953 }
954
955 if (pHwAccess->uBusError)
956 {
957 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
958 ("whal_hwAccess_ReadMemAsync_Align: SDIO Error status=%d\n",
959 request.status));
960 if (pHwAccess->hwAccesserror_Cb)
961 {
962 UINT16 failure_reason = HEALTH_REPORT_BUS_ERROR;
963 pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,&failure_reason,2);
964 }
965 else
966 pHwAccess->uBusError = 0;
967 }
968
969 return TNETWIF_COMPLETE;
970 }
971
972 #else
973
974 return TNETWIF_COMPLETE;
975
976 #endif
977
978 #else /*HW_ACCESS_WSPI*/
979 {
980 int status;
981
982 os_profile (pHwAccess->hOs, 2, 0);
983
984 status = WSPI_ReadAsync (pHwAccess->hDriver,
985 TRANSLATE_ADDRESS_MEM(addr),
986 data,
987 len,
988 (WSPI_CB_T*)&pHwAccess->CB,
989 TRUE,
990 0);
991
992 os_profile (pHwAccess->hOs, 3, 0);
993
994 WSPI2TNETWIF (pHwAccess, status, addr);
995
996 return status;
997 }
998
999 #endif
1000 }
1001
1002 /****************************************************************************
1003 * whal_hwAccess_WriteAsync_Align
1004 ****************************************************************************
1005 * DESCRIPTION: write data synchronously from the TNET using the defined access (WSPI/SDIO).
1006 * the length of data specified is rounded up so the length will be multiple of 4 (bytes)
1007 * the function is passed a call-back function that will be called after the read request ends.
1008 *
1009 * INPUTS: pHwAccess - HwAccess_T* - the HwAccess context
1010 * addr - UINT32 - the address offset inside the TNET
1011 * data - UINT8* - a pointer to the buffer that holds the data to write
1012 * Len - int - the length of the data to read
1013 * CB - HWAccess_CB_T* - a pointer to a structure that holds the CB function and the passed arg.
1014 *
1015 * OUTPUT: none
1016 *
1017 * RETURNS: one of the error codes (0 => OK)
1018 ****************************************************************************/
whal_hwAccess_WriteMemAsync_Align(TI_HANDLE hHwAccess,UINT32 addr,UINT8 * data,UINT16 len)1019 int whal_hwAccess_WriteMemAsync_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
1020 {
1021 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
1022
1023 /* Round the length so it will be multiple of 4bytes */
1024 if ((len & 0x3) != 0)
1025 len = (len & ~3) + 4;
1026
1027 /* Check address */
1028 if (addr + len > pHwAccess->workingPartUpperLimit || addr < pHwAccess->MemRegionAddr)
1029 {
1030 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1031 ("whal_hwAccess_WriteMemAsync_Align: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
1032 addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
1033 return ERROR_HW_ACCEESS_ADDR;
1034 }
1035
1036 #if defined(HW_ACCESS_SDIO)
1037
1038 #if defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
1039 {
1040 struct SDIO_Request request;
1041 int status = OK;
1042
1043 request.buffer = data; /*Pointer to the data buffer aligned address*/
1044 request.buffer_len = len; /*Data buffer length in bytes*/
1045 request.status = SDIO_Request_None;
1046 request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
1047 request.acquire_window = 0; /* Time out value is not set */
1048 request.block_len = 0; /* Block length. Assigned by driver */
1049 request.physical_buffer = 0; /* Physical address of data buffer is not set */
1050 request.owner = (SDIO_Owner) pHwAccess;
1051 request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
1052 request.access_flag = 0;
1053 request.fnotify = sdio_async_transaction_notify; /* completion notification */
1054 request.ferror = sdio_async_transaction_error; /* error notification */
1055
1056 os_profile (pHwAccess->hOs, 2, 0);
1057
1058 status = SDIO_AsyncWrite (pHwAccess->hDriver, &request);
1059
1060 os_profile (pHwAccess->hOs, 3, 0);
1061
1062 if (status != OK)
1063 {
1064 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1065 ("whal_hwAccess_WriteMemAsync_Align: Error in write async, addr=0x%08x status=%d\n",
1066 addr, status));
1067
1068 return TNETWIF_ERROR;
1069 }
1070
1071 return TNETWIF_COMPLETE;
1072 }
1073
1074 #else
1075
1076 return TNETWIF_COMPLETE;
1077
1078 #endif
1079
1080 #else /*HW_ACCESS_WSPI*/
1081 {
1082 int status;
1083
1084 os_profile (pHwAccess->hOs, 2, 0);
1085
1086 status = WSPI_WriteAsync (pHwAccess->hDriver,
1087 TRANSLATE_ADDRESS_MEM(addr),
1088 data,
1089 len,
1090 (WSPI_CB_T*)&pHwAccess->CB,
1091 TRUE,
1092 FALSE);
1093
1094 os_profile (pHwAccess->hOs, 3, 0);
1095
1096 WSPI2TNETWIF (pHwAccess, status, addr);
1097
1098 return status;
1099 }
1100 #endif
1101 }
1102
1103
1104 #ifdef USE_SYNC_API
1105 /****************************************************************************
1106 * whal_hwAccess_ReadMem
1107 ****************************************************************************
1108 * DESCRIPTION: read data synchronously from the TNET using the defined access (WSPI/SDIO).
1109 * the length of data is checked and the remnant (length%4) is completed with read-modify
1110 *
1111 * INPUTS: pHwAccess - HwAccess_T* - the HwAccess context
1112 * AddrOffset - UINT32 - the address offset inside the TNET
1113 * Len - int - the length of the data to read
1114 *
1115 * OUTPUT: data - UINT8* - a pointer to the buffer to fill with the read data
1116 *
1117 * RETURNS: one of the error codes (0 => OK)
1118 ****************************************************************************/
whal_hwAccess_ReadMem(TI_HANDLE hHwAccess,UINT32 addr,UINT8 * data,UINT16 len)1119 int whal_hwAccess_ReadMem(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
1120 {
1121 int status = OK;
1122 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
1123
1124 #ifdef HW_ACCESS_SDIO
1125 struct SDIO_Request request;
1126 #elif defined(HW_ACCESS_WSPI)
1127 int reminder = len%HW_ACCESS_WSPI_ALIGNED_SIZE;
1128 int tempLen = len - reminder;
1129 UINT32 mask = 0;
1130 status = whal_hwAccess_ReadMemAsync(hHwAccess, addr, data, len);
1131 if (status == TNETWIF_COMPLETE)
1132 {
1133 status = OK;
1134 }
1135 return status;
1136 #endif
1137
1138 /* access is blocked */
1139 if (pHwAccess->uBusError)
1140 {
1141 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_CTRL_MODULE_LOG,
1142 ("Bus is blocked \n"));
1143 return ERROR_HW_ACCEESS_ADDR;
1144 }
1145
1146 #ifdef __HWACCESS_DEBUG__
1147 /* check address alignment */
1148 if(addr & 0x3)
1149 {
1150 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1151 ("whal_hwAccess_ReadMem: addr is not aligned 0x%x\n",
1152 addr));
1153 }
1154
1155 #endif
1156
1157 #ifdef HW_ACCESS_SDIO
1158
1159 /* check address */
1160 if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
1161 {
1162 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1163 ("whal_hwAccess_ReadMem: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
1164 addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
1165 return ERROR_HW_ACCEESS_ADDR;
1166 }
1167
1168 request.buffer = data; /* Pointer to the data buffer aligned address. */
1169 request.buffer_len = len; /* Data buffer length in bytes */
1170 request.status = SDIO_Request_None;
1171 request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
1172 request.acquire_window = 0; /*Time out value is not set*/
1173 request.block_len = 0; /*Block length. Assigned by driver*/
1174 request.physical_buffer = 0; /*Physical address of data buffer is not set*/
1175 request.owner = (SDIO_Owner) pHwAccess;
1176 request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
1177 request.access_flag = 1;
1178
1179 os_profile (pHwAccess->hOs, 2, 0);
1180
1181 status = SDIO_SyncRead(pHwAccess->hDriver, &request);
1182
1183 os_profile (pHwAccess->hOs, 3, 0);
1184
1185 if (status != OK)
1186 {
1187 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1188 ("whal_hwAccess_ReadMem: SDIO Error in read\n"));
1189 return status;
1190 }
1191
1192 #elif defined(HW_ACCESS_WSPI)
1193
1194 /* check address */
1195 if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
1196 {
1197 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1198 ("whal_hwAccess_ReadMem: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
1199 addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
1200 return ERROR_HW_ACCEESS_ADDR;
1201 }
1202
1203 os_profile (pHwAccess->hOs, 2, 0);
1204
1205 /* read the aligned size */
1206 status = WSPI_ReadSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr),data,tempLen);
1207
1208 os_profile (pHwAccess->hOs, 3, 0);
1209
1210 if (status != OK)
1211 {
1212 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1213 ("whal_hwAccess_ReadMem: WSPI Error in read\n"));
1214 return status;
1215 }
1216
1217 /* read the non aligned reminder */
1218 if(reminder)
1219 {
1220 UINT32 tempVal = 0;
1221
1222 os_profile (pHwAccess->hOs, 2, 0);
1223
1224 /* read the extra data*/
1225 status |= WSPI_ReadSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr+tempLen),(UINT8*)&tempVal,HW_ACCESS_WSPI_ALIGNED_SIZE);
1226
1227 os_profile (pHwAccess->hOs, 3, 0);
1228
1229 if (status != OK)
1230 {
1231 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1232 ("whal_hwAccess_ReadMem: WSPI Error in read\n"));
1233 return status;
1234 }
1235
1236 /* extract the relevant data */
1237 switch(reminder)
1238 {
1239 case 1:
1240 mask = HW_ACCESS_1_BYTE_REMINDE_MASK;
1241 break;
1242 case 2:
1243 mask = HW_ACCESS_2_BYTE_REMINDE_MASK;
1244 break;
1245 case 3:
1246 mask = HW_ACCESS_3_BYTE_REMINDE_MASK;
1247 break;
1248 }
1249 *(UINT32*)&data[tempLen] &= ~mask;
1250 *(UINT32*)&data[tempLen] |= tempVal & mask;
1251 }
1252
1253 #else
1254 whal_hwAccess_DirectCopy_new(pHwAccess, data, (UINT8*)(pHwAccess->MemBaseAddr+addr), len);
1255 #endif
1256
1257 #ifdef HW_ACCESS_SDIO
1258 if (pHwAccess->uBusError)
1259 {
1260 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1261 ("whal_hwAccess_ReadMem: SDIO Error status=%d\n",
1262 request.status));
1263 if (pHwAccess->hwAccesserror_Cb)
1264 {
1265 UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
1266 pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,(char*)&failure_reason,2);
1267 }
1268 else
1269 pHwAccess->uBusError = 0;
1270 }
1271 #endif
1272
1273 return OK;
1274 }
1275
1276
1277
1278 /****************************************************************************
1279 * whal_hwAccess_WriteMem
1280 ****************************************************************************
1281 * DESCRIPTION: write data synchronously to the TNET using the defined access (WSPI/SDIO).
1282 * the length of data is checked and the remnant (length%4) is completed with read-modify-write
1283 *
1284 * INPUTS: pHwAccess - TI_HANDLE* - the HwAccess context
1285 * addr - UINT32 - the address offset inside the TNET
1286 * data - UINT8* - a pointer to the buffer that holds the data to write
1287 * Len - int - the length of the data to read
1288 *
1289 * OUTPUT: none
1290 *
1291 * RETURNS: one of the error codes (0 => OK)
1292 ****************************************************************************/
whal_hwAccess_WriteMem(TI_HANDLE hHwAccess,UINT32 addr,UINT8 * data,UINT16 len)1293 int whal_hwAccess_WriteMem(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
1294 {
1295 int status = OK;
1296 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
1297
1298 #ifdef HW_ACCESS_SDIO
1299 struct SDIO_Request request;
1300 #elif defined(HW_ACCESS_WSPI)
1301 int reminder = len % HW_ACCESS_WSPI_ALIGNED_SIZE;
1302 int tempLen = len - reminder;
1303 UINT32 mask = 0;
1304 status = whal_hwAccess_WriteMemAsync(hHwAccess, addr, data, len);
1305 if (status == TNETWIF_COMPLETE)
1306 {
1307 status = OK;
1308 }
1309 return status;
1310 #endif
1311
1312 /* access is blocked */
1313 if (pHwAccess->uBusError)
1314 {
1315 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_CTRL_MODULE_LOG,
1316 ("Bus is blocked \n"));
1317 return ERROR_HW_ACCEESS_ADDR;
1318 }
1319
1320 #ifdef __HWACCESS_DEBUG__
1321 /* check address alignment */
1322 if(addr & 0x3)
1323 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1324 ("whal_hwAccess_WriteMem: addr is not aligned 0x%x\n",
1325 addr));
1326 #endif
1327
1328 #ifdef HW_ACCESS_SDIO
1329
1330 /* check address */
1331 if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
1332 {
1333 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1334 ("whal_hwAccess_WriteMem: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
1335 addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
1336 return ERROR_HW_ACCEESS_ADDR;
1337 }
1338
1339 request.buffer = data; /* Pointer to the data buffer aligned address. */
1340 request.buffer_len = len; /* Data buffer length in bytes */
1341 request.status = SDIO_Request_None;
1342 request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
1343 request.acquire_window = 0; /*Time out value is not set*/
1344 request.block_len = 0; /*Block length. Assigned by driver*/
1345 request.physical_buffer = 0; /*Physical address of data buffer is not set*/
1346 request.owner = (SDIO_Owner) pHwAccess;
1347 request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
1348 request.access_flag = 0;
1349
1350 os_profile (pHwAccess->hOs, 2, 0);
1351
1352 status = SDIO_SyncWrite(pHwAccess->hDriver, &request);
1353
1354 os_profile (pHwAccess->hOs, 3, 0);
1355
1356 if (status != OK)
1357 {
1358 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1359 ("whal_hwAccess_WriteMem: SDIO Error in write (%d)\n", status));
1360 return status;
1361 }
1362
1363 #elif defined(HW_ACCESS_WSPI)
1364
1365 /* check address */
1366 if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
1367 {
1368 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1369 ("whal_hwAccess_WriteMem: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
1370 addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
1371 return ERROR_HW_ACCEESS_ADDR;
1372 }
1373
1374 os_profile (pHwAccess->hOs, 2, 0);
1375
1376 /* write the aligned size */
1377 status = WSPI_WriteSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr),data,tempLen);
1378
1379 os_profile (pHwAccess->hOs, 3, 0);
1380
1381
1382 if (status != OK)
1383 {
1384 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1385 ("whal_hwAccess_WriteMem: WSPI Error in write\n"));
1386 return status;
1387 }
1388
1389 /* read the non aligned reminder */
1390 if(reminder)
1391 {
1392 UINT32 tempVal;
1393
1394 os_profile (pHwAccess->hOs, 2, 0);
1395
1396 /* read the extra data*/
1397 status |= WSPI_ReadSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr + tempLen),(UINT8*)&tempVal,HW_ACCESS_WSPI_ALIGNED_SIZE);
1398
1399 os_profile (pHwAccess->hOs, 3, 0);
1400
1401 if (status != OK)
1402 {
1403 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1404 ("whal_hwAccess_WriteMem: WSPI Error in read\n"));
1405 return status;
1406 }
1407
1408 /* extract the relevant data */
1409 switch(reminder)
1410 {
1411 case 1:
1412 mask = HW_ACCESS_1_BYTE_REMINDE_MASK;
1413 break;
1414 case 2:
1415 mask = HW_ACCESS_2_BYTE_REMINDE_MASK;
1416 break;
1417 case 3:
1418 mask = HW_ACCESS_3_BYTE_REMINDE_MASK;
1419 break;
1420 }
1421
1422 tempVal &= ~mask;
1423 tempVal |= *(UINT32*)&data[tempLen] & mask;
1424
1425 os_profile (pHwAccess->hOs, 2, 0);
1426
1427 /* write the modified extra data */
1428 status = WSPI_WriteSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr + tempLen),(UINT8*)&tempVal,HW_ACCESS_WSPI_ALIGNED_SIZE);
1429
1430 os_profile (pHwAccess->hOs, 3, 0);
1431
1432 if (status != OK)
1433 {
1434 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1435 ("whal_hwAccess_WriteMem: WSPI Error in write\n"));
1436 return status;
1437 }
1438 }
1439
1440 #else
1441 whal_hwAccess_DirectCopy_new(pHwAccess, (UINT8*)(pHwAccess->MemBaseAddr+addr), data, len);
1442 #endif
1443
1444 #ifdef HW_ACCESS_SDIO
1445 if (pHwAccess->uBusError)
1446 {
1447 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1448 ("whal_hwAccess_WriteMem: SDIO Error in write status=%d\n",
1449 request.status));
1450 if (pHwAccess->hwAccesserror_Cb)
1451 {
1452 UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
1453 pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,(char*)&failure_reason,2);
1454 }
1455 else
1456 pHwAccess->uBusError = 0;
1457
1458 }
1459 #endif
1460 return OK;
1461 }
1462 #endif /* USE_SYNC_API */
1463
1464
1465 /****************************************************************************
1466 * whal_hwAccess_WriteMemAsync
1467 ****************************************************************************
1468 * DESCRIPTION: write data synchronously from the TNET using the defined access (WSPI/SDIO).
1469 * the length of data is checked and the remnant (length%4) is completed with read-modify-write
1470 * the function is passed a call-back function that will be called after the read request ends.
1471 *
1472 * INPUTS: pHwAccess - TI_HANDLE* - the HwAccess context
1473 * addr - UINT32 - the address offset inside the TNET
1474 * data - UINT8* - a pointer to the buffer that holds the data to write
1475 * Len - int - the length of the data to read
1476 * CB - HWAccess_CB_T* - a pointer to a structure that holds the CB function and the passed arg.
1477 *
1478 * OUTPUT: none
1479 *
1480 * RETURNS: one of the error codes (0 => OK)
1481 ****************************************************************************/
whal_hwAccess_WriteMemAsync(TI_HANDLE hHwAccess,UINT32 addr,UINT8 * data,UINT16 len)1482 TI_STATUS whal_hwAccess_WriteMemAsync(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
1483 {
1484 #if defined(HW_ACCESS_SDIO) && !defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
1485
1486 /* Just call to synchronous API - add the offset that was added to the WSPI bus - only if it was reserved*/
1487 return (whal_hwAccess_WriteMem (hHwAccess, addr, data + TNETWIF_WRITE_OFFSET_BYTES, len) == OK)
1488 ? TNETWIF_COMPLETE
1489 : TNETWIF_ERROR;
1490
1491 #else
1492
1493 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
1494 int status = OK;
1495
1496 /* Access is blocked */
1497 if (pHwAccess->uBusError)
1498 {
1499 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_CTRL_MODULE_LOG,
1500 ("Bus is blocked \n"));
1501 return (TI_STATUS)ERROR_HW_ACCEESS_ADDR;
1502 }
1503
1504 /* Check length */
1505 if ((len & 0x3) != 0)
1506 {
1507 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1508 ("whal_hwAccess_WriteMemAsync: Error in length = %d\n",
1509 len));
1510 return (TI_STATUS)ERROR_HW_ACCEESS_LEN;
1511 }
1512
1513 /* Check address */
1514 if (addr + len > pHwAccess->workingPartUpperLimit ||
1515 addr < pHwAccess->MemRegionAddr)
1516 {
1517 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1518 ("whal_hwAccess_WriteMemAsync: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
1519 addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
1520 return (TI_STATUS)ERROR_HW_ACCEESS_ADDR;
1521 }
1522
1523 #if defined(HW_ACCESS_SDIO)
1524 {
1525 struct SDIO_Request request;
1526
1527 request.buffer = data + TNETWIF_WRITE_OFFSET_BYTES; /*Pointer to the data buffer aligned address*/
1528 request.buffer_len = len; /*Data buffer length in bytes*/
1529 request.status = SDIO_Request_None;
1530 request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
1531 request.acquire_window = 0; /* Time out value is not set */
1532 request.block_len = 0; /* Block length. Assigned by driver */
1533 request.physical_buffer = 0; /* Physical address of data buffer is not set */
1534 request.owner = (SDIO_Owner) pHwAccess;
1535 request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
1536 request.access_flag = 0;
1537 request.fnotify = sdio_async_transaction_notify; /* completion notification */
1538 request.ferror = sdio_async_transaction_error; /* error notification */
1539
1540 os_profile (pHwAccess->hOs, 2, 0);
1541
1542 status = SDIO_AsyncWrite (pHwAccess->hDriver, &request);
1543
1544 os_profile (pHwAccess->hOs, 3, 0);
1545
1546 if (status != OK)
1547 {
1548 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1549 ("whal_hwAccess_WriteMemAsync: Error in write async, addr=0x%08x status=%d\n",
1550 addr, status));
1551 return TNETWIF_ERROR;
1552 }
1553
1554 if (pHwAccess->uBusError)
1555 {
1556 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1557 ("whal_hwAccess_WriteMemAsync: SDIO Error in write status=%d\n",
1558 request.status));
1559 if (pHwAccess->hwAccesserror_Cb)
1560 {
1561 UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
1562 pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,&failure_reason,2);
1563 }
1564 else
1565 pHwAccess->uBusError = 0;
1566
1567 }
1568
1569 return TNETWIF_COMPLETE;
1570 }
1571
1572 #elif defined(HW_ACCESS_WSPI)
1573
1574 os_profile (pHwAccess->hOs, 2, 0);
1575
1576 status = WSPI_WriteAsync (pHwAccess->hDriver,
1577 TRANSLATE_ADDRESS_MEM(addr),
1578 data,
1579 len,
1580 (WSPI_CB_T*)&pHwAccess->CB,
1581 TRUE,
1582 TRUE); /* place is always reserved in write mem operation */
1583
1584 os_profile (pHwAccess->hOs, 3, 0);
1585
1586 WSPI2TNETWIF (pHwAccess, status, addr);
1587
1588 return (TI_STATUS)status;
1589
1590 #else
1591
1592 /* By now since the CB is a SYNCH interface then call the SYNCH interface */
1593 whal_hwAccess_DirectCopy_new(pHwAccess, (UINT8*)(pHwAccess->MemBaseAddr+addr), data, len);
1594
1595 return OK;
1596
1597 #endif
1598
1599 #endif
1600 }
1601
1602
1603 /****************************************************************************
1604 * whal_hwAccess_ReadMemAsync
1605 ****************************************************************************
1606 * DESCRIPTION: read data asynchronously from the TNET using the defined access (WSPI/SDIO).
1607 * the length of data is checked and the remnant (length%4) is completed with read-modify
1608 * the function is passed a call-back function that will be called after the read request ends.
1609 *
1610 * INPUTS: pHwAccess - TI_HANDLE* - the HwAccess context
1611 * addr - UINT32 - the address offset inside the TNET
1612 * Len - int - the length of the data to read
1613 * CB - HWAccess_CB_T* - a pointer to a structure that holds the CB function and the passed arg.
1614 *
1615 * OUTPUT: data - UINT8* - a pointer to the buffer to fill with the read data
1616 *
1617 * RETURNS: one of the error codes (0 => OK)
1618 ****************************************************************************/
whal_hwAccess_ReadMemAsync(TI_HANDLE hHwAccess,UINT32 addr,UINT8 * data,UINT16 len)1619 int whal_hwAccess_ReadMemAsync (TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
1620 {
1621 #if defined(HW_ACCESS_SDIO) && !defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
1622
1623 /* Just call to synchronous API - add the offset that was added to the WSPI bus */
1624 return (whal_hwAccess_ReadMem (hHwAccess, addr, data + TNETWIF_READ_OFFSET_BYTES, len) == OK)
1625 ? TNETWIF_COMPLETE
1626 : TNETWIF_ERROR;
1627
1628 #else
1629
1630 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
1631 int status = OK;
1632
1633 /* Access is blocked */
1634 if (pHwAccess->uBusError)
1635 {
1636 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_CTRL_MODULE_LOG,
1637 ("Bus is blocked \n"));
1638 return ERROR_HW_ACCEESS_ADDR;
1639 }
1640
1641 /* Check length */
1642 if ((len & 0x3) != 0)
1643 {
1644 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1645 ("whal_hwAccess_ReadMemAsync: Error in length = %d\n",
1646 len));
1647 return ERROR_HW_ACCEESS_LEN;
1648 }
1649
1650 /* Check address */
1651 if (addr + len > pHwAccess->workingPartUpperLimit ||
1652 addr < pHwAccess->MemRegionAddr)
1653 {
1654 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1655 ("whal_hwAccess_ReadMemAsync: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
1656 addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
1657 return ERROR_HW_ACCEESS_ADDR;
1658 }
1659
1660 #if defined(HW_ACCESS_SDIO)
1661 {
1662 struct SDIO_Request request;
1663
1664 request.buffer = data + TNETWIF_READ_OFFSET_BYTES; /*Pointer to the data buffer aligned address*/
1665 request.buffer_len = len; /*Data buffer length in bytes*/
1666 request.status = SDIO_Request_None;
1667 request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
1668 request.acquire_window = 0; /* Time out value is not set */
1669 request.block_len = 0; /* Block length. Assigned by driver */
1670 request.physical_buffer = 0; /* Physical address of data buffer is not set */
1671 request.owner = (SDIO_Owner) pHwAccess;
1672 request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
1673 request.access_flag = 0;
1674 request.fnotify = sdio_async_transaction_notify; /* completion notification */
1675 request.ferror = sdio_async_transaction_error; /* error notification */
1676
1677 os_profile (pHwAccess->hOs, 2, 0);
1678
1679 status = SDIO_AsyncRead (pHwAccess->hDriver, &request);
1680
1681 os_profile (pHwAccess->hOs, 3, 0);
1682
1683 if (status != OK)
1684 {
1685 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1686 ("whal_hwAccess_ReadMemAsync: Error in write async, addr=0x%08x status=%d\n",
1687 addr, status));
1688 return TNETWIF_ERROR;
1689 }
1690
1691 if (pHwAccess->uBusError)
1692 {
1693 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1694 ("whal_hwAccess_ReadMemAsync: SDIO Error in write SrcOffset=0x%08x status=%d\n",
1695 SrcOffset, request.status));
1696 if (pHwAccess->hwAccesserror_Cb)
1697 {
1698 UINT16 failure_reason = HEALTH_REPORT_BUS_ERROR;
1699 pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,&failure_reason,2);
1700 }
1701 else
1702 pHwAccess->uBusError = 0;
1703 }
1704
1705 return TNETWIF_COMPLETE;
1706 }
1707
1708 #elif defined(HW_ACCESS_WSPI)
1709
1710 os_profile (pHwAccess->hOs, 2, 0);
1711
1712 status = WSPI_ReadAsync (pHwAccess->hDriver,
1713 TRANSLATE_ADDRESS_MEM(addr),
1714 data,
1715 len,
1716 (WSPI_CB_T*)&pHwAccess->CB,
1717 TRUE,
1718 TRUE); /* place is always reserved in readMem */
1719
1720 os_profile (pHwAccess->hOs, 3, 0);
1721
1722 WSPI2TNETWIF (pHwAccess, status, addr);
1723
1724 return status;
1725
1726 #endif
1727
1728 #endif
1729 }
1730
1731
1732 #ifdef USE_SYNC_API
1733 /****************************************************************************
1734 * whal_hwAccess_ReadReg
1735 ****************************************************************************
1736 * DESCRIPTION: read data synchronously from the TNET using the defined access (WSPI/SDIO).
1737 * the length of data is always 4bytes cause this is the size of the TNET registers
1738 *
1739 * INPUTS: pHwAccess - HwAccess_T_new* - the HwAccess context
1740 * addr - UINT32 - the address offset inside the TNET
1741 * Len - int - the length of the data to read
1742 *
1743 * OUTPUT: data - UINT8* - a pointer to the buffer to fill with the read data
1744 *
1745 * RETURNS: one of the error codes (0 => OK)
1746 ****************************************************************************/
whal_hwAccess_ReadReg(TI_HANDLE hHwAccess,UINT32 addr,UINT32 * data)1747 int whal_hwAccess_ReadReg(TI_HANDLE hHwAccess, UINT32 addr, UINT32* data)
1748 {
1749 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
1750 int status = OK;
1751
1752 #ifdef HW_ACCESS_SDIO
1753 struct SDIO_Request request;
1754
1755 /* check address */
1756 if (addr > pHwAccess->registerPartUpperLimit)
1757 {
1758 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1759 ("whal_hwAccess_ReadReg: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
1760 addr, pHwAccess->RegisterRegionAddr, pHwAccess->registerPartUpperLimit));
1761 return ERROR_HW_ACCEESS_ADDR;
1762 }
1763
1764 request.buffer = (UINT8*)data; /*Pointer to the data buffer aligned address.*/
1765 request.buffer_len = HW_ACCESS_REGISTER_SIZE; /*Data buffer length in bytes*/
1766 request.status = SDIO_Request_None;
1767 request.peripheral_addr = TRANSLATE_ADDRESS_REG(addr);
1768 request.acquire_window = 0; /* Time out value is not set */
1769 request.block_len = 0; /* Block length. Assigned by driver */
1770 request.owner = (SDIO_Owner) pHwAccess;
1771 request.physical_buffer = 0; /* Physical address of data buffer is not set */
1772 request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
1773 request.access_flag = 1;
1774
1775 os_profile (pHwAccess->hOs, 2, 0);
1776
1777 status = SDIO_SyncRead(pHwAccess->hDriver, &request);
1778
1779 os_profile (pHwAccess->hOs, 3, 0);
1780
1781
1782 #elif defined(HW_ACCESS_WSPI)
1783
1784 status = whal_hwAccess_ReadRegAsync(hHwAccess, addr, data);
1785 if (status == TNETWIF_COMPLETE)
1786 {
1787 status = OK;
1788 }
1789 return status;
1790 /* check address */
1791 if ((addr > pHwAccess->registerPartUpperLimit) || (addr < 0))
1792 {
1793 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1794 ("whal_hwAccess_ReadReg: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
1795 addr, pHwAccess->RegisterRegionAddr, pHwAccess->registerPartUpperLimit));
1796 return ERROR_HW_ACCEESS_ADDR;
1797 }
1798
1799 os_profile (pHwAccess->hOs, 2, 0);
1800
1801 status = WSPI_ReadSync(pHwAccess->hDriver, TRANSLATE_ADDRESS_REG(addr), (UINT8*)data, HW_ACCESS_REGISTER_SIZE);
1802
1803 os_profile (pHwAccess->hOs, 3, 0);
1804
1805 #else
1806
1807 HW_REG_LONG_READ(pHwAccess,addr,data);
1808
1809 #endif
1810
1811 if (status != OK)
1812 {
1813 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1814 ("whal_hwAccess_ReadReg: Error in reg read RegAddr=0x%08x status=%d\n",
1815 addr, status));
1816
1817 }
1818
1819 #ifdef HW_ACCESS_SDIO
1820 if (pHwAccess->uBusError)
1821 {
1822 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1823 ("whal_hwAccess_ReadReg: SDIO Error status=%d\n",
1824 request.status));
1825 if (pHwAccess->hwAccesserror_Cb)
1826 {
1827 UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
1828 pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,(char *)&failure_reason,2);
1829 }
1830 else
1831 pHwAccess->uBusError = 0;
1832 }
1833 #endif
1834 return status;
1835 }
1836 #endif /* USE_SYNC_API */
1837
1838
1839 /****************************************************************************
1840 * whal_hwAccess_Stop()
1841 ****************************************************************************
1842 * DESCRIPTION: stops the bus driver
1843 *
1844 * INPUTS: None
1845 *
1846 * OUTPUT: None
1847 *
1848 * RETURNS:
1849 ****************************************************************************/
whal_hwAccess_Stop(TI_HANDLE hHwAccess)1850 int whal_hwAccess_Stop(TI_HANDLE hHwAccess)
1851 {
1852 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
1853
1854 /* unbclock the access to the bus */
1855 pHwAccess->uBusError = 0;
1856
1857 #ifdef HW_ACCESS_SDIO
1858 SDIO_Stop(pHwAccess->hDriver,0);
1859 #elif defined(HW_ACCESS_WSPI)
1860 /* TODO*/
1861 #endif
1862 return OK;
1863 }
1864
1865
1866 #ifdef USE_SYNC_API
1867
1868 /****************************************************************************
1869 * whal_hwAccess_WriteReg
1870 ****************************************************************************
1871 * DESCRIPTION: write data synchronously to the TNET using the defined access (WSPI/SDIO).
1872 * the length of data is always 4bytes cause this is the size of the TNET registers
1873 *
1874 * INPUTS: pHwAccess - TI_HANDLE * - the HwAccess context
1875 * addr - UINT32 - the address offset inside the TNET
1876 * data - UINT8* - a pointer to the buffer that holds the data to write
1877 * Len - int - the length of the data to read
1878 *
1879 * OUTPUT: none
1880 *
1881 * RETURNS: one of the error codes (0 => OK)
1882 ****************************************************************************/
whal_hwAccess_WriteReg(TI_HANDLE hHwAccess,UINT32 addr,UINT32 data)1883 int whal_hwAccess_WriteReg(TI_HANDLE hHwAccess, UINT32 addr, UINT32 data)
1884 {
1885 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
1886 int status = OK;
1887
1888 #ifdef HW_ACCESS_SDIO
1889 struct SDIO_Request request;
1890
1891 /* check address */
1892 if (addr > pHwAccess->registerPartUpperLimit)
1893 {
1894 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1895 ("whal_hwAccess_WriteReg: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
1896 addr, pHwAccess->RegisterRegionAddr, pHwAccess->registerPartUpperLimit));
1897 return ERROR_HW_ACCEESS_ADDR;
1898 }
1899
1900 request.buffer = (UINT8*)&data; /*Pointer to the data buffer aligned address.*/
1901 request.buffer_len = HW_ACCESS_REGISTER_SIZE; /*Data buffer length in bytes*/
1902 request.status = SDIO_Request_None;
1903 request.peripheral_addr = TRANSLATE_ADDRESS_REG(addr);
1904 request.acquire_window = 0; /* Time out value is not set */
1905 request.block_len = 0; /* Block length. Assigned by driver */
1906 request.owner = (SDIO_Owner) pHwAccess;
1907 request.physical_buffer = 0; /* Physical address of data buffer is not set */
1908 request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
1909 request.access_flag = 0;
1910
1911 os_profile (pHwAccess->hOs, 2, 0);
1912
1913 status = SDIO_SyncWrite(pHwAccess->hDriver, &request);
1914
1915 os_profile (pHwAccess->hOs, 3, 0);
1916
1917 #elif defined(HW_ACCESS_WSPI)
1918 status = whal_hwAccess_WriteRegAsync(hHwAccess, addr, data);
1919 if (status == TNETWIF_COMPLETE)
1920 {
1921 status = OK;
1922 }
1923 return status;
1924 /* check address */
1925 if ((addr > pHwAccess->registerPartUpperLimit) || (addr < 0))
1926 {
1927 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1928 ("whal_hwAccess_WriteReg: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
1929 addr, pHwAccess->RegisterRegionAddr, pHwAccess->registerPartUpperLimit));
1930 return ERROR_HW_ACCEESS_ADDR;
1931 }
1932
1933 os_profile (pHwAccess->hOs, 2, 0);
1934
1935 status = WSPI_WriteSync(pHwAccess->hDriver, TRANSLATE_ADDRESS_REG(addr), (UINT8*)&data, HW_ACCESS_REGISTER_SIZE);
1936
1937 os_profile (pHwAccess->hOs, 3, 0);
1938
1939 #else
1940
1941 HW_REG_LONG_WRITE(pHwAccess, addr, data);
1942
1943 #endif
1944
1945 if (status != OK)
1946 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1947 ("whal_hwAccess_WriteReg: Error in reg write RegAddr=0x%08x status=%d\n",
1948 addr, status));
1949
1950 #ifdef HW_ACCESS_SDIO
1951 if (pHwAccess->uBusError)
1952 {
1953 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
1954 ("whal_hwAccess_WriteReg: SDIO Error in write status=%d\n",
1955 request.status));
1956 if (pHwAccess->hwAccesserror_Cb)
1957 {
1958 UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
1959 pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,(char *)&failure_reason,2);
1960 }
1961 else
1962 pHwAccess->uBusError = 0;
1963
1964 }
1965 #endif
1966 return status;
1967 }
1968 #endif /* USE_SYNC_API */
1969
1970
1971 /****************************************************************************
1972 * whal_hwAccess_ReadRegAsync
1973 ****************************************************************************
1974 * DESCRIPTION: read data asynchronously from the TNET using the defined access (WSPI/SDIO).
1975 * the length of data is always 4bytes cause this is the size of the TNET registers
1976 * the function is passed a call-back function that will be called after the read request ends.
1977 *
1978 * INPUTS: pHwAccess - TI_HANDLE * - the HwAccess context
1979 * addr - UINT32 - the address offset inside the TNET
1980 *
1981 * OUTPUT: data - UINT8* - a pointer to the buffer to fill with the read data
1982 *
1983 * RETURNS: one of the error codes (0 => OK)
1984 ****************************************************************************/
whal_hwAccess_ReadRegAsync(TI_HANDLE hHwAccess,UINT32 addr,UINT32 * data)1985 int whal_hwAccess_ReadRegAsync(TI_HANDLE hHwAccess, UINT32 addr, UINT32* data)
1986 {
1987 #if defined(HW_ACCESS_SDIO)
1988
1989 #if defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
1990
1991 #error "SDIO asynchronous mode is not supported"
1992
1993 /* Not implemented yet */
1994 return OK;
1995
1996 #else
1997
1998 /* Just call to synchronous API */
1999 return (whal_hwAccess_ReadReg (hHwAccess, addr, data) == OK)
2000 ? TNETWIF_COMPLETE
2001 : TNETWIF_ERROR;
2002
2003 #endif
2004
2005 #else /* HW_ACCESS_WSPI */
2006
2007 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
2008 int status;
2009
2010 /* Check address */
2011 if (addr > pHwAccess->registerPartUpperLimit)
2012 {
2013 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
2014 ("whal_hwAccess_ReadRegAsync: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
2015 addr, pHwAccess->RegisterRegionAddr, pHwAccess->registerPartUpperLimit));
2016 return ERROR_HW_ACCEESS_ADDR;
2017 }
2018
2019 os_profile (pHwAccess->hOs, 2, 0);
2020
2021 /* In registers we don't save place */
2022 status = WSPI_ReadAsync (pHwAccess->hDriver,
2023 TRANSLATE_ADDRESS_REG(addr),
2024 (UINT8*)data,
2025 HW_ACCESS_REGISTER_SIZE,
2026 (WSPI_CB_T*)&pHwAccess->CB,
2027 TRUE,
2028 FALSE);
2029
2030 os_profile (pHwAccess->hOs, 3, 0);
2031
2032 WSPI2TNETWIF (pHwAccess, status, addr);
2033
2034 return status;
2035
2036 #endif
2037 }
2038
2039 /****************************************************************************
2040 * whal_hwAccess_WriteRegAsync
2041 ****************************************************************************
2042 * DESCRIPTION: write data synchronously from the TNET using the defined access (WSPI/SDIO).
2043 * the length of data is always 4bytes cause this is the size of the TNET registers
2044 * the function is passed a call-back function that will be called after the read request ends.
2045 *
2046 * INPUTS: pHwAccess - TI_HANDLE * - the HwAccess context
2047 * addr - UINT32 - the address offset inside the TNET
2048 * data - UINT8* - a pointer to the buffer that holds the data to write
2049 *
2050 * OUTPUT: none
2051 *
2052 * RETURNS: one of the error codes (0 => OK)
2053 ****************************************************************************/
whal_hwAccess_WriteRegAsync(TI_HANDLE hHwAccess,UINT32 addr,UINT32 data)2054 int whal_hwAccess_WriteRegAsync(TI_HANDLE hHwAccess, UINT32 addr, UINT32 data)
2055 {
2056 #if defined(HW_ACCESS_SDIO)
2057
2058 #if defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
2059
2060 #error "SDIO asynchronous mode is not supported"
2061
2062 /* Not implemented yet */
2063 return OK;
2064
2065 #else
2066
2067 /* Just call to synchronous API */
2068 return (whal_hwAccess_WriteReg (hHwAccess, addr, data) == OK)
2069 ? TNETWIF_COMPLETE
2070 : TNETWIF_ERROR;
2071
2072 #endif
2073
2074 #else /* HW_ACCESS_WSPI */
2075
2076 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
2077 int status;
2078
2079 /* Check address */
2080 if (addr > pHwAccess->registerPartUpperLimit)
2081 {
2082 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
2083 ("whal_hwAccess_WriteRegAsync: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
2084 addr, pHwAccess->RegisterRegionAddr, pHwAccess->registerPartUpperLimit));
2085 return ERROR_HW_ACCEESS_ADDR;
2086 }
2087
2088 os_profile (pHwAccess->hOs, 2, 0);
2089
2090 status = WSPI_WriteAsync (pHwAccess->hDriver,
2091 TRANSLATE_ADDRESS_REG(addr),
2092 (UINT8*)&data,
2093 HW_ACCESS_REGISTER_SIZE,
2094 (WSPI_CB_T*)&pHwAccess->CB,
2095 TRUE,
2096 FALSE);
2097 os_profile (pHwAccess->hOs, 3, 0);
2098
2099 WSPI2TNETWIF (pHwAccess, status, addr);
2100
2101 return status;
2102 #endif
2103 }
2104
2105
2106 #ifdef USE_SYNC_API
2107 /****************************************************************************
2108 * whal_hwAccess_SetPartitions
2109 ****************************************************************************
2110 * DESCRIPTION: the client always sees two partitions
2111 * 1 - the working partition that the client access it with mem functions (for this partition the client supplies the base address)
2112 * 2 - the registers partition that is always set on HW_ACCESS_REG_ADDR and its size is HW_ACCESS_REG_SIZE.
2113 *
2114 * INPUTS: pHwAccess - a pointer to the module context
2115 * partitionMode - the mode to set the partitions
2116 * partition_start - the start address of the working partition
2117 *
2118 * OUTPUT: none
2119 *
2120 * RETURNS: one of the error codes (0 => OK)
2121 ****************************************************************************/
whal_hwAccess_SetPartitions(TI_HANDLE hHwAccess,TNETIF_HwAccess_SetPartition_mode_e partitionMode,UINT32 partition_start)2122 int whal_hwAccess_SetPartitions (TI_HANDLE hHwAccess, TNETIF_HwAccess_SetPartition_mode_e partitionMode, UINT32 partition_start)
2123 {
2124 HwAccess_T_new *pHwAccess = (HwAccess_T_new*) hHwAccess;
2125 int status = OK;
2126
2127 #ifdef HW_ACCESS_SDIO
2128 SDIO_TNETWConfigParams sdioConfParam;
2129 Peripheral_ConfigParams *cfg;
2130 #endif
2131
2132 pHwAccess->partition[0].size = 0;
2133 pHwAccess->partition[0].start = partition_start;
2134 pHwAccess->partition[1].size = 0;
2135 pHwAccess->partition[1].start = 0;
2136
2137 switch(partitionMode)
2138 {
2139 case HW_ACCESS_DOWNLOAD:
2140 pHwAccess->partition[0].size = HW_ACCESS_MEMORY_MAX_RANGE - HW_ACCESS_DOWN_PART1_SIZE;
2141 pHwAccess->partition[1].start = HW_ACCESS_DOWN_PART1_ADDR;
2142 pHwAccess->partition[1].size = HW_ACCESS_DOWN_PART1_SIZE;
2143 break;
2144 case HW_ACCESS_WORKING:
2145 pHwAccess->partition[0].size = HW_ACCESS_MEMORY_MAX_RANGE - HW_ACCESS_WORK_PART1_SIZE;
2146 pHwAccess->partition[1].start = HW_ACCESS_WORK_PART1_ADDR;
2147 pHwAccess->partition[1].size = HW_ACCESS_WORK_PART1_SIZE;
2148 break;
2149 }
2150
2151 #if (defined(HW_ACCESS_SDIO) || defined(HW_ACCESS_WSPI))
2152 /* guarantee that the working partition wont overlap the registers partition */
2153 if((pHwAccess->partition[0].start + pHwAccess->partition[0].size) > pHwAccess->partition[1].start)
2154 pHwAccess->partition[0].size = pHwAccess->partition[1].start - pHwAccess->partition[0].start;
2155
2156 /* guarantee that the working partition won't exceed the packet RAM */
2157 if((pHwAccess->partition[0].start + pHwAccess->partition[0].size) > HW_ACCESS_PRAM_MAX_RANGE)
2158 pHwAccess->partition[0].size = HW_ACCESS_PRAM_MAX_RANGE - pHwAccess->partition[0].start;
2159
2160 pHwAccess->workingPartUpperLimit = pHwAccess->partition[0].start + pHwAccess->partition[0].size;
2161 pHwAccess->registerPartUpperLimit = pHwAccess->partition[1].size;
2162
2163 pHwAccess->RegisterRegionAddr = pHwAccess->partition[0].size;
2164 pHwAccess->MemRegionAddr = pHwAccess->partition[0].start;
2165
2166 #ifdef HW_ACCESS_SDIO
2167
2168 os_memoryZero (pHwAccess->hOs, &sdioConfParam, sizeof(SDIO_TNETWConfigParams));
2169 sdioConfParam.num_of_parts = 2;
2170 sdioConfParam.map_reg[0].reg_size = pHwAccess->partition[0].size;
2171 sdioConfParam.map_reg[0].scr_offset = pHwAccess->partition[0].start;
2172 sdioConfParam.map_reg[1].reg_size = pHwAccess->partition[1].size;
2173 sdioConfParam.map_reg[1].scr_offset = pHwAccess->partition[1].start;
2174
2175 status = SDIO_TNETWInit(&sdioConfParam);
2176 status = (status == SDIO_SUCCESS) ? SDIO_TNETWConfig(pHwAccess->hDriver, &cfg) : status;
2177 status = (status == SDIO_SUCCESS) ? TNETWIF_COMPLETE : TNETWIF_ERROR;
2178
2179 #elif defined(HW_ACCESS_WSPI)
2180 /*
2181 * IMPORTANT NOTE (TODO): the ASYNC API is used here assuming the call will always
2182 * be completed synchronously. This is done because only the Async API is wokring
2183 * in 4.0.4. In future versions, the whole recovery process should be made asynchronous.
2184 */
2185 /* May use only one write because the addresses in the firmware are sequential */
2186 status = WSPI_WriteAsync (pHwAccess->hDriver,
2187 HW_ACCESS_PART0_SIZE_ADDR,
2188 PADWRITE (pHwAccess->partition),
2189 sizeof(partition_t) * 2,
2190 (WSPI_CB_T*)&pHwAccess->CB,
2191 TRUE, TRUE);
2192
2193 WSPI2TNETWIF (pHwAccess, status, HW_ACCESS_PART0_SIZE_ADDR);
2194 #endif
2195
2196 #endif
2197
2198 return status;
2199 }
2200 #endif /* USE_SYNC_API */
2201
2202
2203 /****************************************************************************
2204 * whal_hwAccess_SetPartitionsAsync
2205 ****************************************************************************
2206 * DESCRIPTION: the client always sees two partitions
2207 * 1 - the working partition that the client access it with mem functions (for this partition the client supplies the base address)
2208 * 2 - the registers partition that is always set on HW_ACCESS_REG_ADDR and its size is HW_ACCESS_REG_SIZE.
2209 *
2210 * INPUTS: pHwAccess - a pointer to the module context
2211 * partitionMode - the mode to set the partitions
2212 * partition_start - the start address of the working partition
2213 *
2214 * OUTPUT: none
2215 *
2216 * RETURNS: one of the error codes (0 => OK)
2217 ****************************************************************************/
whal_hwAccess_SetPartitionsAsync(TI_HANDLE hHwAccess,TNETIF_HwAccess_SetPartition_mode_e partitionMode,UINT32 partition_start)2218 int whal_hwAccess_SetPartitionsAsync (TI_HANDLE hHwAccess, TNETIF_HwAccess_SetPartition_mode_e partitionMode, UINT32 partition_start)
2219 {
2220 HwAccess_T_new *pHwAccess = (HwAccess_T_new*) hHwAccess;
2221 int status = OK;
2222
2223 #ifdef HW_ACCESS_SDIO
2224 SDIO_TNETWConfigParams sdioConfParam;
2225 Peripheral_ConfigParams *cfg;
2226 #endif
2227
2228 pHwAccess->partition[0].size = 0;
2229 pHwAccess->partition[0].start = partition_start;
2230 pHwAccess->partition[1].size = 0;
2231 pHwAccess->partition[1].start = 0;
2232
2233 switch(partitionMode)
2234 {
2235 case HW_ACCESS_DOWNLOAD:
2236 pHwAccess->partition[0].size = HW_ACCESS_MEMORY_MAX_RANGE - HW_ACCESS_DOWN_PART1_SIZE;
2237 pHwAccess->partition[1].start = HW_ACCESS_DOWN_PART1_ADDR;
2238 pHwAccess->partition[1].size = HW_ACCESS_DOWN_PART1_SIZE;
2239 break;
2240 case HW_ACCESS_WORKING:
2241 pHwAccess->partition[0].size = HW_ACCESS_MEMORY_MAX_RANGE - HW_ACCESS_WORK_PART1_SIZE;
2242 pHwAccess->partition[1].start = HW_ACCESS_WORK_PART1_ADDR;
2243 pHwAccess->partition[1].size = HW_ACCESS_WORK_PART1_SIZE;
2244 break;
2245 }
2246
2247 #if (defined(HW_ACCESS_SDIO) || defined(HW_ACCESS_WSPI))
2248 /* guarantee that the working partition wont overlap the registers partition */
2249 if((pHwAccess->partition[0].start + pHwAccess->partition[0].size) > pHwAccess->partition[1].start)
2250 pHwAccess->partition[0].size = pHwAccess->partition[1].start - pHwAccess->partition[0].start;
2251
2252 /* guarantee that the working partition won't exceed the packet RAM */
2253 if((pHwAccess->partition[0].start + pHwAccess->partition[0].size) > HW_ACCESS_PRAM_MAX_RANGE)
2254 pHwAccess->partition[0].size = HW_ACCESS_PRAM_MAX_RANGE - pHwAccess->partition[0].start;
2255
2256 pHwAccess->workingPartUpperLimit = pHwAccess->partition[0].start + pHwAccess->partition[0].size;
2257 pHwAccess->registerPartUpperLimit = pHwAccess->partition[1].size;
2258
2259 pHwAccess->RegisterRegionAddr = pHwAccess->partition[0].size;
2260 pHwAccess->MemRegionAddr = pHwAccess->partition[0].start;
2261
2262 #ifdef HW_ACCESS_SDIO
2263
2264 os_memoryZero (pHwAccess->hOs, &sdioConfParam, sizeof(SDIO_TNETWConfigParams));
2265 sdioConfParam.num_of_parts = 2;
2266 sdioConfParam.map_reg[0].reg_size = pHwAccess->partition[0].size;
2267 sdioConfParam.map_reg[0].scr_offset = pHwAccess->partition[0].start;
2268 sdioConfParam.map_reg[1].reg_size = pHwAccess->partition[1].size;
2269 sdioConfParam.map_reg[1].scr_offset = pHwAccess->partition[1].start;
2270
2271 status = SDIO_TNETWInit(&sdioConfParam);
2272 status = (status == SDIO_SUCCESS) ? SDIO_TNETWConfig(pHwAccess->hDriver, &cfg) : status;
2273 status = (status == SDIO_SUCCESS) ? TNETWIF_COMPLETE : TNETWIF_ERROR;
2274
2275 #elif defined(HW_ACCESS_WSPI)
2276
2277 /* May use only one write because the addresses in the firmware are sequential */
2278 status = WSPI_WriteAsync (pHwAccess->hDriver,
2279 HW_ACCESS_PART0_SIZE_ADDR,
2280 PADWRITE (pHwAccess->partition),
2281 sizeof(partition_t) * 2,
2282 (WSPI_CB_T*)&pHwAccess->CB,
2283 TRUE,
2284 TRUE);
2285
2286 WSPI2TNETWIF (pHwAccess, status, HW_ACCESS_PART0_SIZE_ADDR);
2287
2288 #endif
2289
2290 #endif
2291
2292 return status;
2293 }
2294
2295
2296 #if !defined(HW_ACCESS_SDIO) && !defined(HW_ACCESS_WSPI)
2297 /****************************************************************************
2298 * whal_hwAccess_DirectCopy_new()
2299 ****************************************************************************
2300 * DESCRIPTION: Direct Copy sequence of bytes to/from the hardware
2301 *
2302 * INPUTS:
2303 * pHwAccess The object
2304 * Dest Destination address
2305 * Src Source address
2306 * Len The length of the data to copy
2307 *
2308 * OUTPUT: None
2309 *
2310 * RETURNS: OK or NOK
2311 ****************************************************************************/
whal_hwAccess_DirectCopy_new(HwAccess_T_new * pHwAccess,UINT8 * Dest,UINT8 * Src,UINT32 Len)2312 static void whal_hwAccess_DirectCopy_new(HwAccess_T_new *pHwAccess, UINT8* Dest, UINT8* Src, UINT32 Len)
2313 {
2314
2315 #ifdef NOT_SUPPORT_08_BIT_ACCESS_COMMAND
2316
2317 /* first see if dest addr is 4 bytes
2318 align if not we are using local copy and not
2319 os_memoryCopy
2320 */
2321 if(((UINT32)Dest & 0x00000001))
2322 {
2323 /* TBD - Currently unaligned destination address is not handled.
2324 it means that CKIP will not work currently.
2325 */
2326
2327 }else
2328 if(((UINT32)Dest & 0x00000002))
2329 {
2330 register volatile unsigned short *shortDest = (volatile unsigned short *)Dest;
2331 register volatile unsigned short *shortSrc = (unsigned short *)Src;
2332 register int Size = Len >> 1;
2333
2334 unsigned short TempWord;
2335 while (Size--)
2336 *shortDest++ = *shortSrc++;
2337
2338 if (Len&1)
2339 {
2340 TempWord = ENDIAN_HANDLE_WORD((*shortSrc & 0x00ff) | (*shortDest & 0xff00));
2341 *shortDest = TempWord;
2342 }
2343 }else
2344 {
2345 /* The address line A0 is not connected
2346 For arm/linux sake not 2, but 4-alignment is enforced.
2347 (Linux memcpy uses longs copy logic)
2348 */
2349 int Len1 = Len & 0xfffffffc;
2350
2351 os_memoryCopy(pHwAccess->hOs, (void*)Dest, (void*)Src, Len1);
2352
2353 if (Len1 != Len)
2354 {
2355 int ShortSize=Len1 >> 1;
2356 volatile unsigned short *shortDest = ((unsigned short *)Dest) + ShortSize;
2357 volatile unsigned short *shortSrc = ((unsigned short *)Src) + ShortSize;
2358 if (Len - Len1 >= 2)
2359 *shortDest++ = *shortSrc++;
2360 if (Len & 1)
2361 *shortDest = ENDIAN_HANDLE_WORD((*shortSrc & 0x00ff) | (*shortDest & 0xff00));
2362 }
2363 }
2364
2365 #else
2366 os_memoryCopy(pHwAccess->hOs, (void*)Dest, (void*)Src, Len);
2367 #endif
2368 }
2369 #endif
2370
2371
2372 #ifdef HW_ACCESS_SDIO
2373
2374 /* callback notify read/write transaction function */
sdio_transaction_notify_read(struct SDIO_Request * req,int status)2375 static void sdio_transaction_notify_read(struct SDIO_Request *req, int status)
2376 {
2377 }
2378
sdio_transaction_notify_write(struct SDIO_Request * req,int status)2379 static void sdio_transaction_notify_write(struct SDIO_Request *req, int status)
2380 {
2381 }
2382
2383 /* callback notify error read/write transaction function */
sdio_transaction_error(struct SDIO_Request * req,int stat)2384 static void sdio_transaction_error(struct SDIO_Request *req, int stat)
2385 {
2386 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)req->owner;
2387
2388 WLAN_REPORT_ERROR (pHwAccess->hReport, HAL_CTRL_MODULE_LOG, ("sdio_transaction_error\n"));
2389
2390 pHwAccess->uBusError = 1;
2391 }
2392
2393
2394 #if defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
2395
sdio_async_transaction_notify(struct SDIO_Request * req,int status)2396 static void sdio_async_transaction_notify(struct SDIO_Request *req, int status)
2397 {
2398 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)req->owner;
2399
2400 /* call the CB */
2401 pHwAccess->CB.CBFunc(pHwAccess->CB.CBArg,status);
2402
2403 WLAN_REPORT_INFORMATION(pHwAccess->hReport,
2404 HAL_HW_CTRL_MODULE_LOG,
2405 ("sdio_async_transaction_notify - request=%p, buf=%p, sdio_addr=0x%08lx, len=%u\n",
2406 req, req->buffer, req->peripheral_addr, req->block_len));
2407
2408 }
2409
2410 /* callback notify error read/write transaction function */
sdio_async_transaction_error(struct SDIO_Request * req,int status)2411 static void sdio_async_transaction_error(struct SDIO_Request *req, int status)
2412 {
2413 HwAccess_T_new* pHwAccess = (HwAccess_T_new*)req->owner;
2414
2415 WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
2416 ("sdio_async_transaction_error: request=%p, buf=%p, sdio_addr=0x%08lx, len=%u\n",
2417 req, req->buffer, req->peripheral_addr, req->block_len));
2418 }
2419
2420 #endif /*HW_ACCESS_SDIO_ASYNC_SUPPORT*/
2421
2422 #endif /*HW_ACCESS_SDIO*/
2423
whal_hwAccess_RegisterForErrorCB(TI_HANDLE hHwAccess,void * CbFunc,TI_HANDLE CbObj)2424 TI_STATUS whal_hwAccess_RegisterForErrorCB(TI_HANDLE hHwAccess,
2425 void* CbFunc,
2426 TI_HANDLE CbObj)
2427 {
2428 HwAccess_T_new *pHwAccess = (HwAccess_T_new *)hHwAccess;
2429 pHwAccess->hwAccesserror_Cb = (HwAccessErrorHandle)CbFunc;
2430 pHwAccess->hBackReference = CbObj;
2431 return OK;
2432 }
2433
2434
2435 /***********************************************************/
2436
2437
2438 #ifdef USE_SYNC_API
2439 /****************************************************************************
2440 * whal_hwAccess_RegSetBitVal()
2441 ****************************************************************************
2442 * DESCRIPTION: wlan hardware registers bits access
2443 *
2444 * INPUTS:
2445 *
2446 * OUTPUT: None
2447 *
2448 * RETURNS: OK or NOK
2449 ****************************************************************************/
whal_hwAccess_RegSetBitVal(TI_HANDLE hHwAccess,UINT32 RegAddr,UINT32 BitVal)2450 void whal_hwAccess_RegSetBitVal(TI_HANDLE hHwAccess, UINT32 RegAddr, UINT32 BitVal)
2451 {
2452 UINT32 rVal;
2453
2454 whal_hwAccess_ReadReg(hHwAccess,RegAddr,&rVal);
2455 rVal |= BitVal;
2456 whal_hwAccess_WriteReg(hHwAccess, RegAddr, rVal);
2457 }
2458
2459 /****************************************************************************
2460 * whal_hwAccess_RegResetBitVal()
2461 ****************************************************************************
2462 * DESCRIPTION: wlan hardware registers bits access
2463 *
2464 * INPUTS:
2465 *
2466 * OUTPUT: None
2467 *
2468 * RETURNS: OK or NOK
2469 ****************************************************************************/
whal_hwAccess_RegResetBitVal(TI_HANDLE hHwAccess,UINT32 RegAddr,UINT32 BitVal)2470 void whal_hwAccess_RegResetBitVal(TI_HANDLE hHwAccess, UINT32 RegAddr, UINT32 BitVal)
2471 {
2472 UINT32 rVal;
2473
2474 whal_hwAccess_ReadReg(hHwAccess,RegAddr,&rVal);
2475 rVal &= ~BitVal;
2476 whal_hwAccess_WriteReg(hHwAccess, RegAddr, rVal);
2477 }
2478
2479 /****************************************************************************
2480 * whal_hwAccess_RegIsBitSet()
2481 ****************************************************************************
2482 * DESCRIPTION: wlan hardware registers bits access
2483 *
2484 * INPUTS:
2485 *
2486 * OUTPUT: None
2487 *
2488 * RETURNS: OK or NOK
2489 ****************************************************************************/
whal_hwAccess_RegIsBitSet(TI_HANDLE hHwAccess,UINT32 RegAddr,UINT32 BitVal)2490 int whal_hwAccess_RegIsBitSet(TI_HANDLE hHwAccess, UINT32 RegAddr, UINT32 BitVal)
2491 {
2492 UINT32 RegVal;
2493
2494 whal_hwAccess_ReadReg(hHwAccess,RegAddr,&RegVal);
2495 if (RegVal & BitVal)
2496 return 1;
2497
2498 return 0;
2499 }
2500
2501
2502 /****************************************************************************
2503 * whal_hwAccess_(Get/Set/SetBits/ResetBits)U08()
2504 ****************************************************************************
2505 * DESCRIPTION: wlan hardware memory access to bytes
2506 *
2507 * INPUTS:
2508 *
2509 * OUTPUT: None
2510 *
2511 * RETURNS: OK or NOK
2512 ****************************************************************************/
whal_hwAccess_GetU08(TI_HANDLE hHwAccess,UINT32 Addr)2513 UINT8 whal_hwAccess_GetU08(TI_HANDLE hHwAccess, UINT32 Addr)
2514 {
2515
2516
2517 #ifdef HW_ACCESS_SDIO
2518 UINT32 SrcOffset ;
2519 UINT16 DataShort;
2520
2521 SrcOffset = (Addr & 0xfffffffe);
2522 whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)SrcOffset),(UINT8*)((char *)&DataShort),sizeof(UINT16));
2523 return (EXTRACT_BYTE_FROM_WORD(DataShort, Addr));
2524
2525 #else /* HW_ACCESS_SDIO */
2526
2527 UINT32 data = 0;
2528
2529 whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2530 return (data & 0x000000FF);
2531
2532 #endif /* HW_ACCESS_SDIO */
2533
2534 }
2535
whal_hwAccess_SetU08(TI_HANDLE hHwAccess,UINT32 Addr,UINT8 Val)2536 void whal_hwAccess_SetU08(TI_HANDLE hHwAccess, UINT32 Addr, UINT8 Val)
2537 {
2538
2539
2540 #ifdef HW_ACCESS_SDIO
2541
2542 UINT32 sdioAddr;
2543 UINT16 DataShort;
2544
2545 sdioAddr = (Addr & 0xfffffffe);
2546 whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT16));
2547 EXTRACT_BYTE_FROM_WORD(DataShort, Addr) = Val;
2548 whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT16));
2549
2550 #else /* HW_ACCESS_SDIO */
2551
2552 UINT32 data = 0;
2553
2554 whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2555 data &= 0xFFFFFF00;
2556 data |= Val;
2557 whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2558
2559 #endif /* HW_ACCESS_SDIO */
2560
2561 }
2562
2563
whal_hwAccess_ResetU08_Bits(TI_HANDLE hHwAccess,UINT32 Addr,UINT8 BitsVal)2564 void whal_hwAccess_ResetU08_Bits(TI_HANDLE hHwAccess, UINT32 Addr, UINT8 BitsVal)
2565 {
2566
2567
2568 #ifdef HW_ACCESS_SDIO
2569
2570 UINT32 sdioAddr;
2571 UINT16 DataShort;
2572
2573 sdioAddr = (Addr & 0xfffffffe);
2574 whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT16));
2575 EXTRACT_BYTE_FROM_WORD(DataShort, Addr) &= ~BitsVal;
2576 whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT16));
2577
2578 #else /* HW_ACCESS_SDIO */
2579
2580 UINT32 data = 0;
2581
2582 whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2583 data &= ~BitsVal;
2584 whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2585
2586 #endif /* HW_ACCESS_SDIO */
2587
2588 }
2589
2590 /****************************************************************************
2591 * whal_hwAccess_(Get/Set/SetBits/ResetBits)U16()
2592 ****************************************************************************
2593 * DESCRIPTION: wlan hardware memory access to shorts
2594 *
2595 * INPUTS:
2596 *
2597 * OUTPUT: None
2598 *
2599 * RETURNS: OK or NOK
2600 ****************************************************************************/
whal_hwAccess_GetU16(TI_HANDLE hHwAccess,UINT32 Addr)2601 UINT16 whal_hwAccess_GetU16(TI_HANDLE hHwAccess, UINT32 Addr)
2602 {
2603
2604
2605 #ifdef HW_ACCESS_SDIO
2606
2607 UINT32 sdioAddr;
2608 UINT16 DataShort;
2609
2610 sdioAddr = Addr;
2611 whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT16));
2612
2613 return (ENDIAN_HANDLE_WORD(DataShort));
2614
2615 #else /* HW_ACCESS_SDIO */
2616
2617 UINT32 data = 0;
2618
2619 whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2620 return (data & 0x0000FFFF);
2621
2622 #endif /* HW_ACCESS_SDIO */
2623
2624 }
2625
whal_hwAccess_SetU16(TI_HANDLE hHwAccess,UINT32 Addr,UINT16 Val)2626 void whal_hwAccess_SetU16(TI_HANDLE hHwAccess, UINT32 Addr, UINT16 Val)
2627 {
2628
2629
2630 #ifdef HW_ACCESS_SDIO
2631
2632 UINT32 sdioAddr;
2633 UINT16 sdioVal;
2634
2635 sdioAddr = (Addr & 0xfffffffe);
2636 sdioVal = ENDIAN_HANDLE_WORD(Val);
2637 whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&sdioVal),sizeof(UINT16));
2638
2639 #else /* HW_ACCESS_SDIO */
2640
2641 UINT32 data = 0;
2642 UINT32 sdioAddr;
2643
2644 sdioAddr = (Addr & 0xfffffffc);
2645 whal_hwAccess_ReadMem(hHwAccess,(UINT32)sdioAddr,(UINT8*)&data,sizeof(data));
2646
2647 if((Addr&0x3) == 2)
2648 {
2649 data &= 0x0000FFFF;
2650 data |= ((UINT32)Val)<<16;
2651 }
2652 else
2653 {
2654 data &= 0xFFFF0000;
2655 data |= Val;
2656 }
2657 whal_hwAccess_WriteMem(hHwAccess,(UINT32)sdioAddr,(UINT8*)&data,sizeof(data));
2658
2659 #endif /* HW_ACCESS_SDIO */
2660
2661 }
2662
whal_hwAccess_SetU16_Bits(TI_HANDLE hHwAccess,UINT32 Addr,UINT16 Val)2663 void whal_hwAccess_SetU16_Bits(TI_HANDLE hHwAccess, UINT32 Addr, UINT16 Val)
2664 {
2665
2666
2667 #ifdef HW_ACCESS_SDIO
2668
2669 UINT32 sdioAddr;
2670 UINT16 sdioVal;
2671
2672 sdioAddr = Addr;
2673 whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&sdioVal),sizeof(UINT16));
2674 sdioVal |= ENDIAN_HANDLE_WORD(Val);
2675 whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&sdioVal),sizeof(UINT16));
2676
2677 #else /* HW_ACCESS_SDIO */
2678
2679 UINT32 data = 0;
2680
2681 whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2682 data |= Val;
2683 whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2684
2685 #endif /* HW_ACCESS_SDIO */
2686
2687 }
2688
whal_hwAccess_ResetU16_Bits(TI_HANDLE hHwAccess,UINT32 Addr,UINT16 Val)2689 void whal_hwAccess_ResetU16_Bits(TI_HANDLE hHwAccess, UINT32 Addr, UINT16 Val)
2690 {
2691
2692
2693 #ifdef HW_ACCESS_SDIO
2694
2695 UINT32 sdioAddr;
2696 UINT16 sdioVal;
2697
2698 sdioAddr = Addr;
2699 whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&sdioVal),sizeof(UINT16));
2700 sdioVal &= ~ENDIAN_HANDLE_WORD(Val);
2701 whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&sdioVal),sizeof(UINT16));
2702
2703 #else /* HW_ACCESS_SDIO */
2704
2705 UINT32 data = 0;
2706
2707 whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2708 data &= ~Val;
2709 whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2710
2711 #endif /* HW_ACCESS_SDIO */
2712
2713 }
2714
2715 /****************************************************************************
2716 * whal_hwAccess_(Get/Set/SetBits/ResetBits)U32()
2717 ****************************************************************************
2718 * DESCRIPTION: wlan hardware memory access to longs
2719 *
2720 * INPUTS:
2721 *
2722 * OUTPUT: None
2723 *
2724 * RETURNS: OK or NOK
2725 ****************************************************************************/
whal_hwAccess_GetU32(TI_HANDLE hHwAccess,UINT32 Addr)2726 UINT32 whal_hwAccess_GetU32(TI_HANDLE hHwAccess, UINT32 Addr)
2727 {
2728
2729
2730 #ifdef HW_ACCESS_SDIO
2731
2732 UINT32 DataLong;
2733 UINT32 sdioAddr;
2734
2735 sdioAddr = Addr;
2736 whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataLong),sizeof(UINT32));
2737 return (ENDIAN_HANDLE_LONG(DataLong));
2738
2739 #else /* HW_ACCESS_SDIO */
2740
2741 UINT32 data = 0;
2742
2743 whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2744 return data;
2745
2746 #endif /* HW_ACCESS_SDIO */
2747
2748 }
2749
2750
whal_hwAccess_SetU32(TI_HANDLE hHwAccess,UINT32 Addr,UINT32 Val)2751 void whal_hwAccess_SetU32(TI_HANDLE hHwAccess, UINT32 Addr, UINT32 Val)
2752 {
2753
2754
2755 #ifdef HW_ACCESS_SDIO
2756
2757 UINT32 sdioAddr;
2758 UINT32 sdioVal;
2759
2760 sdioAddr = Addr;
2761 sdioVal = ENDIAN_HANDLE_WORD(Val);
2762 whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&sdioVal),sizeof(UINT32));
2763
2764 #else /* HW_ACCESS_SDIO */
2765
2766 whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&Val,sizeof(Val));
2767
2768 #endif /* HW_ACCESS_SDIO */
2769
2770 }
2771
whal_hwAccess_SetU32_Bits(TI_HANDLE hHwAccess,UINT32 Addr,UINT32 Val)2772 void whal_hwAccess_SetU32_Bits(TI_HANDLE hHwAccess, UINT32 Addr, UINT32 Val)
2773 {
2774
2775
2776 #ifdef HW_ACCESS_SDIO
2777
2778 UINT32 sdioAddr;
2779 UINT32 DataShort;
2780
2781 sdioAddr = (Addr & 0xfffffffe);
2782 whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT32));
2783 DataShort |= ENDIAN_HANDLE_LONG(Val);
2784 whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT32));
2785
2786 #else /* HW_ACCESS_SDIO */
2787
2788 UINT32 data = 0;
2789
2790 whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2791 data |= Val;
2792 whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2793
2794 #endif /* HW_ACCESS_SDIO */
2795
2796 }
2797
whal_hwAccess_ResetU32_Bits(TI_HANDLE hHwAccess,UINT32 Addr,UINT32 Val)2798 void whal_hwAccess_ResetU32_Bits(TI_HANDLE hHwAccess, UINT32 Addr, UINT32 Val)
2799 {
2800
2801
2802 #ifdef HW_ACCESS_SDIO
2803
2804 UINT32 sdioAddr;
2805 UINT32 DataShort;
2806
2807 sdioAddr = (Addr & 0xfffffffe);
2808 whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT32));
2809 DataShort &= ~ENDIAN_HANDLE_LONG(Val);
2810 whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT32));
2811
2812 #else /* HW_ACCESS_SDIO */
2813
2814 UINT32 data = 0;
2815
2816 whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2817 data &= ~Val;
2818 whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
2819
2820 #endif /* HW_ACCESS_SDIO */
2821
2822 }
2823
2824 #endif /* USE_SYNC_API */
2825
2826
2827 /****************************************************************************
2828 * whal_hwAccess_Print()
2829 ****************************************************************************
2830 * DESCRIPTION: Print interrupts information
2831 *
2832 * INPUTS: None
2833 *
2834 * OUTPUT: None
2835 *
2836 * RETURNS:
2837 ****************************************************************************/
whal_hwAccess_Print(TI_HANDLE hHwAccess)2838 void whal_hwAccess_Print(TI_HANDLE hHwAccess)
2839 {
2840 /* will be in use only if a print function will be neaded.
2841 HwAccess_T_new *pHwAccess = (HwAccess_T_new*) hHwAccess;
2842 */
2843 WLAN_OS_REPORT(("whal_hwAccess_Print ----------------------------\n"));
2844 WLAN_OS_REPORT((" NOTHING RIGHTNOW\n"));
2845 }
2846
2847 /************************************************************************
2848 * Internal functions
2849 ************************************************************************/
2850
2851 #ifdef HW_ACCESS_SDIO
whal_hwAccess_RecreateInterface(TI_HANDLE hHwAccess)2852 TI_STATUS whal_hwAccess_RecreateInterface(TI_HANDLE hHwAccess)
2853 {
2854 SDIO_ConfigParams configParams;
2855 HwAccess_T_new *pHwAccess = (HwAccess_T_new*)hHwAccess;
2856 SDIO_Status status;
2857
2858 os_memoryZero( pHwAccess->hOs, &configParams, sizeof(SDIO_ConfigParams));
2859 configParams.fnotify_read = sdio_transaction_notify_read;
2860 configParams.fnotify_write = sdio_transaction_notify_write;
2861 configParams.ferror = sdio_transaction_error;
2862 configParams.fconfig_peripheral = SDIO_TNETWConfig;
2863 configParams.fconvert = NULL;
2864 configParams.owner = pHwAccess;
2865
2866 status = SDIO_Init(&configParams, &pHwAccess->hDriver);
2867
2868 return (status == SDIO_SUCCESS) ? OK : NOK;
2869 }
2870 #elif defined(HW_ACCESS_WSPI)
whal_hwAccess_RecreateInterface(TI_HANDLE hHwAccess)2871 TI_STATUS whal_hwAccess_RecreateInterface(TI_HANDLE hHwAccess)
2872 {
2873 HwAccess_T_new *pHwAccess = (HwAccess_T_new*)hHwAccess;
2874 int status;
2875
2876 /* re-configure the WSPi interface, using NULL to keep old parameters */
2877 status = WSPI_Configure (pHwAccess->hDriver , NULL, NULL, NULL);
2878
2879 #ifndef _WINDOWS
2880 WSPI2TNETWIF (pHwAccess, status, 0x0);
2881 return (TI_STATUS)status;
2882 #else
2883 #endif
2884 }
2885 #else /* ifdef HW_ACCESS_SDIO */
whal_hwAccess_RecreateInterface(TI_HANDLE hHwAccess)2886 TI_STATUS whal_hwAccess_RecreateInterface(TI_HANDLE hHwAccess)
2887 {
2888 TI_STATUS status = NOK;
2889
2890 /*#error whal_hwAccess_RecreateInterface function is not implemented for HW interface other than SDIO.*/
2891
2892 return (status);
2893 }
2894 #endif /* ifdef HW_ACCESS_SDIO */
2895
2896
2897