1 /* 2 * SiliconBackplane Chipcommon core hardware definitions. 3 * 4 * The chipcommon core provides chip identification, SB control, 5 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer, 6 * gpio interface, extbus, and support for serial and parallel flashes. 7 * 8 * $Id: sbchipc.h,v 13.103.2.5.4.5.2.9 2009/07/03 14:23:21 Exp $ 9 * 10 * Copyright (C) 1999-2009, Broadcom Corporation 11 * 12 * Unless you and Broadcom execute a separate written software license 13 * agreement governing use of this software, this software is licensed to you 14 * under the terms of the GNU General Public License version 2 (the "GPL"), 15 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 16 * following added to such license: 17 * 18 * As a special exception, the copyright holders of this software give you 19 * permission to link this software with independent modules, and to copy and 20 * distribute the resulting executable under terms of your choice, provided that 21 * you also meet, for each linked independent module, the terms and conditions of 22 * the license of that module. An independent module is a module which is not 23 * derived from this software. The special exception does not apply to any 24 * modifications of the software. 25 * 26 * Notwithstanding the above, under no circumstances may you combine this 27 * software in any way with any other Broadcom software provided under a license 28 * other than the GPL, without Broadcom's express prior written consent. 29 */ 30 31 32 #ifndef _SBCHIPC_H 33 #define _SBCHIPC_H 34 35 #ifndef _LANGUAGE_ASSEMBLY 36 37 38 #ifndef PAD 39 #define _PADLINE(line) pad ## line 40 #define _XSTR(line) _PADLINE(line) 41 #define PAD _XSTR(__LINE__) 42 #endif 43 44 typedef volatile struct { 45 uint32 chipid; 46 uint32 capabilities; 47 uint32 corecontrol; 48 uint32 bist; 49 50 51 uint32 otpstatus; 52 uint32 otpcontrol; 53 uint32 otpprog; 54 uint32 PAD; 55 56 57 uint32 intstatus; 58 uint32 intmask; 59 uint32 chipcontrol; 60 uint32 chipstatus; 61 62 63 uint32 jtagcmd; 64 uint32 jtagir; 65 uint32 jtagdr; 66 uint32 jtagctrl; 67 68 69 uint32 flashcontrol; 70 uint32 flashaddress; 71 uint32 flashdata; 72 uint32 PAD[1]; 73 74 75 uint32 broadcastaddress; 76 uint32 broadcastdata; 77 78 79 uint32 gpiopullup; 80 uint32 gpiopulldown; 81 uint32 gpioin; 82 uint32 gpioout; 83 uint32 gpioouten; 84 uint32 gpiocontrol; 85 uint32 gpiointpolarity; 86 uint32 gpiointmask; 87 88 89 uint32 gpioevent; 90 uint32 gpioeventintmask; 91 92 93 uint32 watchdog; 94 95 96 uint32 gpioeventintpolarity; 97 98 99 uint32 gpiotimerval; 100 uint32 gpiotimeroutmask; 101 102 103 uint32 clockcontrol_n; 104 uint32 clockcontrol_sb; 105 uint32 clockcontrol_pci; 106 uint32 clockcontrol_m2; 107 uint32 clockcontrol_m3; 108 uint32 clkdiv; 109 uint32 PAD[2]; 110 111 112 uint32 pll_on_delay; 113 uint32 fref_sel_delay; 114 uint32 slow_clk_ctl; 115 uint32 PAD[1]; 116 117 118 uint32 system_clk_ctl; 119 uint32 clkstatestretch; 120 uint32 PAD[13]; 121 122 123 uint32 eromptr; 124 125 126 uint32 pcmcia_config; 127 uint32 pcmcia_memwait; 128 uint32 pcmcia_attrwait; 129 uint32 pcmcia_iowait; 130 uint32 ide_config; 131 uint32 ide_memwait; 132 uint32 ide_attrwait; 133 uint32 ide_iowait; 134 uint32 prog_config; 135 uint32 prog_waitcount; 136 uint32 flash_config; 137 uint32 flash_waitcount; 138 uint32 PAD[4]; 139 uint32 PAD[40]; 140 141 142 143 uint32 clk_ctl_st; 144 uint32 hw_war; 145 uint32 PAD[70]; 146 147 148 uint8 uart0data; 149 uint8 uart0imr; 150 uint8 uart0fcr; 151 uint8 uart0lcr; 152 uint8 uart0mcr; 153 uint8 uart0lsr; 154 uint8 uart0msr; 155 uint8 uart0scratch; 156 uint8 PAD[248]; 157 158 uint8 uart1data; 159 uint8 uart1imr; 160 uint8 uart1fcr; 161 uint8 uart1lcr; 162 uint8 uart1mcr; 163 uint8 uart1lsr; 164 uint8 uart1msr; 165 uint8 uart1scratch; 166 uint32 PAD[126]; 167 168 169 uint32 pmucontrol; 170 uint32 pmucapabilities; 171 uint32 pmustatus; 172 uint32 res_state; 173 uint32 res_pending; 174 uint32 pmutimer; 175 uint32 min_res_mask; 176 uint32 max_res_mask; 177 uint32 res_table_sel; 178 uint32 res_dep_mask; 179 uint32 res_updn_timer; 180 uint32 res_timer; 181 uint32 clkstretch; 182 uint32 pmuwatchdog; 183 uint32 gpiosel; 184 uint32 gpioenable; 185 uint32 res_req_timer_sel; 186 uint32 res_req_timer; 187 uint32 res_req_mask; 188 uint32 PAD; 189 uint32 chipcontrol_addr; 190 uint32 chipcontrol_data; 191 uint32 regcontrol_addr; 192 uint32 regcontrol_data; 193 uint32 pllcontrol_addr; 194 uint32 pllcontrol_data; 195 uint32 PAD[102]; 196 uint16 otp[768]; 197 } chipcregs_t; 198 199 #endif 200 201 #define CC_CHIPID 0 202 #define CC_CAPABILITIES 4 203 #define CC_OTPST 0x10 204 #define CC_CHIPST 0x2c 205 #define CC_JTAGCMD 0x30 206 #define CC_JTAGIR 0x34 207 #define CC_JTAGDR 0x38 208 #define CC_JTAGCTRL 0x3c 209 #define CC_WATCHDOG 0x80 210 #define CC_CLKC_N 0x90 211 #define CC_CLKC_M0 0x94 212 #define CC_CLKC_M1 0x98 213 #define CC_CLKC_M2 0x9c 214 #define CC_CLKC_M3 0xa0 215 #define CC_CLKDIV 0xa4 216 #define CC_SYS_CLK_CTL 0xc0 217 #define CC_CLK_CTL_ST SI_CLK_CTL_ST 218 #define CC_EROMPTR 0xfc 219 #define PMU_CTL 0x600 220 #define PMU_CAP 0x604 221 #define PMU_ST 0x608 222 #define PMU_RES_STATE 0x60c 223 #define PMU_TIMER 0x614 224 #define PMU_MIN_RES_MASK 0x618 225 #define PMU_MAX_RES_MASK 0x61c 226 #define PMU_REG_CONTROL_ADDR 0x658 227 #define PMU_REG_CONTROL_DATA 0x65C 228 #define PMU_PLL_CONTROL_ADDR 0x660 229 #define PMU_PLL_CONTROL_DATA 0x664 230 #define CC_OTP 0x800 231 232 233 #define CID_ID_MASK 0x0000ffff 234 #define CID_REV_MASK 0x000f0000 235 #define CID_REV_SHIFT 16 236 #define CID_PKG_MASK 0x00f00000 237 #define CID_PKG_SHIFT 20 238 #define CID_CC_MASK 0x0f000000 239 #define CID_CC_SHIFT 24 240 #define CID_TYPE_MASK 0xf0000000 241 #define CID_TYPE_SHIFT 28 242 243 244 #define CC_CAP_UARTS_MASK 0x00000003 245 #define CC_CAP_MIPSEB 0x00000004 246 #define CC_CAP_UCLKSEL 0x00000018 247 #define CC_CAP_UINTCLK 0x00000008 248 #define CC_CAP_UARTGPIO 0x00000020 249 #define CC_CAP_EXTBUS_MASK 0x000000c0 250 #define CC_CAP_EXTBUS_NONE 0x00000000 251 #define CC_CAP_EXTBUS_FULL 0x00000040 252 #define CC_CAP_EXTBUS_PROG 0x00000080 253 #define CC_CAP_FLASH_MASK 0x00000700 254 #define CC_CAP_PLL_MASK 0x00038000 255 #define CC_CAP_PWR_CTL 0x00040000 256 #define CC_CAP_OTPSIZE 0x00380000 257 #define CC_CAP_OTPSIZE_SHIFT 19 258 #define CC_CAP_OTPSIZE_BASE 5 259 #define CC_CAP_JTAGP 0x00400000 260 #define CC_CAP_ROM 0x00800000 261 #define CC_CAP_BKPLN64 0x08000000 262 #define CC_CAP_PMU 0x10000000 263 #define CC_CAP_ECI 0x20000000 264 265 266 #define PLL_NONE 0x00000000 267 #define PLL_TYPE1 0x00010000 268 #define PLL_TYPE2 0x00020000 269 #define PLL_TYPE3 0x00030000 270 #define PLL_TYPE4 0x00008000 271 #define PLL_TYPE5 0x00018000 272 #define PLL_TYPE6 0x00028000 273 #define PLL_TYPE7 0x00038000 274 275 276 #define ILP_CLOCK 32000 277 278 279 #define ALP_CLOCK 20000000 280 281 282 #define HT_CLOCK 80000000 283 284 285 #define CC_UARTCLKO 0x00000001 286 #define CC_SE 0x00000002 287 #define CC_UARTCLKEN 0x00000008 288 289 290 #define CHIPCTRL_4321A0_DEFAULT 0x3a4 291 #define CHIPCTRL_4321A1_DEFAULT 0x0a4 292 #define CHIPCTRL_4321_PLL_DOWN 0x800000 293 294 295 #define OTPS_OL_MASK 0x000000ff 296 #define OTPS_OL_MFG 0x00000001 297 #define OTPS_OL_OR1 0x00000002 298 #define OTPS_OL_OR2 0x00000004 299 #define OTPS_OL_GU 0x00000008 300 #define OTPS_GUP_MASK 0x00000f00 301 #define OTPS_GUP_SHIFT 8 302 #define OTPS_GUP_HW 0x00000100 303 #define OTPS_GUP_SW 0x00000200 304 #define OTPS_GUP_CI 0x00000400 305 #define OTPS_GUP_FUSE 0x00000800 306 #define OTPS_READY 0x00001000 307 #define OTPS_RV(x) (1 << (16 + (x))) 308 #define OTPS_RV_MASK 0x0fff0000 309 310 311 #define OTPC_PROGSEL 0x00000001 312 #define OTPC_PCOUNT_MASK 0x0000000e 313 #define OTPC_PCOUNT_SHIFT 1 314 #define OTPC_VSEL_MASK 0x000000f0 315 #define OTPC_VSEL_SHIFT 4 316 #define OTPC_TMM_MASK 0x00000700 317 #define OTPC_TMM_SHIFT 8 318 #define OTPC_ODM 0x00000800 319 #define OTPC_PROGEN 0x80000000 320 321 322 #define OTPP_COL_MASK 0x000000ff 323 #define OTPP_COL_SHIFT 0 324 #define OTPP_ROW_MASK 0x0000ff00 325 #define OTPP_ROW_SHIFT 8 326 #define OTPP_OC_MASK 0x0f000000 327 #define OTPP_OC_SHIFT 24 328 #define OTPP_READERR 0x10000000 329 #define OTPP_VALUE_MASK 0x20000000 330 #define OTPP_VALUE_SHIFT 29 331 #define OTPP_START_BUSY 0x80000000 332 333 334 #define OTPPOC_READ 0 335 #define OTPPOC_BIT_PROG 1 336 #define OTPPOC_VERIFY 3 337 #define OTPPOC_INIT 4 338 #define OTPPOC_SET 5 339 #define OTPPOC_RESET 6 340 #define OTPPOC_OCST 7 341 #define OTPPOC_ROW_LOCK 8 342 #define OTPPOC_PRESCN_TEST 9 343 344 345 #define JCMD_START 0x80000000 346 #define JCMD_BUSY 0x80000000 347 #define JCMD_STATE_MASK 0x60000000 348 #define JCMD_STATE_TLR 0x00000000 349 #define JCMD_STATE_PIR 0x20000000 350 #define JCMD_STATE_PDR 0x40000000 351 #define JCMD_STATE_RTI 0x60000000 352 #define JCMD0_ACC_MASK 0x0000f000 353 #define JCMD0_ACC_IRDR 0x00000000 354 #define JCMD0_ACC_DR 0x00001000 355 #define JCMD0_ACC_IR 0x00002000 356 #define JCMD0_ACC_RESET 0x00003000 357 #define JCMD0_ACC_IRPDR 0x00004000 358 #define JCMD0_ACC_PDR 0x00005000 359 #define JCMD0_IRW_MASK 0x00000f00 360 #define JCMD_ACC_MASK 0x000f0000 361 #define JCMD_ACC_IRDR 0x00000000 362 #define JCMD_ACC_DR 0x00010000 363 #define JCMD_ACC_IR 0x00020000 364 #define JCMD_ACC_RESET 0x00030000 365 #define JCMD_ACC_IRPDR 0x00040000 366 #define JCMD_ACC_PDR 0x00050000 367 #define JCMD_ACC_PIR 0x00060000 368 #define JCMD_ACC_IRDR_I 0x00070000 369 #define JCMD_ACC_DR_I 0x00080000 370 #define JCMD_IRW_MASK 0x00001f00 371 #define JCMD_IRW_SHIFT 8 372 #define JCMD_DRW_MASK 0x0000003f 373 374 375 #define JCTRL_FORCE_CLK 4 376 #define JCTRL_EXT_EN 2 377 #define JCTRL_EN 1 378 379 380 #define CLKD_SFLASH 0x0f000000 381 #define CLKD_SFLASH_SHIFT 24 382 #define CLKD_OTP 0x000f0000 383 #define CLKD_OTP_SHIFT 16 384 #define CLKD_JTAG 0x00000f00 385 #define CLKD_JTAG_SHIFT 8 386 #define CLKD_UART 0x000000ff 387 388 389 #define CI_GPIO 0x00000001 390 #define CI_EI 0x00000002 391 #define CI_TEMP 0x00000004 392 #define CI_SIRQ 0x00000008 393 #define CI_ECI 0x00000010 394 #define CI_PMU 0x00000020 395 #define CI_UART 0x00000040 396 #define CI_WDRESET 0x80000000 397 398 399 #define SCC_SS_MASK 0x00000007 400 #define SCC_SS_LPO 0x00000000 401 #define SCC_SS_XTAL 0x00000001 402 #define SCC_SS_PCI 0x00000002 403 #define SCC_LF 0x00000200 404 #define SCC_LP 0x00000400 405 #define SCC_FS 0x00000800 406 #define SCC_IP 0x00001000 407 #define SCC_XC 0x00002000 408 #define SCC_XP 0x00004000 409 #define SCC_CD_MASK 0xffff0000 410 #define SCC_CD_SHIFT 16 411 412 413 #define SYCC_IE 0x00000001 414 #define SYCC_AE 0x00000002 415 #define SYCC_FP 0x00000004 416 #define SYCC_AR 0x00000008 417 #define SYCC_HR 0x00000010 418 #define SYCC_CD_MASK 0xffff0000 419 #define SYCC_CD_SHIFT 16 420 421 422 #define CF_EN 0x00000001 423 #define CF_EM_MASK 0x0000000e 424 #define CF_EM_SHIFT 1 425 #define CF_EM_FLASH 0 426 #define CF_EM_SYNC 2 427 #define CF_EM_PCMCIA 4 428 #define CF_DS 0x00000010 429 #define CF_BS 0x00000020 430 #define CF_CD_MASK 0x000000c0 431 #define CF_CD_SHIFT 6 432 #define CF_CD_DIV2 0x00000000 433 #define CF_CD_DIV3 0x00000040 434 #define CF_CD_DIV4 0x00000080 435 #define CF_CE 0x00000100 436 #define CF_SB 0x00000200 437 438 439 #define PM_W0_MASK 0x0000003f 440 #define PM_W1_MASK 0x00001f00 441 #define PM_W1_SHIFT 8 442 #define PM_W2_MASK 0x001f0000 443 #define PM_W2_SHIFT 16 444 #define PM_W3_MASK 0x1f000000 445 #define PM_W3_SHIFT 24 446 447 448 #define PA_W0_MASK 0x0000003f 449 #define PA_W1_MASK 0x00001f00 450 #define PA_W1_SHIFT 8 451 #define PA_W2_MASK 0x001f0000 452 #define PA_W2_SHIFT 16 453 #define PA_W3_MASK 0x1f000000 454 #define PA_W3_SHIFT 24 455 456 457 #define PI_W0_MASK 0x0000003f 458 #define PI_W1_MASK 0x00001f00 459 #define PI_W1_SHIFT 8 460 #define PI_W2_MASK 0x001f0000 461 #define PI_W2_SHIFT 16 462 #define PI_W3_MASK 0x1f000000 463 #define PI_W3_SHIFT 24 464 465 466 #define PW_W0_MASK 0x0000001f 467 #define PW_W1_MASK 0x00001f00 468 #define PW_W1_SHIFT 8 469 #define PW_W2_MASK 0x001f0000 470 #define PW_W2_SHIFT 16 471 #define PW_W3_MASK 0x1f000000 472 #define PW_W3_SHIFT 24 473 474 #define PW_W0 0x0000000c 475 #define PW_W1 0x00000a00 476 #define PW_W2 0x00020000 477 #define PW_W3 0x01000000 478 479 480 #define FW_W0_MASK 0x0000003f 481 #define FW_W1_MASK 0x00001f00 482 #define FW_W1_SHIFT 8 483 #define FW_W2_MASK 0x001f0000 484 #define FW_W2_SHIFT 16 485 #define FW_W3_MASK 0x1f000000 486 #define FW_W3_SHIFT 24 487 488 489 #define WATCHDOG_CLOCK 48000000 490 #define WATCHDOG_CLOCK_5354 32000 491 492 493 #define PCTL_ILP_DIV_MASK 0xffff0000 494 #define PCTL_ILP_DIV_SHIFT 16 495 #define PCTL_PLL_PLLCTL_UPD 0x00000400 496 #define PCTL_NOILP_ON_WAIT 0x00000200 497 #define PCTL_HT_REQ_EN 0x00000100 498 #define PCTL_ALP_REQ_EN 0x00000080 499 #define PCTL_XTALFREQ_MASK 0x0000007c 500 #define PCTL_XTALFREQ_SHIFT 2 501 #define PCTL_ILP_DIV_EN 0x00000002 502 #define PCTL_LPO_SEL 0x00000001 503 504 505 #define CSTRETCH_HT 0xffff0000 506 #define CSTRETCH_ALP 0x0000ffff 507 508 509 #define GPIO_ONTIME_SHIFT 16 510 511 512 #define CN_N1_MASK 0x3f 513 #define CN_N2_MASK 0x3f00 514 #define CN_N2_SHIFT 8 515 #define CN_PLLC_MASK 0xf0000 516 #define CN_PLLC_SHIFT 16 517 518 519 #define CC_M1_MASK 0x3f 520 #define CC_M2_MASK 0x3f00 521 #define CC_M2_SHIFT 8 522 #define CC_M3_MASK 0x3f0000 523 #define CC_M3_SHIFT 16 524 #define CC_MC_MASK 0x1f000000 525 #define CC_MC_SHIFT 24 526 527 528 #define CC_F6_2 0x02 529 #define CC_F6_3 0x03 530 #define CC_F6_4 0x05 531 #define CC_F6_5 0x09 532 #define CC_F6_6 0x11 533 #define CC_F6_7 0x21 534 535 #define CC_F5_BIAS 5 536 537 #define CC_MC_BYPASS 0x08 538 #define CC_MC_M1 0x04 539 #define CC_MC_M1M2 0x02 540 #define CC_MC_M1M2M3 0x01 541 #define CC_MC_M1M3 0x11 542 543 544 #define CC_T2_BIAS 2 545 #define CC_T2M2_BIAS 3 546 547 #define CC_T2MC_M1BYP 1 548 #define CC_T2MC_M2BYP 2 549 #define CC_T2MC_M3BYP 4 550 551 552 #define CC_T6_MMASK 1 553 #define CC_T6_M0 120000000 554 #define CC_T6_M1 100000000 555 #define SB2MIPS_T6(sb) (2 * (sb)) 556 557 558 #define CC_CLOCK_BASE1 24000000 559 #define CC_CLOCK_BASE2 12500000 560 561 562 #define CLKC_5350_N 0x0311 563 #define CLKC_5350_M 0x04020009 564 565 566 #define FLASH_NONE 0x000 567 #define SFLASH_ST 0x100 568 #define SFLASH_AT 0x200 569 #define PFLASH 0x700 570 571 572 #define CC_CFG_EN 0x0001 573 #define CC_CFG_EM_MASK 0x000e 574 #define CC_CFG_EM_ASYNC 0x0000 575 #define CC_CFG_EM_SYNC 0x0002 576 #define CC_CFG_EM_PCMCIA 0x0004 577 #define CC_CFG_EM_IDE 0x0006 578 #define CC_CFG_DS 0x0010 579 #define CC_CFG_CD_MASK 0x00e0 580 #define CC_CFG_CE 0x0100 581 #define CC_CFG_SB 0x0200 582 #define CC_CFG_IS 0x0400 583 584 585 #define CC_EB_BASE 0x1a000000 586 #define CC_EB_PCMCIA_MEM 0x1a000000 587 #define CC_EB_PCMCIA_IO 0x1a200000 588 #define CC_EB_PCMCIA_CFG 0x1a400000 589 #define CC_EB_IDE 0x1a800000 590 #define CC_EB_PCMCIA1_MEM 0x1a800000 591 #define CC_EB_PCMCIA1_IO 0x1aa00000 592 #define CC_EB_PCMCIA1_CFG 0x1ac00000 593 #define CC_EB_PROGIF 0x1b000000 594 595 596 597 #define SFLASH_OPCODE 0x000000ff 598 #define SFLASH_ACTION 0x00000700 599 #define SFLASH_CS_ACTIVE 0x00001000 600 #define SFLASH_START 0x80000000 601 #define SFLASH_BUSY SFLASH_START 602 603 604 #define SFLASH_ACT_OPONLY 0x0000 605 #define SFLASH_ACT_OP1D 0x0100 606 #define SFLASH_ACT_OP3A 0x0200 607 #define SFLASH_ACT_OP3A1D 0x0300 608 #define SFLASH_ACT_OP3A4D 0x0400 609 #define SFLASH_ACT_OP3A4X4D 0x0500 610 #define SFLASH_ACT_OP3A1X4D 0x0700 611 612 613 #define SFLASH_ST_WREN 0x0006 614 #define SFLASH_ST_WRDIS 0x0004 615 #define SFLASH_ST_RDSR 0x0105 616 #define SFLASH_ST_WRSR 0x0101 617 #define SFLASH_ST_READ 0x0303 618 #define SFLASH_ST_PP 0x0302 619 #define SFLASH_ST_SE 0x02d8 620 #define SFLASH_ST_BE 0x00c7 621 #define SFLASH_ST_DP 0x00b9 622 #define SFLASH_ST_RES 0x03ab 623 #define SFLASH_ST_CSA 0x1000 624 625 626 #define SFLASH_ST_WIP 0x01 627 #define SFLASH_ST_WEL 0x02 628 #define SFLASH_ST_BP_MASK 0x1c 629 #define SFLASH_ST_BP_SHIFT 2 630 #define SFLASH_ST_SRWD 0x80 631 632 633 #define SFLASH_AT_READ 0x07e8 634 #define SFLASH_AT_PAGE_READ 0x07d2 635 #define SFLASH_AT_BUF1_READ 636 #define SFLASH_AT_BUF2_READ 637 #define SFLASH_AT_STATUS 0x01d7 638 #define SFLASH_AT_BUF1_WRITE 0x0384 639 #define SFLASH_AT_BUF2_WRITE 0x0387 640 #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 641 #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 642 #define SFLASH_AT_BUF1_PROGRAM 0x0288 643 #define SFLASH_AT_BUF2_PROGRAM 0x0289 644 #define SFLASH_AT_PAGE_ERASE 0x0281 645 #define SFLASH_AT_BLOCK_ERASE 0x0250 646 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 647 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 648 #define SFLASH_AT_BUF1_LOAD 0x0253 649 #define SFLASH_AT_BUF2_LOAD 0x0255 650 #define SFLASH_AT_BUF1_COMPARE 0x0260 651 #define SFLASH_AT_BUF2_COMPARE 0x0261 652 #define SFLASH_AT_BUF1_REPROGRAM 0x0258 653 #define SFLASH_AT_BUF2_REPROGRAM 0x0259 654 655 656 #define SFLASH_AT_READY 0x80 657 #define SFLASH_AT_MISMATCH 0x40 658 #define SFLASH_AT_ID_MASK 0x38 659 #define SFLASH_AT_ID_SHIFT 3 660 661 662 663 #define UART_RX 0 664 #define UART_TX 0 665 #define UART_DLL 0 666 #define UART_IER 1 667 #define UART_DLM 1 668 #define UART_IIR 2 669 #define UART_FCR 2 670 #define UART_LCR 3 671 #define UART_MCR 4 672 #define UART_LSR 5 673 #define UART_MSR 6 674 #define UART_SCR 7 675 #define UART_LCR_DLAB 0x80 676 #define UART_LCR_WLEN8 0x03 677 #define UART_MCR_OUT2 0x08 678 #define UART_MCR_LOOP 0x10 679 #define UART_LSR_RX_FIFO 0x80 680 #define UART_LSR_TDHR 0x40 681 #define UART_LSR_THRE 0x20 682 #define UART_LSR_BREAK 0x10 683 #define UART_LSR_FRAMING 0x08 684 #define UART_LSR_PARITY 0x04 685 #define UART_LSR_OVERRUN 0x02 686 #define UART_LSR_RXRDY 0x01 687 #define UART_FCR_FIFO_ENABLE 1 688 689 690 #define UART_IIR_FIFO_MASK 0xc0 691 #define UART_IIR_INT_MASK 0xf 692 #define UART_IIR_MDM_CHG 0x0 693 #define UART_IIR_NOINT 0x1 694 #define UART_IIR_THRE 0x2 695 #define UART_IIR_RCVD_DATA 0x4 696 #define UART_IIR_RCVR_STATUS 0x6 697 #define UART_IIR_CHAR_TIME 0xc 698 699 700 #define UART_IER_EDSSI 8 701 #define UART_IER_ELSI 4 702 #define UART_IER_ETBEI 2 703 #define UART_IER_ERBFI 1 704 705 706 #define PST_INTPEND 0x0040 707 #define PST_SBCLKST 0x0030 708 #define PST_SBCLKST_ILP 0x0010 709 #define PST_SBCLKST_ALP 0x0020 710 #define PST_SBCLKST_HT 0x0030 711 #define PST_ALPAVAIL 0x0008 712 #define PST_HTAVAIL 0x0004 713 #define PST_RESINIT 0x0003 714 715 716 #define PCAP_REV_MASK 0x000000ff 717 #define PCAP_RC_MASK 0x00001f00 718 #define PCAP_RC_SHIFT 8 719 #define PCAP_TC_MASK 0x0001e000 720 #define PCAP_TC_SHIFT 13 721 #define PCAP_PC_MASK 0x001e0000 722 #define PCAP_PC_SHIFT 17 723 #define PCAP_VC_MASK 0x01e00000 724 #define PCAP_VC_SHIFT 21 725 #define PCAP_CC_MASK 0x1e000000 726 #define PCAP_CC_SHIFT 25 727 #define PCAP5_PC_MASK 0x003e0000 728 #define PCAP5_PC_SHIFT 17 729 #define PCAP5_VC_MASK 0x07c00000 730 #define PCAP5_VC_SHIFT 22 731 #define PCAP5_CC_MASK 0xf8000000 732 #define PCAP5_CC_SHIFT 27 733 734 735 736 #define PRRT_TIME_MASK 0x03ff 737 #define PRRT_INTEN 0x0400 738 #define PRRT_REQ_ACTIVE 0x0800 739 #define PRRT_ALP_REQ 0x1000 740 #define PRRT_HT_REQ 0x2000 741 742 743 #define PMURES_BIT(bit) (1 << (bit)) 744 745 746 #define PMURES_MAX_RESNUM 30 747 748 749 750 751 #define PMU0_PLL0_PLLCTL0 0 752 #define PMU0_PLL0_PC0_PDIV_MASK 1 753 #define PMU0_PLL0_PC0_PDIV_FREQ 25000 754 #define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 755 #define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 756 #define PMU0_PLL0_PC0_DIV_ARM_BASE 8 757 758 759 #define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 760 #define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 761 #define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 762 #define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 763 #define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 764 #define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 765 #define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 766 #define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 767 768 769 #define PMU0_PLL0_PLLCTL1 1 770 #define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 771 #define PMU0_PLL0_PC1_WILD_INT_SHIFT 28 772 #define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 773 #define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 774 #define PMU0_PLL0_PC1_STOP_MOD 0x00000040 775 776 777 #define PMU0_PLL0_PLLCTL2 2 778 #define PMU0_PLL0_PC2_WILD_INT_MASK 0xf 779 #define PMU0_PLL0_PC2_WILD_INT_SHIFT 4 780 781 782 #define RES4328_EXT_SWITCHER_PWM 0 783 #define RES4328_BB_SWITCHER_PWM 1 784 #define RES4328_BB_SWITCHER_BURST 2 785 #define RES4328_BB_EXT_SWITCHER_BURST 3 786 #define RES4328_ILP_REQUEST 4 787 #define RES4328_RADIO_SWITCHER_PWM 5 788 #define RES4328_RADIO_SWITCHER_BURST 6 789 #define RES4328_ROM_SWITCH 7 790 #define RES4328_PA_REF_LDO 8 791 #define RES4328_RADIO_LDO 9 792 #define RES4328_AFE_LDO 10 793 #define RES4328_PLL_LDO 11 794 #define RES4328_BG_FILTBYP 12 795 #define RES4328_TX_FILTBYP 13 796 #define RES4328_RX_FILTBYP 14 797 #define RES4328_XTAL_PU 15 798 #define RES4328_XTAL_EN 16 799 #define RES4328_BB_PLL_FILTBYP 17 800 #define RES4328_RF_PLL_FILTBYP 18 801 #define RES4328_BB_PLL_PU 19 802 803 #define RES5354_EXT_SWITCHER_PWM 0 804 #define RES5354_BB_SWITCHER_PWM 1 805 #define RES5354_BB_SWITCHER_BURST 2 806 #define RES5354_BB_EXT_SWITCHER_BURST 3 807 #define RES5354_ILP_REQUEST 4 808 #define RES5354_RADIO_SWITCHER_PWM 5 809 #define RES5354_RADIO_SWITCHER_BURST 6 810 #define RES5354_ROM_SWITCH 7 811 #define RES5354_PA_REF_LDO 8 812 #define RES5354_RADIO_LDO 9 813 #define RES5354_AFE_LDO 10 814 #define RES5354_PLL_LDO 11 815 #define RES5354_BG_FILTBYP 12 816 #define RES5354_TX_FILTBYP 13 817 #define RES5354_RX_FILTBYP 14 818 #define RES5354_XTAL_PU 15 819 #define RES5354_XTAL_EN 16 820 #define RES5354_BB_PLL_FILTBYP 17 821 #define RES5354_RF_PLL_FILTBYP 18 822 #define RES5354_BB_PLL_PU 19 823 824 825 826 #define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 827 #define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 828 #define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 829 830 831 #define PMU2_PHY_PLL_PLLCTL 4 832 #define PMU2_SI_PLL_PLLCTL 10 833 834 835 #define RES4325_BUCK_BOOST_BURST 0 836 #define RES4325_CBUCK_BURST 1 837 #define RES4325_CBUCK_PWM 2 838 #define RES4325_CLDO_CBUCK_BURST 3 839 #define RES4325_CLDO_CBUCK_PWM 4 840 #define RES4325_BUCK_BOOST_PWM 5 841 #define RES4325_ILP_REQUEST 6 842 #define RES4325_ABUCK_BURST 7 843 #define RES4325_ABUCK_PWM 8 844 #define RES4325_LNLDO1_PU 9 845 #define RES4325_OTP_PU 10 846 #define RES4325_LNLDO3_PU 11 847 #define RES4325_LNLDO4_PU 12 848 #define RES4325_XTAL_PU 13 849 #define RES4325_ALP_AVAIL 14 850 #define RES4325_RX_PWRSW_PU 15 851 #define RES4325_TX_PWRSW_PU 16 852 #define RES4325_RFPLL_PWRSW_PU 17 853 #define RES4325_LOGEN_PWRSW_PU 18 854 #define RES4325_AFE_PWRSW_PU 19 855 #define RES4325_BBPLL_PWRSW_PU 20 856 #define RES4325_HT_AVAIL 21 857 858 859 #define RES4325B0_CBUCK_LPOM 1 860 #define RES4325B0_CBUCK_BURST 2 861 #define RES4325B0_CBUCK_PWM 3 862 #define RES4325B0_CLDO_PU 4 863 864 865 #define RES4325C1_OTP_PWRSW_PU 10 866 #define RES4325C1_LNLDO2_PU 12 867 868 869 #define CST4325_SPROM_OTP_SEL_MASK 0x00000003 870 #define CST4325_DEFCIS_SEL 0 871 #define CST4325_SPROM_SEL 1 872 #define CST4325_OTP_SEL 2 873 #define CST4325_OTP_PWRDN 3 874 #define CST4325_SDIO_USB_MODE_MASK 0x00000004 875 #define CST4325_SDIO_USB_MODE_SHIFT 2 876 #define CST4325_RCAL_VALID_MASK 0x00000008 877 #define CST4325_RCAL_VALID_SHIFT 3 878 #define CST4325_RCAL_VALUE_MASK 0x000001f0 879 #define CST4325_RCAL_VALUE_SHIFT 4 880 #define CST4325_PMUTOP_2B_MASK 0x00000200 881 #define CST4325_PMUTOP_2B_SHIFT 9 882 883 #define RES4329_RESERVED0 0 884 #define RES4329_CBUCK_LPOM 1 885 #define RES4329_CBUCK_BURST 2 886 #define RES4329_CBUCK_PWM 3 887 #define RES4329_CLDO_PU 4 888 #define RES4329_PALDO_PU 5 889 #define RES4329_ILP_REQUEST 6 890 #define RES4329_RESERVED7 7 891 #define RES4329_RESERVED8 8 892 #define RES4329_LNLDO1_PU 9 893 #define RES4329_OTP_PU 10 894 #define RES4329_RESERVED11 11 895 #define RES4329_LNLDO2_PU 12 896 #define RES4329_XTAL_PU 13 897 #define RES4329_ALP_AVAIL 14 898 #define RES4329_RX_PWRSW_PU 15 899 #define RES4329_TX_PWRSW_PU 16 900 #define RES4329_RFPLL_PWRSW_PU 17 901 #define RES4329_LOGEN_PWRSW_PU 18 902 #define RES4329_AFE_PWRSW_PU 19 903 #define RES4329_BBPLL_PWRSW_PU 20 904 #define RES4329_HT_AVAIL 21 905 906 #define CST4329_SPROM_OTP_SEL_MASK 0x00000003 907 #define CST4329_DEFCIS_SEL 0 908 #define CST4329_SPROM_SEL 1 909 #define CST4329_OTP_SEL 2 910 #define CST4329_OTP_PWRDN 3 911 #define CST4329_SPI_SDIO_MODE_MASK 0x00000004 912 #define CST4329_SPI_SDIO_MODE_SHIFT 2 913 914 915 #define RES4312_SWITCHER_BURST 0 916 #define RES4312_SWITCHER_PWM 1 917 #define RES4312_PA_REF_LDO 2 918 #define RES4312_CORE_LDO_BURST 3 919 #define RES4312_CORE_LDO_PWM 4 920 #define RES4312_RADIO_LDO 5 921 #define RES4312_ILP_REQUEST 6 922 #define RES4312_BG_FILTBYP 7 923 #define RES4312_TX_FILTBYP 8 924 #define RES4312_RX_FILTBYP 9 925 #define RES4312_XTAL_PU 10 926 #define RES4312_ALP_AVAIL 11 927 #define RES4312_BB_PLL_FILTBYP 12 928 #define RES4312_RF_PLL_FILTBYP 13 929 #define RES4312_HT_AVAIL 14 930 931 #define RES4322_RF_LDO 0 932 #define RES4322_ILP_REQUEST 1 933 #define RES4322_XTAL_PU 2 934 #define RES4322_ALP_AVAIL 3 935 #define RES4322_SI_PLL_ON 4 936 #define RES4322_HT_SI_AVAIL 5 937 #define RES4322_PHY_PLL_ON 6 938 #define RES4322_HT_PHY_AVAIL 7 939 #define RES4322_OTP_PU 8 940 941 942 #define CST4322_XTAL_FREQ_20_40MHZ 0x00000020 943 #define CST4322_SPROM_OTP_SEL_MASK 0x000000c0 944 #define CST4322_SPROM_OTP_SEL_SHIFT 6 945 #define CST4322_NO_SPROM_OTP 0 946 #define CST4322_SPROM_PRESENT 1 947 #define CST4322_OTP_PRESENT 2 948 #define CST4322_PCI_OR_USB 0x00000100 949 #define CST4322_BOOT_MASK 0x00000600 950 #define CST4322_BOOT_SHIFT 9 951 #define CST4322_BOOT_FROM_SRAM 0 952 #define CST4322_BOOT_FROM_ROM 1 953 #define CST4322_BOOT_FROM_FLASH 2 954 #define CST4322_BOOT_FROM_INVALID 3 955 #define CST4322_ILP_DIV_EN 0x00000800 956 #define CST4322_FLASH_TYPE_MASK 0x00001000 957 #define CST4322_FLASH_TYPE_SHIFT 12 958 #define CST4322_FLASH_TYPE_SHIFT_ST 0 959 #define CST4322_FLASH_TYPE_SHIFT_ATMEL 1 960 #define CST4322_ARM_TAP_SEL 0x00002000 961 #define CST4322_RES_INIT_MODE_MASK 0x0000c000 962 #define CST4322_RES_INIT_MODE_SHIFT 14 963 #define CST4322_RES_INIT_MODE_ILPAVAIL 0 964 #define CST4322_RES_INIT_MODE_ILPREQ 1 965 #define CST4322_RES_INIT_MODE_ALPAVAIL 2 966 #define CST4322_RES_INIT_MODE_HTAVAIL 3 967 #define CST4322_PCIPLLCLK_GATING 0x00010000 968 #define CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 969 #define CST4322_PCI_CARDBUS_MODE 0x00040000 970 971 #define RES4315_CBUCK_LPOM 1 972 #define RES4315_CBUCK_BURST 2 973 #define RES4315_CBUCK_PWM 3 974 #define RES4315_CLDO_PU 4 975 #define RES4315_PALDO_PU 5 976 #define RES4315_ILP_REQUEST 6 977 #define RES4315_LNLDO1_PU 9 978 #define RES4315_OTP_PU 10 979 #define RES4315_LNLDO2_PU 12 980 #define RES4315_XTAL_PU 13 981 #define RES4315_ALP_AVAIL 14 982 #define RES4315_RX_PWRSW_PU 15 983 #define RES4315_TX_PWRSW_PU 16 984 #define RES4315_RFPLL_PWRSW_PU 17 985 #define RES4315_LOGEN_PWRSW_PU 18 986 #define RES4315_AFE_PWRSW_PU 19 987 #define RES4315_BBPLL_PWRSW_PU 20 988 #define RES4315_HT_AVAIL 21 989 990 #define CST4315_SPROM_OTP_SEL_MASK 0x00000003 991 #define CST4315_DEFCIS_SEL 0x00000000 992 #define CST4315_SPROM_SEL 0x00000001 993 #define CST4315_OTP_SEL 0x00000002 994 #define CST4315_OTP_PWRDN 0x00000003 995 #define CST4315_SDIO_MODE 0x00000004 996 #define CST4315_RCAL_VALID 0x00000008 997 #define CST4315_RCAL_VALUE_MASK 0x000001f0 998 #define CST4315_RCAL_VALUE_SHIFT 4 999 #define CST4315_PALDO_EXTPNP 0x00000200 1000 #define CST4315_CBUCK_MODE_MASK 0x00000c00 1001 #define CST4315_CBUCK_MODE_BURST 0x00000400 1002 #define CST4315_CBUCK_MODE_LPBURST 0x00000c00 1003 1004 #define PMU_MAX_TRANSITION_DLY 15000 1005 1006 1007 #define PMURES_UP_TRANSITION 2 1008 1009 1010 1011 1012 1013 #define ECI_BW_20 0x0 1014 #define ECI_BW_25 0x1 1015 #define ECI_BW_30 0x2 1016 #define ECI_BW_35 0x3 1017 #define ECI_BW_40 0x4 1018 #define ECI_BW_45 0x5 1019 #define ECI_BW_50 0x6 1020 #define ECI_BW_ALL 0x7 1021 1022 1023 #define WLAN_NUM_ANT1 TXANT_0 1024 #define WLAN_NUM_ANT2 TXANT_1 1025 1026 #endif 1027