1 /**************************************************************************** 2 **+-----------------------------------------------------------------------+** 3 **| |** 4 **| Copyright(c) 1998 - 2008 Texas Instruments. All rights reserved. |** 5 **| All rights reserved. |** 6 **| |** 7 **| Redistribution and use in source and binary forms, with or without |** 8 **| modification, are permitted provided that the following conditions |** 9 **| are met: |** 10 **| |** 11 **| * Redistributions of source code must retain the above copyright |** 12 **| notice, this list of conditions and the following disclaimer. |** 13 **| * Redistributions in binary form must reproduce the above copyright |** 14 **| notice, this list of conditions and the following disclaimer in |** 15 **| the documentation and/or other materials provided with the |** 16 **| distribution. |** 17 **| * Neither the name Texas Instruments nor the names of its |** 18 **| contributors may be used to endorse or promote products derived |** 19 **| from this software without specific prior written permission. |** 20 **| |** 21 **| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |** 22 **| "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |** 23 **| LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |** 24 **| A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |** 25 **| OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |** 26 **| SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |** 27 **| LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |** 28 **| DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |** 29 **| THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |** 30 **| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |** 31 **| OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |** 32 **| |** 33 **+-----------------------------------------------------------------------+** 34 ****************************************************************************/ 35 36 /**************************************************************************** 37 * 38 * MODULE: hwAccess.c 39 * PURPOSE: Support access to the wlan hardware registers and memory 40 * 41 ****************************************************************************/ 42 43 #ifndef __WHAL_HW_ACCESS_H__ 44 #define __WHAL_HW_ACCESS_H__ 45 46 /************************************************************************ 47 * partition addresses 48 * 49 * each access region will have its base address and the HAL will use only the logical offset 50 * there isnt an access region for the registers. 51 * for the mem the access regions are defined for their functionality : double-buffer,tx registers, rx registers etc... 52 * 53 * EXAMPLE : 54 * if the HAL wants to read register at offset 0xA the the call will be : 55 * whal_hwAccess_ReadReg(hHwAccess, 0xA, &RegVal); 56 * if the HAL wants to read 4bytes from mem at offset 0x10 in the double-buffer region the the call will be: 57 * whal_hwAccess_ReadMem(hHwAccess, HW_ACCESS_BASE_DOUBLE_BUFFER + 0x10, &RegVal , 4); 58 ************************************************************************/ 59 60 #define HW_ACCESS_BASE_DOUBLE_BUFFER 0 61 #define HW_ACCESS_BASE_CMD_MBX 0 62 63 #define HEALTH_REPORT_BUS_ERROR BIT_2 64 65 /************************************************************************ 66 * Return codes 67 ************************************************************************/ 68 #define ERROR_HW_ACCEESS_ADDR 10 69 #define ERROR_HW_ACCEESS_LEN 11 70 71 /************************************************************************ 72 * Types 73 ************************************************************************/ 74 typedef void (*HwAccess_callback_t)(void *data,int status); 75 76 /************************************************************************ 77 * partition addresses 78 ************************************************************************/ 79 80 /* Download phase */ 81 #define HW_ACCESS_DOWN_PART0_SIZE 0x16800 82 #define HW_ACCESS_DOWN_PART0_ADDR 0x0 83 #define HW_ACCESS_DOWN_PART1_SIZE 0x8800 84 #define HW_ACCESS_DOWN_PART1_ADDR 0x300000 85 86 /* Working phase */ 87 #ifdef TNETW1251 88 #define HW_ACCESS_WORK_PART0_SIZE 0x14000 89 #define HW_ACCESS_WORK_PART0_ADDR 0x28000 90 #define HW_ACCESS_WORK_PART1_SIZE 0xB000 91 #else 92 #define HW_ACCESS_WORK_PART0_SIZE 0x16800 93 #define HW_ACCESS_WORK_PART0_ADDR 0xF000 94 #define HW_ACCESS_WORK_PART1_SIZE 0x8800 95 #endif 96 #define HW_ACCESS_WORK_PART1_ADDR 0x300000 97 98 #define HW_ACCESS_MAX_PARTITIONS 2 99 100 #ifndef HW_ACCESS_MEMORY_MAX_RANGE /* this macro is already defined in SDIO client driver */ 101 #define HW_ACCESS_MEMORY_MAX_RANGE 0x1FFC0 102 #endif /* ifndef HW_ACCESS_MEMORY_MAX_RANGE */ 103 104 #define HW_ACCESS_PRAM_MAX_RANGE 0x3c000 105 106 /************************************************************************ 107 * Functions 108 ************************************************************************/ 109 110 extern int whal_hwAccess_ReConfig(TI_HANDLE hHwAccess); 111 extern int whal_hwAccess_Stop(TI_HANDLE hHwAccess); 112 113 #if (defined (HW_ACCESS_SDIO) || defined (HW_ACCESS_WSPI)) 114 TI_STATUS whal_hwAccess_RecreateInterface(TI_HANDLE hHwAccess); 115 #endif 116 117 /* new API */ 118 /***********/ 119 120 TI_HANDLE whal_hwAccess_Create(TI_HANDLE hOs); 121 int whal_hwAccess_Destroy(TI_HANDLE hHwAccess); 122 int whal_hwAccess_Config(TI_HANDLE hHwAccess, TI_HANDLE hReport,UINT32 RegBaseAddr, UINT32 MemBaseAddr, HwAccess_callback_t CBFunc,void* CBArg); 123 124 int whal_hwAccess_SetPartitions(TI_HANDLE hHwAccess, TNETIF_HwAccess_SetPartition_mode_e partitionMode, UINT32 partition_start); 125 int whal_hwAccess_SetPartitionsAsync(TI_HANDLE hHwAccess, TNETIF_HwAccess_SetPartition_mode_e partitionMode, UINT32 partition_start); 126 UINT8 whal_hwAccess_Get_Async_Mode(TI_HANDLE hHwAccess); 127 int whal_hwAccess_WriteELP(TI_HANDLE hHwAccess, UINT32 data); 128 int whal_hwAccess_WriteELPAsync(TI_HANDLE hHwAccess, UINT32 data, BOOL bCb, BOOL bMore); 129 int whal_hwAccess_ReadELPAsync (TI_HANDLE hHwAccess, UINT8 *data, BOOL bCb, BOOL bMore); 130 131 int whal_hwAccess_ReadMem_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len); 132 int whal_hwAccess_WriteMem_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len); 133 int whal_hwAccess_ReadMemAsync_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len); 134 int whal_hwAccess_WriteMemAsync_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len); 135 136 int whal_hwAccess_ReadMem(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len); 137 int whal_hwAccess_WriteMem(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len); 138 int whal_hwAccess_ReadMemAsync(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len); 139 TI_STATUS whal_hwAccess_WriteMemAsync(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len); 140 141 int whal_hwAccess_ReadReg(TI_HANDLE hHwAccess, UINT32 addr, UINT32* data); 142 int whal_hwAccess_WriteReg(TI_HANDLE hHwAccess, UINT32 addr, UINT32 data); 143 int whal_hwAccess_ReadRegAsync(TI_HANDLE hHwAccess, UINT32 addr, UINT32* data); 144 int whal_hwAccess_WriteRegAsync(TI_HANDLE hHwAccess, UINT32 addr, UINT32 data); 145 146 void whal_hwAccess_Print(TI_HANDLE hHwAccess); 147 148 /*old - new*/ 149 /* 150 * Hardware memory Api 151 */ 152 UINT8 whal_hwAccess_GetU08 (TI_HANDLE hHwAccess, UINT32 Addr); 153 void whal_hwAccess_SetU08 (TI_HANDLE hHwAccess, UINT32 Addr, UINT8 Val); 154 void whal_hwAccess_SetU08_Bits (TI_HANDLE hHwAccess, UINT32 Addr, UINT8 BitsVal); 155 void whal_hwAccess_ResetU08_Bits(TI_HANDLE hHwAccess, UINT32 Addr, UINT8 BitsVal); 156 UINT16 whal_hwAccess_GetU16 (TI_HANDLE hHwAccess, UINT32 Addr); 157 void whal_hwAccess_SetU16 (TI_HANDLE hHwAccess, UINT32 Addr, UINT16 Val); 158 void whal_hwAccess_SetU16_Bits (TI_HANDLE hHwAccess, UINT32 Addr, UINT16 BitsVal); 159 void whal_hwAccess_ResetU16_Bits(TI_HANDLE hHwAccess, UINT32 Addr, UINT16 BitsVal); 160 UINT32 whal_hwAccess_GetU32 (TI_HANDLE hHwAccess, UINT32 Addr); 161 void whal_hwAccess_SetU32 (TI_HANDLE hHwAccess, UINT32 Addr, UINT32 Val); 162 void whal_hwAccess_SetU32_Bits (TI_HANDLE hHwAccess, UINT32 Addr, UINT32 BitsVal); 163 void whal_hwAccess_ResetU32_Bits(TI_HANDLE hHwAccess, UINT32 Addr, UINT32 BitsVal); 164 165 /* 166 * Hardware Registers Api 167 */ 168 void whal_hwAccess_RegSetBitVal (TI_HANDLE hHwAccess, UINT32 RegAddr, UINT32 BitVal); 169 void whal_hwAccess_RegResetBitVal(TI_HANDLE hHwAccess, UINT32 RegAddr, UINT32 BitVal); 170 int whal_hwAccess_RegIsBitSet (TI_HANDLE hHwAccess, UINT32 RegAddr, UINT32 BitVal); 171 172 173 174 175 TI_STATUS whal_hwAccess_RegisterForErrorCB(TI_HANDLE hHwAccess,void* CbFunc,TI_HANDLE CbObj); 176 177 178 #endif /*__WHAL_HW_ACCESS_H__*/ 179