1 /* 2 * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions. 3 * 4 * Copyright (C) 1999-2009, Broadcom Corporation 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * $Id: sbpcmcia.h,v 13.31.4.1.2.3.8.7 2009/06/22 05:14:24 Exp $ 25 */ 26 27 28 #ifndef _SBPCMCIA_H 29 #define _SBPCMCIA_H 30 31 32 33 34 #define PCMCIA_FCR (0x700 / 2) 35 36 #define FCR0_OFF 0 37 #define FCR1_OFF (0x40 / 2) 38 #define FCR2_OFF (0x80 / 2) 39 #define FCR3_OFF (0xc0 / 2) 40 41 #define PCMCIA_FCR0 (0x700 / 2) 42 #define PCMCIA_FCR1 (0x740 / 2) 43 #define PCMCIA_FCR2 (0x780 / 2) 44 #define PCMCIA_FCR3 (0x7c0 / 2) 45 46 47 48 #define PCMCIA_COR 0 49 50 #define COR_RST 0x80 51 #define COR_LEV 0x40 52 #define COR_IRQEN 0x04 53 #define COR_BLREN 0x01 54 #define COR_FUNEN 0x01 55 56 57 #define PCICIA_FCSR (2 / 2) 58 #define PCICIA_PRR (4 / 2) 59 #define PCICIA_SCR (6 / 2) 60 #define PCICIA_ESR (8 / 2) 61 62 63 #define PCM_MEMOFF 0x0000 64 #define F0_MEMOFF 0x1000 65 #define F1_MEMOFF 0x2000 66 #define F2_MEMOFF 0x3000 67 #define F3_MEMOFF 0x4000 68 69 70 #define MEM_ADDR0 (0x728 / 2) 71 #define MEM_ADDR1 (0x72a / 2) 72 #define MEM_ADDR2 (0x72c / 2) 73 74 75 #define PCMCIA_ADDR0 (0x072e / 2) 76 #define PCMCIA_ADDR1 (0x0730 / 2) 77 #define PCMCIA_ADDR2 (0x0732 / 2) 78 79 #define MEM_SEG (0x0734 / 2) 80 #define SROM_CS (0x0736 / 2) 81 #define SROM_DATAL (0x0738 / 2) 82 #define SROM_DATAH (0x073a / 2) 83 #define SROM_ADDRL (0x073c / 2) 84 #define SROM_ADDRH (0x073e / 2) 85 #define SROM_INFO2 (0x0772 / 2) 86 #define SROM_INFO (0x07be / 2) 87 88 89 #define SROM_IDLE 0 90 #define SROM_WRITE 1 91 #define SROM_READ 2 92 #define SROM_WEN 4 93 #define SROM_WDS 7 94 #define SROM_DONE 8 95 96 97 #define SRI_SZ_MASK 0x03 98 #define SRI_BLANK 0x04 99 #define SRI_OTP 0x80 100 101 102 103 #define SBTML_INT_ACK 0x40000 104 #define SBTML_INT_EN 0x20000 105 106 107 #define SBTMH_INT_STATUS 0x40000 108 109 #endif 110