1 /**************************************************************************** 2 **+-----------------------------------------------------------------------+** 3 **| |** 4 **| Copyright(c) 1998 - 2008 Texas Instruments. All rights reserved. |** 5 **| All rights reserved. |** 6 **| |** 7 **| Redistribution and use in source and binary forms, with or without |** 8 **| modification, are permitted provided that the following conditions |** 9 **| are met: |** 10 **| |** 11 **| * Redistributions of source code must retain the above copyright |** 12 **| notice, this list of conditions and the following disclaimer. |** 13 **| * Redistributions in binary form must reproduce the above copyright |** 14 **| notice, this list of conditions and the following disclaimer in |** 15 **| the documentation and/or other materials provided with the |** 16 **| distribution. |** 17 **| * Neither the name Texas Instruments nor the names of its |** 18 **| contributors may be used to endorse or promote products derived |** 19 **| from this software without specific prior written permission. |** 20 **| |** 21 **| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |** 22 **| "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |** 23 **| LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |** 24 **| A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |** 25 **| OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |** 26 **| SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |** 27 **| LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |** 28 **| DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |** 29 **| THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |** 30 **| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |** 31 **| OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |** 32 **| |** 33 **+-----------------------------------------------------------------------+** 34 ****************************************************************************/ 35 36 #ifndef _WHAL_DEFAULT_PARAMS_H 37 #define _WHAL_DEFAULT_PARAMS_H 38 39 40 /***************************************************************************** 41 ** ** 42 ** ** 43 ** CONSTANTS ** 44 ** ** 45 ** ** 46 *****************************************************************************/ 47 48 /* PALAU Group Address Default Values */ 49 #define NUM_GROUP_ADDRESS_VALUE_DEF 0 50 #define NUM_GROUP_ADDRESS_VALUE_MIN 0 51 #define NUM_GROUP_ADDRESS_VALUE_MAX 8 52 53 /* Early Wakeup Default Values */ 54 #define EARLY_WAKEUP_ENABLE_MIN (FALSE) 55 #define EARLY_WAKEUP_ENABLE_MAX (TRUE) 56 #define EARLY_WAKEUP_ENABLE_DEF (TRUE) 57 58 /* ARP IP Filter Default Values */ 59 #define MIN_FILTER_ENABLE_VALUE 0 60 #define MAX_FILTER_ENABLE_VALUE 2 61 #define DEF_FILTER_ENABLE_VALUE 0 62 #define FILTER_ENABLE_FLAG_LEN 1 63 64 /* Beacon filter Deafult Values */ 65 #define DEF_BEACON_FILTER_ENABLE_VALUE 1 66 #define DEF_BEACON_FILTER_IE_TABLE_NUM 15 67 #define MIN_BEACON_FILTER_ENABLE_VALUE 0 68 #define MAX_BEACON_FILTER_ENABLE_VALUE 1 69 #define BEACON_FILTER_IE_TABLE_DEF_SIZE 35 70 #define BEACON_FILTER_IE_TABLE_MAX_SIZE 100 71 #define BEACON_FILTER_IE_TABLE_MIN_SIZE 0 72 #define BEACON_FILTER_IE_TABLE_MAX_NUM (6+32) 73 #define BEACON_FILTER_IE_TABLE_MIN_NUM 0 74 75 #define HAL_CTRL_BET_ENABLE_MIN 0 76 #define HAL_CTRL_BET_ENABLE_MAX 1 77 #define HAL_CTRL_BET_ENABLE_DEF 1 78 79 #define HAL_CTRL_BET_MAX_CONSC_MIN 1 80 #define HAL_CTRL_BET_MAX_CONSC_MAX 50 81 #define HAL_CTRL_BET_MAX_CONSC_DEF 8 82 83 /* TX XFER parameters */ 84 #define TX_XFER_HW_BUFFER_FULL_DUR_RECOVERY_DEF 50 85 #define TX_XFER_HW_BUFFER_FULL_DUR_RECOVERY_MIN 30 86 #define TX_XFER_HW_BUFFER_FULL_DUR_RECOVERY_MAX 1000 87 88 /* Default Value for Atheros time out value */ 89 #define DEF_TX_POWER_ADJUST_TIME_OUT 5000 90 91 #define DEF_NUM_STORED_FILTERS 1 92 #define MIN_NUM_STORED_FILTERS 1 93 #define MAX_NUM_STORED_FILTERS 8 94 95 #define HAL_CTRL_HW_ACCESS_METHOD_MIN 0 96 #define HAL_CTRL_HW_ACCESS_METHOD_MAX 2 97 #define HAL_CTRL_HW_ACCESS_METHOD_DEF 1 98 99 #define HAL_CTRL_SITE_FRAG_COLLECT_MIN 2 100 #define HAL_CTRL_SITE_FRAG_COLLECT_MAX 10 101 #define HAL_CTRL_SITE_FRAG_COLLECT_DEF 3 102 103 104 #define HAL_CTRL_HOST_RX_DESC_MIN 1 105 #define HAL_CTRL_HOST_RX_DESC_MAX 127 106 #define HAL_CTRL_HOST_RX_DESC_DEF 32 /* instead of 40 - for a bigger TKIP FW*/ 107 108 #define HAL_CTRL_HOST_TX_DESC_MIN 1 109 #define HAL_CTRL_HOST_TX_DESC_MAX 127 110 #define HAL_CTRL_HOST_TX_DESC_DEF 32 /* instead of 40 - for a bigger TKIP FW*/ 111 112 #define HAL_CTRL_ACX_RX_DESC_MIN 1 113 #define HAL_CTRL_ACX_RX_DESC_MAX 127 114 #define HAL_CTRL_ACX_RX_DESC_DEF 32 115 116 #define HAL_CTRL_ACX_TX_DESC_MIN 1 117 #define HAL_CTRL_ACX_TX_DESC_MAX 127 118 #define HAL_CTRL_ACX_TX_DESC_DEF 16 119 120 #define HAL_CTRL_ACX_BLOCK_SIZE_MIN 256 121 #define HAL_CTRL_ACX_BLOCK_SIZE_MAX 2000 122 #define HAL_CTRL_ACX_BLOCK_SIZE_DEF 256 123 124 #define HAL_CTRL_RX_BLOCKS_RATIO_MIN 0 125 #define HAL_CTRL_RX_BLOCKS_RATIO_MAX 100 126 #define HAL_CTRL_RX_BLOCKS_RATIO_DEF 50 127 128 #define HAL_CTRL_USE_PLCP_HDR_DEF 1 129 #define HAL_CTRL_USE_PLCP_HDR_MAX 1 130 #define HAL_CTRL_USE_PLCP_HDR_MIN 0 131 132 #define HAL_CTRL_TX_FLASH_ENABLE_MIN FALSE 133 #define HAL_CTRL_TX_FLASH_ENABLE_MAX TRUE 134 #define HAL_CTRL_TX_FLASH_ENABLE_DEF TRUE 135 136 #define HAL_CTRL_USE_INTR_TRHESHOLD_MIN 0 137 #define HAL_CTRL_USE_INTR_TRHESHOLD_MAX 1 138 #define HAL_CTRL_USE_INTR_TRHESHOLD_DEF 0 139 140 #define HAL_CTRL_USE_TX_DATA_INTR_MIN 0 141 #define HAL_CTRL_USE_TX_DATA_INTR_MAX 1 142 143 #if (!defined TIWLN_WINCE30) || (defined EMBEDDED_BOARD1) 144 #define HAL_CTRL_USE_TX_DATA_INTR_DEF 1 145 #else 146 #define HAL_CTRL_USE_TX_DATA_INTR_DEF 0 147 #endif 148 149 #define NUM_OF_CHANNELS_24 (14) 150 #define A_5G_BAND_MIN_CHANNEL 36 151 #define A_5G_BAND_MAX_CHANNEL 180 152 #define A_5G_BAND_NUM_CHANNELS (A_5G_BAND_MAX_CHANNEL-A_5G_BAND_MIN_CHANNEL+1) 153 154 155 #define HAL_CTRL_CALIBRATION_CHANNEL_2_4_MIN 1 156 #define HAL_CTRL_CALIBRATION_CHANNEL_2_4_MAX NUM_OF_CHANNELS_24 157 #define HAL_CTRL_CALIBRATION_CHANNEL_2_4_DEF 1 158 159 #define HAL_CTRL_CALIBRATION_CHANNEL_5_0_MIN 34 160 #define HAL_CTRL_CALIBRATION_CHANNEL_5_0_MAX A_5G_BAND_MAX_CHANNEL 161 #define HAL_CTRL_CALIBRATION_CHANNEL_5_0_DEF 36 162 163 #define HAL_CTRL_CALIBRATION_CHANNEL_4_9_MIN 8 164 #define HAL_CTRL_CALIBRATION_CHANNEL_4_9_MAX 16 165 #define HAL_CTRL_CALIBRATION_CHANNEL_4_9_DEF 12 166 167 #define HAL_CTRL_RTS_THRESHOLD_MIN 0 168 #define HAL_CTRL_RTS_THRESHOLD_MAX 4096 169 #define HAL_CTRL_RTS_THRESHOLD_DEF 2347 170 171 #define HAL_CTRL_BCN_RX_TIME_OUT_MIN 10 /* ms */ 172 #define HAL_CTRL_BCN_RX_TIME_OUT_MAX 1000 /* ms */ 173 #define HAL_CTRL_BCN_RX_TIME_OUT_DEF 10 /* ms */ 174 175 #define HAL_CTRL_RX_DISABLE_BROADCAST_MIN FALSE 176 #define HAL_CTRL_RX_DISABLE_BROADCAST_MAX TRUE 177 #define HAL_CTRL_RX_DISABLE_BROADCAST_DEF FALSE 178 179 /* Indicate if the recovery process is active or not */ 180 #define HAL_CTRL_RECOVERY_ENABLE_MIN FALSE 181 #define HAL_CTRL_RECOVERY_ENABLE_MAX TRUE 182 #define HAL_CTRL_RECOVERY_ENABLE_DEF TRUE 183 184 #define HAL_CTRL_FRAG_THRESHOLD_MIN 256 185 #define HAL_CTRL_FRAG_THRESHOLD_MAX 4096 186 #define HAL_CTRL_FRAG_THRESHOLD_DEF 2312 187 188 #define HAL_CTRL_MAX_TX_MSDU_LIFETIME_MIN 0 189 #define HAL_CTRL_MAX_TX_MSDU_LIFETIME_MAX 3000 190 #define HAL_CTRL_MAX_TX_MSDU_LIFETIME_DEF 512 191 192 #define HAL_CTRL_MAX_RX_MSDU_LIFETIME_MIN 0 193 #define HAL_CTRL_MAX_RX_MSDU_LIFETIME_MAX 0xFFFFFFFF 194 #define HAL_CTRL_MAX_RX_MSDU_LIFETIME_DEF 512000 195 196 197 #define HAL_CTRL_LISTEN_INTERVAL_MIN 1 198 #define HAL_CTRL_LISTEN_INTERVAL_MAX 10 199 #define HAL_CTRL_LISTEN_INTERVAL_DEF 3 200 201 #define HAL_CTRL_MAX_FULL_BEACON_MIN 0 202 #define HAL_CTRL_MAX_FULL_BEACON_MAX 10000 203 #define HAL_CTRL_MAX_FULL_BEACON_DEF 1000 204 205 #define HAL_CTRL_BET_ENABLE_THRESHOLD_MIN 0 206 #define HAL_CTRL_BET_ENABLE_THRESHOLD_MAX 255 207 #define HAL_CTRL_BET_ENABLE_THRESHOLD_DEF 8 208 209 #define HAL_CTRL_BET_DISABLE_THRESHOLD_MIN 0 210 #define HAL_CTRL_BET_DISABLE_THRESHOLD_MAX 255 211 #define HAL_CTRL_BET_DISABLE_THRESHOLD_DEF 12 212 213 /* This field indicates the number of transmit retries to attempt at 214 the rate specified in the TNETW1130 Tx descriptor before 215 falling back to the next lowest rate. 216 If this field is set to 0xff, then rate fallback is disabled. 217 If this field is 0, then there will be 0 retries before starting fallback.*/ 218 #define HAL_CTRL_RATE_FB_RETRY_LIMIT_MIN 0 /* => No retries before starting RateFallBack */ 219 #define HAL_CTRL_RATE_FB_RETRY_LIMIT_MAX 255 /* =>0xff for disabling Rate fallback */ 220 #define HAL_CTRL_RATE_FB_RETRY_LIMIT_DEF 0 221 222 #define HAL_CTRL_TX_ANTENNA_MIN TX_ANTENNA_2 223 #define HAL_CTRL_TX_ANTENNA_MAX TX_ANTENNA_1 224 #define HAL_CTRL_TX_ANTENNA_DEF TX_ANTENNA_1 225 226 #define HAL_CTRL_RX_ANTENNA_MIN RX_ANTENNA_1 227 #define HAL_CTRL_RX_ANTENNA_MAX RX_ANTENNA_PARTIAL 228 #define HAL_CTRL_RX_ANTENNA_DEF RX_ANTENNA_FULL 229 230 #define HAL_CTRL_TX_CMPLT_THRESHOLD_DEF 0 231 #define HAL_CTRL_TX_CMPLT_THRESHOLD_MIN 0 232 #define HAL_CTRL_TX_CMPLT_THRESHOLD_MAX 15 233 234 #define HAL_CTRL_ACI_MODE_MIN 0 235 #define HAL_CTRL_ACI_MODE_MAX 255 236 #define HAL_CTRL_ACI_MODE_DEF 0 237 238 #define HAL_CTRL_ACI_INPUT_CCA_MIN 0 239 #define HAL_CTRL_ACI_INPUT_CCA_MAX 255 240 #define HAL_CTRL_ACI_INPUT_CCA_DEF 1 241 242 #define HAL_CTRL_ACI_QUALIFIED_CCA_MIN 0 243 #define HAL_CTRL_ACI_QUALIFIED_CCA_MAX 255 244 #define HAL_CTRL_ACI_QUALIFIED_CCA_DEF 3 245 246 #define HAL_CTRL_ACI_STOMP_FOR_RX_MIN 0 247 #define HAL_CTRL_ACI_STOMP_FOR_RX_MAX 255 248 #define HAL_CTRL_ACI_STOMP_FOR_RX_DEF 2 249 250 #define HAL_CTRL_ACI_STOMP_FOR_TX_MIN 0 251 #define HAL_CTRL_ACI_STOMP_FOR_TX_MAX 255 252 #define HAL_CTRL_ACI_STOMP_FOR_TX_DEF 0 253 254 #define HAL_CTRL_ACI_TX_CCA_MIN 0 255 #define HAL_CTRL_ACI_TX_CCA_MAX 255 256 #define HAL_CTRL_ACI_TX_CCA_DEF 1 257 258 /************************************/ 259 /* Rates values */ 260 /************************************/ 261 262 263 #define BASIC_RATE_SET_1_2 0 264 #define BASIC_RATE_SET_1_2_5_5_11 1 265 266 267 #define BASIC_RATE_SET_UP_TO_12 2 268 #define BASIC_RATE_SET_UP_TO_18 3 269 #define BASIC_RATE_SET_1_2_5_5_6_11_12_24 4 270 #define BASIC_RATE_SET_UP_TO_36 5 271 #define BASIC_RATE_SET_UP_TO_48 6 272 #define BASIC_RATE_SET_UP_TO_54 7 273 #define BASIC_RATE_SET_UP_TO_24 8 274 #define BASIC_RATE_SET_6_12_24 9 275 276 277 /* Keep increasing define values - related to increasing suported rates */ 278 #define SUPPORTED_RATE_SET_1_2 0 279 #define SUPPORTED_RATE_SET_1_2_5_5_11 1 280 #define SUPPORTED_RATE_SET_1_2_5_5_11_22 2 281 #define SUPPORTED_RATE_SET_UP_TO_18 3 282 #define SUPPORTED_RATE_SET_UP_TO_24 4 283 #define SUPPORTED_RATE_SET_UP_TO_36 5 284 #define SUPPORTED_RATE_SET_UP_TO_48 6 285 #define SUPPORTED_RATE_SET_UP_TO_54 7 286 #define SUPPORTED_RATE_SET_ALL 8 287 #define SUPPORTED_RATE_SET_ALL_OFDM 9 288 289 290 /***************************************************************************** 291 ** ** 292 ** ** 293 ** ENUMS ** 294 ** ** 295 ** ** 296 *****************************************************************************/ 297 298 typedef enum 299 { 300 BSS_INDEPENDENT = 0, 301 BSS_INFRASTRUCTURE = 1, 302 BSS_ANY = 2, 303 BSS_AP = 3 304 } bssType_e; 305 306 307 typedef enum 308 { 309 PREAMBLE_LONG = 0, 310 PREAMBLE_SHORT = 1, 311 PREAMBLE_UNSPECIFIED = 0xFF 312 } preamble_e; 313 314 typedef enum 315 { 316 PHY_SLOT_TIME_LONG = 0, 317 PHY_SLOT_TIME_SHORT = 1 318 } slotTime_e; 319 320 typedef enum 321 { 322 NULL_KEY = 0, 323 WEP_KEY, 324 TKIP_KEY, 325 AES_KEY, 326 EXC_KEY, 327 } keyType_e; 328 329 /* make it same as "rate_e" */ 330 typedef enum 331 { 332 REG_RATE_AUTO_BIT = 0, /* This value is reserved if this enum is used for MgmtCtrlTxRate - The auto mode is noly valid for data packets */ 333 REG_RATE_1M_BIT = 1, 334 REG_RATE_2M_BIT = 2, 335 REG_RATE_5_5M_CCK_BIT = 3, 336 REG_RATE_11M_CCK_BIT = 4, 337 REG_RATE_22M_PBCC_BIT = 5, 338 REG_RATE_6M_OFDM_BIT = 6, 339 REG_RATE_9M_OFDM_BIT = 7, 340 REG_RATE_12M_OFDM_BIT = 8, 341 REG_RATE_18M_OFDM_BIT = 9, 342 REG_RATE_24M_OFDM_BIT = 10, 343 REG_RATE_36M_OFDM_BIT = 11, 344 REG_RATE_48M_OFDM_BIT = 12, 345 REG_RATE_54M_OFDM_BIT = 13 346 } registryTxRate_e; 347 348 349 350 351 352 353 #endif /* _WHAL_DEFAULT_PARAMS_H */ 354